FIELD OF INVENTION

The present invention relates to an interfacing circuit and an analog to digital converter for battery monitoring applications. In particular, the present invention provides for a two step noise shaping successive approximation register analog to digital converter to achieve an optimize performance, speed and power consumption.

BACKGROUND ART

In a battery management system of electric vehicles, a high voltage is required due to high stacked cells voltage, and a multi channel high voltage multiplexer with control logic and level shifter is employed in existing interfacing circuits of battery monitoring applications. Various forms of Analog to Digital Converter, ADCs has been utilized and the most commonly utilized form of ADC is Incremental ADC, lADCs, due to its simple implementation of decimation filter with a cascade of counters, easy multiplexing and low latency. IADC comprise of Operational Transconductance Amplifiers OTA. Unlike traditional operational amplifier or op- amps, OTA represent voltage controlled current source and transconductance parameter controlled by an external, amplifier-bias current and expressed as a function of the applied voltage. In addition, OTA employed in the integrators of lADCs consume a considerable amount of power due to static current utilized in achieving high gain and high speed in order to ensure a stable closed loop configuration operation. Incremental ADC or IADC with periodic internal reset are used to cover low frequency signal band and such IADC is not optimal for near simultaneous samples readout. Further, most incremental ADC’s are speed limited to about 20 kHZ or below.

United States Patent No. US 10084467 B1 entitled (hereinafter referred to US 467 B1 Patent) “ADC and an interfacing circuit adaptable thereto”; having a filing date of 3 January 2018; (Applicant: Himax Technologies Ltd NCKU Research and Development Foundation) provides an interfacing circuit in analog to digital conversion. Successive Approximation Register Analog to Digital Converter SAR ADC in US 467 B1 Patent is utilized in order to accommodate high input swing without high voltage device. However, only a single stage of Successive Approximation Analog to Digital Converter SAR ADC is utilized in US 467 B1 Patent. US 467 B1 also provides a general principle of an interfacing circuit adaptable to ADC which includes a sample and hold circuit besides utilizing active device such as operational amplifier.

United States Patent No. US 10103742 B1 entitled (hereinafter referred to US 742 B1 Patent) “Multi-stage hybrid analog-to-digital converter”; having a filing date of 23 January 2018; (Applicant: Hong Kong Applied Science and Technology Research Institute Co Ltd) provides a multi stage hybrid analog to digital converter. In US 742 B1 Patent, analog to digital conversion is performed in multiple steps and it utilized 4 and 8 bit in middle stage of analog to digital conversion. The middle stage in US 742 B1 Patent further utilized a faster flash ADC with multiple comparators to generate middle binary bits. Successive Approximation Register Analog to Digital Converter SAR ADC is utilized as a component in US 742 B1 Patent. However, the SAR ADC is only utilized during first and last stage of analog to digital conversion without noise shaping.

United States Patent No. US 7978117 B2 entitled (hereinafter referred to US 117 B2 Patent) “Multi-stage dual successive approximation register analog-to-digital convertor and method of performing analog-to-digital conversion using the same”; having a filing date of 11 August 2009; (Applicant: Electronics and Telecommunications Research Institute, Korea) provides a multi stage dual Successive Approximation Register Analog to Digital Converter and a method of performing analog to digital conversion. In US 117 B2, analog to digital conversion is performed in a multiple steps. US 117 B2 Patent comprising of pipelined SAR ADC stages and it utilized a residue operational amplifier in order to amplify residue voltage to a next SAR ADC stage.

Due to the limitation of the current circuit interfacing circuit and analog to digital converter ADC for battery monitoring applications, there is a need for an enhanced method to allow performance optimization on resolution, speed and power consumption. SUMMARY OF INVENTION

The present invention relates to an interfacing circuit and an analog to digital converter for battery monitoring applications. In particular, the present invention provides for a two step noise shaping successive approximation register analog to digital converter to achieve an optimize performance, speed and power consumption.

One aspect of the invention provides an interfacing circuit and analog to digital converter for battery monitoring applications (100). The interfacing circuit and an analog to digital converter comprises a plurality of battery cells connected in series (102);at least one sampling circuit (104) for the battery cell (102) corresponding to a cell voltage of at least a subset of the plurality of battery cells (102) of the interfacing circuit; at least one voltage readout circuit (106) for receiving the plurality of battery cells (102) corresponding to the cell voltage of the battery cells (102) and as output of a digital representation of the plurality of battery cells (102). The at least one voltage readout circuit (106) further comprises a first circuitry for a first step coarse analog to digital conversion by performing a fully differential successive of an analog to digital conversion to produce a first conversion known as a coarse result; a second circuitry for a second step fine analog to digital conversion by performing a full differential successive approximation of an analog to digital conversion to produce a second conversion known as a fine result; and a third circuitry for performing noise shaping by utilizing a passive integrator.

Another aspect of the invention provides that the at least one sampling circuit (104) for the plurality of battery cells (102) corresponding to a cell voltage of at least a plurality of battery cells (102) of the interfacing circuit and analog to digital converter for battery monitoring applications (100) comprises a plurality of high voltage input switches (104a) corresponding to at least a plurality of battery cells (102); at least one input capacitor (104b) having a first end connected to the plurality of high voltage switches (104a) and a second end connected to an input of the analog to digital converter through a sampling switch (104c); at least one hold switch (104d) connected between the second end of the at least one input capacitor (104b) and the common-mode voltage (104e); at least one level shift capacitor (104f) connected between the second end of input capacitor (104b) and the common mode voltage (104e); at least one level shift switch (104g) connected between a level shift voltage plus common-mode voltage (104e) potential at one end and a level shift capacitor (104f) at another end; and at least one front end switch (104h) connected between one end of the level shift capacitor (104f) and a ground potential (104i).

A further aspect of the invention provides that the first circuitry comprises a first Digital to Analog Converter, DAC known as coarse DAC (302) having a first input for receiving an analog input; a second input for receiving a first reference voltage; a third input for receiving a second reference voltage; a fourth input for receiving a third reference voltage; and an output.

Yet another aspect of the invention provides that the second circuitry comprises a second Digital to Analog Converter, DAC known as fine DAC (306) having a first input for receiving a first reference voltage input; a second input for receiving a second reference voltage; a third input for receiving a third reference voltage; and an output.

A further aspect of the invention provides that the fine DAC (306) comprises at least one positive top node sharing with at least one positive top node of coarse DAC (302); at least one negative top node sharing with at least one negative top node coarse DAC (302); a first comparator having a first input coupled to the at least one positive top node of the at least one coarse DAC (302) and the fine DAC (306); and an output for providing a comparison result between the coarse DAC (302) and the fine DAC (306).

Another aspect of the invention provides that the third circuitry comprises a plurality of multi input comparator with one input shared with a positive top node of coarse DAC (302) and fine DAC (306); at least one input sharing with a negative top node of coarse DAC (302) and fine DAC (306); and at least one passive integrator having at least two capacitors.

A further aspect of the invention provides method (600) for interfacing circuit and an analog to digital conversion for battery monitoring applications by connecting a plurality of battery cells in series (602); corresponding of at least one sampling circuit for the battery cells to a cell voltage of at least a subset of the plurality of battery cells of the interfacing circuit (604); receiving the cell voltage of the plurality of battery cells as output of a digital representation of the plurality of battery cells by at least one voltage readout circuit (606); and performing a two step noise shaping successive approximation of an analog to digital conversion by at least one voltage readout circuit (608). The step for performing a two step noise shaping successive approximation of an analog to digital conversion by at least one voltage readout circuit comprises steps of (700) performing a first full differential successive approximation for an analog to digital conversion by using a first digital to analog converter known as coarse DAC and at least one comparator (702); producing at least one coarse digital result (704); performing an initialization of a second full differential successive approximation for an analog to digital conversion by using a second digital to analog converter known as fine DAC (706) based on a digital result from the first full differential successive approximation of analog-to-digital conversion; performing a second full differential successive approximation of analog to digital conversion by using a second digital to analog converter known as fine DAC and the at least one comparator for producing at least one fine digital result (708); and combining the coarse digital result and the fine digital result for producing at least one conversion result (710).

Still another aspect of the invention provides that combining the coarse digital result and the fine digital result comprises steps of (800) converting the coarse digital result and the fine digital result simultaneously if sample signal is on (804); converting six most significant bits by the analog digital converter if sample signal is off (806); sending the output to an alignment control circuit (808); converting six least significant bits by 12-bit analog to digital converter to obtain a 12- bit digital data after a set latency (810); and performing noise shaping at least on one residue left on top the node of differential digital to analog converter of a successive approximation analog to digital converter (812).

Another aspect of the invention provides that producing the at least one fine digital result comprises steps of (900) determining a first digital output based on a first analogue residue input by at least one passive integrator (902); obtaining a first quantization error for a first digital input (904); integrating the first quantization error for a first digital output (906); generating the first integrated quantization error (908); receiving a second analog residue input (910); and determining a second digital output through noise-shaping (912).

A further aspect of the invention provides that performing noise shaping at least on one residue left on top the node of differential digital to analog converter of a successive approximation analog to digital converter (812) comprising summation of second analog input; first integrated quantization error by at least one passive integrator, and second integrated quantization error.

The present invention consists of features and a combination of parts hereinafter fully described and illustrated in the accompanying drawings, it being understood that various changes in the details may be made without departing from the scope of the invention or sacrificing any of the advantages of the present invention.

BRIEF DESCRIPTION OF ACCOMPANYING DRAWINGS

To further clarify various aspects of some embodiments of the present invention, a more particular description of the invention will be rendered by references to specific embodiments thereof, which are illustrated in the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. The invention will be described and explained with additional specificity and detail through the accompanying drawings in which:

Fig. 1.0 illustrates a general architecture of a single ended version of analog to digital converter, ADC of the present invention.

Fig. 1.0a illustrates a timing block diagram for single ended version of analog to digital converter, ADC of the present invention.

Fig. 2.0 illustrates a simplified block diagram of an analog to digital converter, ADC of the present invention. Fig. 3.0 illustrates schematic of a two step SAR ADC of the present invention.

Fig. 4.0 illustrates binary weighted 12-bit DAC.

Fig. 4.0a illustrates binary weighted 6-bit DAC.

Fig. 5.0 illustrates application of low energy consuming technique in the present invention. Fig. 6.0 is a flowchart illustrating a general methodology of analog to digital conversion of the present invention

Fig. 7.0 is a flowchart illustrating steps of combining coarse digital result and fine digital result of the present invention

Fig. 8.0 is a flowchart illustrating steps of producing fine digital result of the present invention. DETAILED DESCRIPTION OF THE DRAWINGS

The present invention provides an interfacing circuit and analog digital converter ADC architecture with a two step noise shaping successive approximation register analog to digital converter. The two step noise shaping successive approximation register analog to digital converter of the present invention having a front end interface for digital conversion of each single voltage in order to achieve an optimize performance, speed and power consumption. Hereinafter, this specification will describe the present invention according to the preferred embodiments. It is to be understood that limiting the description to the preferred embodiments of the invention is merely to facilitate discussion of the present invention and it is envisioned without departing from the scope of the appended claims.

Reference is first made to FIG. 1.0. FIG. 1.0 illustrates a general architecture of a single ended version of analog to digital converter, ADC of the present invention. An interfacing circuit and an analog to digital converter for battery monitoring applications (100) comprising a plurality of battery cells connected in series (102); at least one sampling circuit (104) for the battery cell (102) corresponding to a cell voltage of at least a subset of the plurality of battery cells (102) of the interfacing circuit and at least one voltage readout circuit (106) for receiving the plurality of battery cells (102) corresponding to the cell voltage of the plurality of battery cells (102) and as output of a digital representation of the plurality of battery cells (102). The at least one sampling circuit (104) for the battery cell corresponding to a cell voltage of at least a subset of battery cells (102) of the interfacing circuit further comprises a plurality of high voltage input switches (104a) corresponding to at least a subset of battery cells (102), at least one input capacitor (104b) with a first end connected to the plurality of high voltage switches (104a) and with a second end connected to an analog to digital converter input through a sampling switch (104c), at least one hold switch (104d) connected between second end of input capacitor (104b) and a common-mode voltage (104e), at least one level shift capacitor (104f) connected between the second end of input capacitor (104b) and the common mode voltage (104e), at least one level shift switch (104g) connected between a level shift voltage plus common-mode voltage (104e) potential at one end and level shift capacitor (104f) at the other end, and at least one front end switch (104h) connected between one end of level shift capacitor (104f) and ground potential (104i).

The at least one voltage readout circuit (106) further comprising a first circuitry for a first step coarse analog to digital conversion by performing a fully differential successive of an analog to digital conversion to produce a first conversion known as a coarse result, a second circuitry for a second step fine analog to digital conversion by performing a full differential successive approximation of an analog to digital conversion to produce a second conversion known as a fine result, and a third circuitry for performing noise shaping by utilizing a passive integrator.

The single ended version of analog to digital converter, ADC of the circuitry of the present invention is a switched-capacitor circuit combined with the differential digital to analog converter, DAC of successive approximation register analog to digital converter SAR ADC in order to attenuate the input swing. A single high voltage capacitance, Cs works as sampling element for all the 8 channels of high voltage input switches (104a). A capacitor, Ccm which is nominally equal to Cs and implemented as high-voltage, provide a shift voltage equal to 3.6V so that a reference voltage of ±0.6V makes the conversion range from 3 to 4.2V. Fig. 1.0a illustrates a timing block diagram for single ended version of analog to digital converter, ADC of the present invention.

Reference is now made to FIG. 2.0 which illustrates a simplified block diagram of an analog to digital converter, ADC of the present invention. The analog digital converter comprises of at least one high voltage section (202) and at least one low voltage section (204). The high voltage section (202) comprising a plurality of battery cells (102)and at least one high voltage track and hold. Two steps noise shaping successive approximation analog to digital converter is employed in the low voltage section (204).

Reference is now made to FIG. 3.0 which illustrates schematic of the low voltage section operation (300). The low voltage section (300) operation comprises at least one six bits coarse successive approximation analog to digital converter (302); at least one aligned control circuit (304); and at least one 12 bits fine successive approximation analog to digital converter with 2 to 4 bits noise shaping (306). The analog to digital converter (302) operates on a single clock signal according to sample signal which determines the conversion speed. If the sample signal is on (702), coarse digital result and fine digital result are converted simultaneously. Flowever, if sample signal is off, six most significant bits conversion is performed by coarse analog to digital converter. After the six most significant bits are determined, it is sent to the alignment control circuit which sets the initial operation of fine analog to digital converter. After a set latency, six least significant bits are converted by 12-bit fine analog to digital converters to obtain 12-bit digital data. After 12-bit digital data is done, the residue left on the top node of the differential digital to analog converter, DAC of successive approximation register analog to digital converter is will be further noise shaped by a passive integrator. This noise-shaping operation results in an additional 2 - 4 bits extra resolution depending on optimization of noise transfer function, NTF of the noise shaping operation.

The first circuitry comprising a first digital to analog converter, DAC known as coarse DAC (302) having a first input for receiving an analog input, a second input for receiving a first reference voltage, a third input for receiving a second reference voltage, a fourth input for receiving a third reference voltage; and an output. The second circuitry comprising a second digital to analog Converter, DAC known as fine fine DAC (306) having a first input for receiving a first reference voltage input, a second input for receiving a second reference voltage, a third input for receiving a third reference voltage; and an output. The fine DAC comprising at least one positive top node sharing with at least one positive top node of coarse DAC (302), at least one negative top node sharing with at least one negative top node coarse DAC (302), a first comparator having a first input coupled to the at least one positive top node of the at least one and the fine DAC (306), and an output for providing a comparison result between the coarse DAC (302) and the fine DAC (306).

The third circuitry comprising a plurality of multi input comparator with one input shared with a positive top node of coarse DAC (302) and fine DAC (306), at least one input sharing with a negative top node of coarse DAC (302) and fine DAC (306), and at least one passive integrator having at least two capacitors.

Reference is now made to FIG. 4.0 and FIG 4.0a respectively. Fig. 4.0 illustrates binary weighted 12-bit digital analog conversion. If 12-bit binary weighted digital analog conversion is used, large capacitor size is required and as a result, high power is consumed due to high switching energy.

As illustrated in FIG. 4.0a, a binary weighted 6-bit digital analog conversion is utilized. As a result, switching energy significantly reduced due to a low-resolution successive approximation register for analog to digital conversion, SAR ADC.

FIG. 5.0 further illustrates application of low energy consuming technique in the present invention. FIG. 5.0 illustrates switching last low significant bit cap to Vcm instead of normally to Vrefp or Vrefm in order to reduce the bit cycling sequence by 1 step or 1 bit. As a result, the bit cycling only need to be performed for 10 times instead of conventionally 12 times for 12 bits successive approximation register for analog to digital conversion, SAR ADC.

Reference is now made to FIG. 6.0 which illustrates a general methodology of analog to digital conversion. The steps starts by connecting a plurality of battery cells in series (602) corresponding of at least one sampling circuit for the battery cells to a cell voltage of at least a subset of the plurality of battery cells (102) of the interfacing circuit (604). Next, receiving the cell voltage of the plurality of battery cells as output of a digital representation of the plurality of battery cells by at least one voltage readout circuit (606) and performing a two step noise shaping successive approximation of an analog to digital conversion by at least one voltage readout circuit (608).

As illustrated in FIG 7.0 performing a two step noise shaping successive approximation of an analog to digital conversion by at least one voltage readout circuit (608) further comprising steps of (700) performing a first full differential successive approximation for analog to digital conversion by coarse ADC and at least one comparator 702for producing at least one coarse digital result (704). Next, an initialization of a second differential successive approximation for analog to digital conversion is performed by fine ADC (706) based on digital result from the first fully differential successive approximation of analog-to-digital conversion. A second full differential successive approximation of analog to digital conversion further performed fine ADC and the at least one comparator for producing one fine digital result is produced (708). Coarse digital result and fine digital result are combined in order to produce at least one conversion result (710).

Reference is now made to Fig. 8.0 which illustrates the steps for combining coarse digital result and fine digital result. The steps start by determining sample signal from analog to digital conversion (802). If the sample signal is on, coarse and fine analog digital converter convert sample simultaneously (804). Flowever, if the sample signal is off, 6 Most Significant Bits (MSBs) is converted by analog digital converter (806) and the output is further send to alignment control circuit (808). In order to obtain 12- bit digital data after a set of latency, 6 Least Significant Bits (LSBs) is converted by analog digital converter (810). As a result of the conversion, the residue left on the top node of the differential digital analog converter of successive approximation for analog to digital conversion SAR ADC will be noise shaped (812) by a passive integrator. This noise-shaping operation results in an additional 2 - 4 bits extra resolution depending on optimization of noise transfer function (NTF) of the noise shaping operation.

FIG. 9.0 illustrates the steps for producing fine digital result. Initially, a first digital output is determined based on a first analogue residue input by at least one passive integrator (902). Next, a first quantization error for first digital output is obtained (904) and the first quantization error is further integrate in order to produce a first integrated quantization error by at least one passive integrator (906). Upon generating the first integrated quantization error (908), second analog residue input is received (910). Second digital output is further determined via noise-shaping (912). In the present invention, two step noise shaping successive approximation analog to digital converter is employed whereby first step coarse and second step fine analog to digital conversion followed by noise shaping by utilizing a passive integrator. Throughout this specification, unless the context requires otherwise, the word “comprise”, or variations such as “comprises” or “comprising”, will be understood to imply the inclusion of a stated step or element or integer or group of steps or elements or integers, but not the exclusion of any other step or element or integer or group of steps, elements or integers. Thus, in the context of this specification, the term “comprising” is used in an inclusive sense and thus should be understood as meaning “including principally, but not necessarily solely”.