TECHNICAL FIELD

The present invention relates to clock recovery devices in digital communications systems.

BACKGROUND

In order to successfully detect and decode modulated data symbols in a digital communications system, it is necessary to accurately synchronize the local sampling clock (also known as clock recovery) in the receiver to that of the transmitter. If the local sampling clock is not properly synchronized then the performance of the communications system may be severely degraded.

Several devices for clock recovery have been suggested in literature.

However, a common denominator of the clock recovery devices in literature is that their performance is limited by the presence of strong external interference resulting in that accurate synchronization cannot be achieved.

Interference sensitive clock recovery devices which are used in strong interference conditions must therefore be protected from the interference, e.g., by the application of interference countermeasures in the receiver prior to clock recovery. However, such interference countermeasures have been shown to limit the resilience of the communications receiver to certain types of receiver noise, e.g., phase noise. Thus, there is a need for a clock recovery device which is robust to interference, since, such a clock recovery device would obviate the need to apply interference countermeasures in the receiver prior to clock recovery.

SUMMARY It is an object to provide an interference robust clock recovery device.

This object is addressed by the present invention in that it discloses a clock recovery device arranged to receive a communications signal and to also receive a first and a second clock input signal as well as a control signal and a data signal. The clock recovery device also comprises means for sampling the received communications signal at a rate based on a clock error signal in order to create a sampled communications signal which is arranged to be an output of the clock recovery device.

The clock recovery device also comprises a first means for clock error detection arranged to create a first clock error signal based on the first clock input signal. In addition, the clock recovery device also comprises a second means for clock error detection arranged to create a second clock error signal based on the second clock input signal and on the data signal.

The clock recovery device further comprises a switch arranged to select the first or the second clock error signal to be the clock error signal of the means for sampling and a control unit arranged to control said switch based on the control signal.

In embodiments, the first means for clock error detection comprises a data- agnostic clock error detector arranged to receive the first clock input signal, and to output a detected error signal to a low-pass filter comprised in the first means for clock error detection. The low-pass-filter is arranged to low-pass filter the detected error signal to create the first clock error signal, which first clock error signal is arranged to be an output signal of the first means for clock error detection. In embodiments, the data agnostic clock error detector comprises a Gardner clock error detector.

In embodiments, the data agnostic clock error detector comprises a Mueller and Muller clock error detector.

In embodiments, the second means for clock error detection comprises a data-aided clock error detector arranged to receive the second clock input signal as well as the data signal. The data-aided clock error detector also comprises a delay unit arranged to delay the second clock input signal by a pre-determined amount to create a delayed second clock input signal.

The data-aided clock error detector further comprises a first and a second correlator device. The first correlator device is arranged to correlate the data signal with the second clock input signal, and the second correlator device is arranged to correlate the data signal with the delayed second clock input signal. These two correlations are determined in order to create a first and a second correlation output signal, from the first and the second correlator device, respectively.

The data-aided clock error detector further comprises a comparison device arranged to determine the absolute value of the first and the second correlation output signal. The comparison device is arranged to determine a difference between the absolute value of the first correlation output signal and the absolute value of the second correlation output signal, and to output a correlation difference signal based on the determined difference.

The second means for clock error detection also comprises a low-pass filter arranged to receive and to low-pass filter said correlation difference signal. The low-pass filtered correlation difference signal is arranged to be output from the second means for clock error detection as the second clock error signal.

It should be noted that both data-agnostic and data-aided clock error detectors may be implemented in a number of different ways. The disclosed clock recovery device should therefore not be construed as being limited to the clock error detector embodiments set forth herein.

In embodiments, the received communications signal is an analog signal and the means for sampling the received communications signal comprises an analog to digital converter, ADC, arranged to sample the analog received communications signal in order to create and to output the sampled communications signal. The sampling rate of said ADC is arranged to be controlled by means of the clock error signal.

In embodiments, the received communications signal is a sampled digital signal and the means for sampling the received communications signal comprises an interpolator filter arranged to resample the received digital communications signal in order to create and to output the sampled communications signal. The sampling rate and sampling time offset of the sampled communications signal output from the interpolator filter is arranged to be controlled by means of the clock error signal.

In embodiments, the control signal can assume the two states 'true' and 'false', and the control unit is arranged to control the switch such that the first clock error signal is selected when the control signal is in the 'false' state, and the second clock error signal is selected when the control signal is in the 'true' state. To exemplify, the control signal mentioned above may in embodiments be a receiver lock signal generated by a communications receiver comprising the disclosed clock recovery device. A 'true' state of the control signal then indicates that the receiver is operating in locked mode, and a 'false' state of the control signal indicates that the receiver operates in unlocked mode.

The above stated object is also obtained by means of a method for clock recovery, comprising the steps of:

• receiving a communications signal;

· receiving a first and a second clock input signal;

• receiving a control signal as well as a data signal;

• detecting a first clock error based on the first clock input signal, and creating a first clock error signal by means of the detected first clock error;

· detecting a second clock error based on the second clock input signal and on the data signal and creating a second clock error signal by means of the detected second clock error;

• selecting, based on the control signal, the first or the second clock error signal to be a selected clock error signal;

· sampling the received communications signal at a sampling rate determined by means of the selected clock error signal in order to create a sampled communications signal.

In embodiments of the clock recovery method, the step of detecting a first clock error based on the first clock input signal and creating a first clock error signal by means of the detected first clock error comprises the steps of:

• applying a data-agnostic clock-error detection method to the first clock input signal in order to create the first clock error, and

• low-pass filtering the first clock error in order to create the first clock error signal. In embodiments of the clock recovery method, the step of detecting a second clock error based on the second clock input signal and on the data signal and creating a second clock error signal by means of the detected second clock error comprises the steps of:

• using a data-aided clock error detection method which comprises correlating the data signal with the second clock input signal in order to create a first correlation output signal and

• correlating the data signal with a second clock input signal which is delayed by a pre-determined amount, in order to create a second correlation output signal,

wherein the data-aided clock error detection method further comprises the steps of:

• determining and comparing the absolute values of the first and second correlation output signals in order to create a correlation difference signal, and

• using said correlation difference signal as the detected second clock error, and

• low-pass filtering of the detected second clock error in order to obtain the second clock error signal.

In embodiments of the clock recovery method, the received communications signal is an analog signal and the step of sampling the received communications signal comprises analog to digital conversion of the received communications signal, with the sampling being performed at a rate controlled by means of the selected clock error signal.

In embodiments of the clock recovery method, the received communications signal is a sampled digital signal and the step of sampling the received communications signal comprises the step of interpolation filtering of the received communications signal, with the sampling rate and sampling offset of the received communications signal after said interpolation filtering being controlled by means of the selected clock error signal. In embodiments of the clock recovery method, the control signal is a receiver lock signal generated by a communications receiver. The receiver lock signal can assume the two states 'true' and 'false', and the step of selecting the first or the second clock error signal to be the selected clock error signal comprises selecting the first clock error signal when the receiver lock signal is in the 'false' state, and selecting the second clock error signal when the control signal is in the 'true' state.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be described in more detail in the following, with reference to the appended drawings, in which

Fig 1 shows an example of a digital communications receiver with clock recovery according to prior art, and

Fig 2 shows an embodiment of a clock recovery device, and

Fig 3 shows a first embodiment of a clock error detector for use in a clock recovery device, and

Fig 4 shows a second embodiment of a clock error detector for use in a clock recovery device, and

Fig 5 shows a communications receiver comprising a clock recovery device of the invention, and

Fig 6 shows a flowchart of a method of the invention.

DETAILED DESCRIPTION

Embodiments of the present invention will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. The invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Like numbers in the drawings refer to like elements throughout.

The terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the invention.

In order to make differences between prior art and the present invention clear, and to provide a better understanding of the benefits associated with the disclosed invention compared to the prior art, a digital communications receiver comprising a clock recovery device according to prior art will first be described, following which a detailed description of the present invention will be given.

Fig 1 shows a digital communications receiver 100 according to prior art. A received communications signal 101 is an input signal to a means 1 10 for sampling the received communications signal 101 , which means 1 10 for sampling generate a sampled communications signal 103. The means 1 10 for sampling is controlled in sampling rate and possibly also in sampling time offset by means of a clock recovery device comprising a clock error detector 170, shown in fig 1 as a Gardner detector 170 and a clock loop filter 180, which suitably comprises a low-pass filter for suppressing noise in the clock error detector 170 output signal, since interference in the received communications signal 101 will affect the output signal from the clock error detector 170 and cause a sub-optimal sampling of the received communications signal 101.

In order to prevent degraded sampling due to interference, an interference suppression device 190 is comprised in the digital communications receiver suppress interference in the sampled communications signal 103, prior to clock recovery, by means of a reference signal 102, a first adaptive filter 130, and a first signal adder 140.

After interference suppression by the interference suppression device 190, the received signal is filtered by a second adaptive filter 150 followed by detection of information symbols in the received signal by a detector device 160. The detector device 160 is also arranged to generate a detection error signal 161 , which is fed back in the receiver and arranged to be an input signal to the first 130 and the second 150 adaptive filters. The transfer functions of the first 130 and the second 150 adaptive filter are continuously updated by means of the detection error signal 161. One way of determining a detection error signal, such as the detection error signal 161 in fig 1 , is to take the value of the input signal to the detector device and subtract the corresponding value of the detected information symbol. In general, an interference suppression device, such as the interference suppression device 190 shown in fig 1 , is able to suppress interference in a received communications signal by using an adaptive filter, such as the adaptive filter 130, as long as there exist correlation between the interference present in the received communications signal and the received reference signal.

There are several methods available in literature for the updating of adaptive filter transfer functions by means of a detection error signal, examples of which include the least mean squares, LMS, and recursive least squares, RLS, methods. A problem with the digital communications receiver 100 of fig 1 is the potentially large loop delay in the loop for adapting the first adaptive filter 130, marked as 'LOOP delay' in fig 1. If this delay is large, the first adaptive filter 130 cannot be adapted fast enough to compensate for rapid changes in e.g., phase difference between the reference signal 102 and the received communications signal 101. This leads to a reduced resilience to, e.g., phase noise, in the digital communications receiver 100. Fig 2 shows a schematic view of a clock recovery device 200. A received communications signal 101 is arranged to be an input signal to a means 210 for sampling the received communications signal 101 , which means 210 for sampling is arranged to output a sampled communications signal 103. The means 210 for sampling is controlled by means of a clock error signal 221 which is arranged to be received by the means 210 for sampling from a switch 220 comprised in the clock recovery device 200.

The clock recovery device 200 shown in fig 2 also comprises two clock error detectors, shown in fig 2 as a first 240 and a second 230 clock error detector, respectively. The first 240 and second 230 clock error detectors are arranged to generate and output first 241 and second 231 clock error signals, respectively.

The first clock error detector 240 is arranged to generate the first clock error signal 241 by means of a first clock input signal 242 which first clock input signal 242 is arranged to be an input signal of the clock recovery device 200. The second clock error detector 230 is arranged to generate the second clock error signal 231 by means of a second clock input signal 233 as well as a data signal 232. The second clock input signal 233 and the data signal 232 are both arranged to be input signals of the clock recovery device 200. The clock error signal 221 of the means 210 for sampling is selected to be either the first 241 or the second 231 clock error signal by the comprised switch 220, which switch 220 is arranged to be controlled by a control unit 250. The control unit 250 is arranged to receive a control signal 251 , which control signal 251 is arranged to be an input signal of the clock recovery device 200, and to base its control of the switch 220 on the control signal 251. It should be noted that more than two clock error detectors may potentially be comprised in the clock recovery device 200, in which case the switch 220 is arranged to select between more than two input signals, and the control unit 250 is arranged to control the switch 220 to select between the at least two input clock error signals based on the received control signal 251.

Suitably, the control signal 251 carries information regarding which of the first clock input signal 242, the second clock input signal 233, and the data signal 232 that are valid in the sense that they are suitable to be used for clock recovery. An example of a suitable control signal is a receiver lock signal which is generated by a communications receiver comprising the clock recovery device 200. In case the communications receiver is not operating in locked mode, the data signal 232 is most likely not valid since no data can be extracted from the received communication signal 101 when the communications receiver is in unlocked mode. Consequently, when the data signal 232 is not valid, the first clock error signal 241 is preferred and thus selected by the switch 220, since the second means for clock recovery 230 most likely cannot provide a valid clock error signal 231.

In embodiments, the received communications signal 101 is an analog signal, in which case the means 210 for sampling suitably comprises an analog to digital converter, ADC. The sampling rate of the ADC is preferably arranged to be controlled by means of the clock error signal 221.

In further embodiments, the received communications signal 101 is a received sampled digital signal, in which case the means 210 for sampling suitably comprises an interpolation filter arranged to resample the received sampled digital signal at a rate and with a time offset determined by means of the clock error signal 221. Several methods exist for the re-sampling of a sampled digital signal, one example being a Farrow interpolator filter.

Fig 3 shows an embodiment of the first clock error detector 240. The first clock error signal 241 is in this embodiment generated by means of low-pass filtering, by a low-pass filter 245, of the output signal 244 from a data- agnostic clock error detector 243 which is arranged to receive the first clock input signal 242 as an input signal.

A data-agnostic clock error detector, such as the one shown in fig 3, is a clock error detector which generates a clock error signal by means of a clock input signal without making use of any data information carried by the clock input signal. Examples of data-agnostic clock error detectors from literature are the Gardner clock error detector, and the Mueller and Muller clock error detector. A low-pass filter, such as the low-pass filter 245 shown in fig 3, is often connected in series with the clock error detector in order to suppress high frequency noise in the detected clock error signal.

Fig 4 shows an embodiment of the second clock error detector 230. In this embodiment the second clock error signal 231 is arranged to be generated by means of low-pass filtering, by a low-pass filter 350, a correlation difference signal 341 which is arranged to be an output signal from a data- aided clock error detector 300 comprised in the second clock error detector 230. The data-aided clock error detector 300 shown in fig 4 is arranged to generate the input signal 341 to the low-pass filter 350 by means of the second clock input signal 233 as well as the data signal 232 which signals 232, 233 are arranged to be input signals of the data-aided clock error detector 300.

In general, a data-aided clock error detector is a clock error detector which exploits data or other structures present in the clock input signal. The exploited data is often information symbols, or pilot symbols, that are present in the input signals of the data-aided clock error detector. It should be noted that data-aided clock error detectors can be implemented in many different ways. The embodiment of the data-aided clock error detector 300 shown in fig 4 is merely one example of such a device.

In the embodiment of the second clock error detector 230 shown in fig 4, it is assumed that modulation symbols are present in the second clock input signal 233, and that reference modulation symbols are present in the data signal 232, and that the target sampling rate of the means 210 for sampling is two samples per symbol.

The data-aided clock error detector 300 comprises a delay unit 310 arranged to delay the second clock input signal 233 by a predetermined amount to create a delayed second clock input signal 31 1. This pre-determined amount of delay is suitably a fraction of the modulation symbol duration, and the delay applied in delay unit 310 must not exceed a duration of one modulation symbol.

A first 320 and a second 330 correlator device are also comprised in the data-aided clock error detector 300. The first 320 and second 330 correlator devices are arranged to correlate the data signal 232 with the second clock input signal 233 and with the delayed second clock input signal 31 1 , respectively. The result of which are a first 321 and a second 331 correlation signal outputted from the first correlation device 320 and from the second correlation device 330, respectively. The absolute values of the correlation signals indicate to what extent the second clock input signal 233 is time aligned with the data signal 232, and to what extent the delayed second clock input signal 31 1 is time aligned with the data signal 232. Now, by what is commonly referred to in literature as the early-late gate principle, a clock error in the second clock input signal 233 can be determined by taking the difference between the absolute value of the first correlation signal 321 and the absolute value of the second correlation signal 331 , i.e.

D [t] = abs(Cl [t]) - abs(C2 [t]), where t is a time index, D is said correlation difference signal, abs() denotes the absolute value, C1 [t] is the first correlation signal 321 , and C2[t] is the second correlation signal 331. It should be noted that in embodiments, the data signal 232 and the second clock input signal 233 may be complex signals, in which case the first 320 and second 330 correlator devices are arranged to be complex correlator devices and to generate complex output signals. In further embodiments the data signal 232 and the second clock input signal 233 may be real signals, in which case the first 320 and second 330 correlator devices are arranged to be real correlator devices and to generate real output signals.

Fig 5 shows a communications receiver 400 of the invention. The clock recovery device 200 shown in fig 2 and described in connection with that drawing is comprised in the communications receiver 400 and arranged to receive a communications signal 101 and to output a sampled communications signal 103 for further processing by the communications receiver 400. The communications receiver 400 comprises a delay unit 120 arranged to delay, by a pre-determined amount, the sampled communications signal 103 to create a delayed sampled communications signal 121.

The purpose of the delay unit 120 is to time-align the sampled communications signal 103 with a reference signal 102 arranged to be an input signal to a first interference suppression device 401. The reference signal 102 is preferably correlated with the interference present in the received communications signal 101. The first interference suppression device 401 is arranged to receive the reference signal 102, to filter the reference signal 102 by a first adaptive filter 130, to multiply the filtered reference signal 130 by a weighting multiplier 410, and to add, by a first signal adder 140, the result to the delayed sampled communication signal 121 , in order to suppress interference in the sampled communications signal 103 and output a signal processed sampled communications signal 141.

The second clock input signal 233 of the clock recovery device 200 is arranged to be the delayed sampled communication signal 121 , i.e., the received signal prior to interference suppression by the first interference suppression device 401. The first clock input signal 242 of the clock recovery device 200 is arranged to be the output signal from the first signal adder 140, i.e., the signal processed sampled communications signal 141. The signal processed sampled communications signal 141 is also arranged to be an input signal of a second interference suppression device 450 arranged to further suppress interference in the received signal. The second interference suppression device 450 is arranged to generate a detector signal 431 as an output signal by means of a second 150 and a third 420 adaptive filter as well as a second signal adder 430 and the filtered reference signal 131.

The second interference suppression device 450 is arranged to add, by the second signal adder 430, the output of the second 150 and third 420 adaptive filters, to create the detector signal 431. The second adaptive filter 150 is arranged to filter the signal processed sampled communications signal 141 , and the third adaptive filter 420 is arranged to filter the filtered reference signal 131.

The communications receiver 400 also comprises a detector device 160 arranged to receive the detector signal 431 and to detect information symbols in the detector signal 431. The detector unit 160 is also arranged to generate a detection error signal 160 which is fed back in the receiver and arranged to be an input signal of the first 130, the second 150, as well as the third 420 adaptive filter. The transfer functions of the first 130, second 150, and third 420 adaptive filters are arranged to be updated by means of the detection error signal 161. As mentioned in connection to fig 1 , there are several methods available in literature for the updating of adaptive filter transfer functions by means of a detection error signal, examples of which include the least mean squares, LMS, and recursive least squares, RLS, methods. The detector unit 160 is also arranged to generate the data signal 232 of the clock recovery device 200. The data signal 232 generated by the detector device 160 comprises detected modulation symbols, and potentially also pilot symbol information.

The communications receiver 400 further comprises a lock detect device 440 arranged to generate a receiver lock signal, which receiver lock signal is arranged to be the control signal 251 of the clock recovery device 200. In embodiments, the receiver lock signal is suitably arranged to enter a 'true' state when the magnitude of the detection error signal 161 is below a predetermined threshold indicating that the communications receiver 400 is operating in locked mode, and to enter a 'false' state otherwise, indicating that the communications receiver 400 is operating in unlocked mode.

In embodiments, the communications receiver 400 schematically shown in fig 5 is initialized in unlocked mode. In unlocked mode, the detector unit 160 is not able to detect any information in the detector signal 431 , hence the data signal 232 is not valid, which is indicated by the receiver lock signal 251 being in the 'false' state since the detection error signal 161 is likely to be of large magnitude. The clock recovery device 200 will therefore control the means 210 for sampling based on the first clock error detector 240.

In embodiments of the clock recovery device 200, the first clock error detector 240 comprises a data-agnostic clock error detector 243 which need to be protected from interference. Thus, the weighting multiplier 410 is set to one during unlocked mode, which causes the first interference suppression device 401 to suppress interference prior to clock recovery by the clock recovery device 200. As soon as the detection error signal 161 goes below the pre-determined threshold, the communications receiver 400 can be said to have entered a locked mode of operation. Consequently, the data signal 232 now contains valid reference data, the control signal 251 enters its 'true' state, and the clock recovery device 200 switches, by means of the switch 220, from the first clock error signal 241 to the second clock error signal 231 , which second clock error signal 231 in embodiments comprises a data-aided clock error detector 300. When the communications receiver 400 operates in locked mode, the weight applied by the weighting multiplier 410 (marked as W in fig 5) is gradually reduced from one down to a pre-determined value between zero and one, preferably on the order of 0.2. This gradual reduction of weight W means that less interference suppression is done early, by the first interference suppression device 401 , in the receive chain of the communications receiver 400, and more interference suppression is done later in the receive chain of the communications receiver 400, by the second interference suppression device 450. As a consequence, the overall effective loop delay, marked as 'LOOP delay' in fig 5, is significantly shorter when the receiver is operating in locked mode as compared to the prior art communications receiver 100 shown in fig 1 and described in connection with that figure. Hence the communications receiver 400 shown in fig 5 can be expected to be able to handle larger amounts of, e.g., phase noise, than the prior art communications receiver 100 shown in fig 1.

Fig 6 shows a flow chart of a method 600 of the invention for use in a clock recovery device. As shown in step 610, the method 600 comprises receiving a communications signal. As shown in step 615, the method 600 also comprises receiving a first and a second clock input signal, and step 620, receiving a control signal, and a data signal. As shown in step 630, the method 600 comprises detecting, by means of the first clock input signal, a first clock error, and creating a first clock error signal based on the detected first clock error. In embodiments, the step 630 is suitably accomplished by means of a data-agnostic clock error detection method.

As shown in step 640, the method 600 also comprises detecting, by means of the second clock input signal and the data signal, a second clock error, and creating a second clock error signal based on the detected second clock error. In embodiments, the step 640 is suitably accomplished by means of a data-aided clock error detection method.

As shown in step 650, the method 600 comprises selecting, based on the state of a control signal, the first or the second clock error signal to be a selected clock error signal.

As shown in step 660, the method also comprises sampling the received communications signal at a sampling rate determined by means of the selected clock error signal.

In embodiments of the clock recovery method, 600, the step 630 of detecting a first clock error based on the first clock input signal and creating a first clock error signal by means of the detected first clock error comprises the steps of:

· applying a data-agnostic clock-error detection method to the first clock input signal in order to create the first clock error , and

• low-pass filtering the first clock error in order to create the first clock error signal. In embodiments of the clock recovery method 600, the step 640 of detecting a second clock error based on the second clock input signal and on the data signal and creating a second clock error signal by means of the detected second clock error comprises the steps of:

· using a data-aided clock error detection method which comprises correlating the data signal with the second clock input signal in order to create a first correlation output signal and

• correlating the data signal with a second clock input signal which is delayed by a pre-determined amount, in order to create a second correlation output signal,

with the data-aided clock error detection method further comprising the steps of:

• determining and comparing the absolute values of the first and second correlation output signals in order to create a correlation difference signal, and

• using said correlation difference signal as the detected second clock error, and

• low-pass filtering of the detected second clock error in order to obtain the second clock error signal.

In embodiments of the clock recovery method 600, the received communications signal is an analog signal and the step 660 of sampling the received communications signal comprises analog to digital conversion of the received communications signal, with the sampling being performed at a rate controlled by means of the selected clock error signal.

In embodiments of the clock recovery method 600, the received communications signal is a sampled digital signal and the step 660 of sampling the received communications signal comprises the step of interpolation filtering of the received communications signal, with the sampling rate and sampling offset of the received communications signal after said interpolation filtering being controlled by means of the selected clock error signal. In embodiments of the clock recovery method 600, the control signal is a receiver lock signal generated by a communications receiver, which receiver lock signal can assume the two states 'true' and 'false', and the step 650 of selecting the first or the second clock error signal to be the selected clock error signal comprises selecting the first clock error signal when the receiver lock signal is in the 'false' state, and selecting the second clock error signal when the control signal is in the 'true' state.

Embodiments of the invention are described with reference to the drawings, such as block diagrams and/or flowcharts. It is understood that several blocks of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by computer program instructions. Such computer program instructions may be provided to a processor of a general purpose computer, a special purpose computer and/or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer and/or other programmable data processing apparatus, create means for implementing the functions/acts specified in the block diagrams and/or flowchart block or blocks. These computer program instructions may also be stored in a computer- readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the function/act specified in the block diagrams and/or flowchart block or blocks. The computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions/acts specified in the block diagrams and/or flowchart block or blocks. . In some implementations, the functions or steps noted in the blocks may occur out of the order noted in the operational illustrations. For example, two blocks shown in succession may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality/acts involved.

In the drawings and specification, there have been disclosed exemplary embodiments of the invention. However, many variations and modifications can be made to these embodiments without substantially departing from the principles of the present invention. Accordingly, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation.

The invention is not limited to the examples of embodiments described above and shown in the drawings, but may be freely varied within the scope of the appended claims.