CORRECTION

CROSS REFERENCE TO RELATED APPLICATION

[0001] This application claims benefit under 35 U.S.C. § 119(e) to U.S. Provisional Patent Application No. 62/268,185 entitled "INTERLACING METHOD FOR HIGH THROUGHPUT FORWARD ERROR CORRECTION" filed on December 16, 2015; and U.S. Utility Patent Application No. 15/377,707 entitled, "INTERLACING

METHOD FOR HIGH THROUGHPUT FORWARD ERROR CORRECTION" filed on December 13, 2016, which are expressly incorporated by reference herein in their entirety

BACKGROUND

FIELD OF THE DISCLOSURE

[0002] The described technology generally relates to transmitting data with forward error correction (FEC). More specifically, the disclosure is directed to devices, systems, and methods related to interlacing transmitted data for use in a high throughput system that uses forward error correction to provide for improved performance.

DESCRIPTION OF RELATED ART

[0003] Forward error correction (FEC) is used on communication channels where there is a chance that data can be lost or corrupted. With some communication channels, such as a packet network where packets are likely to be discarded if corrupted, the channel would experience erasures much more than corruption, but FEC can be used in both cases to recover from losses. With FEC, an encoder encodes the source data to be sent with some repair data that can be used at a decoder to recover from losses.

Typically, the encoder is used at or near a transmitter and the decoder is used at or near a receiver.

[0004] Sometimes source data is available at the transmitter in advance and can be encoded well before the encoded data needs to be transmitted, but for many streaming applications, the latency between the time the source data is made available to the transmitter and encoder and the time the source data is output by the receiver needs to be very small. Latency might be in part a function of the type of FEC coding used and might be in part a function of how much hardware or processing power is available to encoders and decoders. For example, FEC encoding that applies repair data over a large span of the source data might result in added latency as a decoder has to wait to receive repair data to recover for much earlier sent source data.

SUMMARY

[0005] The implementations disclosed herein each have several innovative aspects, no single one of which is solely responsible for the desirable attributes of the present disclosure. Without limiting the scope of the invention, as expressed by the claims that follow, the more prominent features will be briefly disclosed here. After considering this description, one will understand how the features of the various implementations provide several advantages over current systems.

[0006] Encoding data for transmission can comprise receiving source symbols in a first sequence, storing the source symbols to a first memory in a second sequence, wherein the first sequence is a first interlacing relative to the second sequence, determining if the memory contains all source symbols of a codeword, wherein the source symbols of a codeword are the symbols used to generate repair symbols for that codeword, generating repair symbols for the codeword, storing the repair symbols to a second memory in a third sequence, interlacing the repair symbols and the source symbols into an output stream as a stream of encoded symbols, wherein the repair symbols appear in the output stream in a fourth sequence, wherein the fourth sequence is a second interlacing relative to the third sequence, and outputting the stream of encoded symbols.

[0007] An encoder might receive additional source symbols in the first sequence, store them in the first memory in the second sequence, determine which of the additional codewords are complete codewords in the first memory, and for each of the complete codewords, generate repair symbols by storing the repair symbols for each of the complete codewords to the second memory in the third sequence and interlacing the repair symbols and the source symbols for each of the complete codewords into the output stream as the stream of encoded symbols prior to the outputting of the stream of encoded symbols.

[0008] The first interlacing and the second interlacing can be equal. The first interlacing and the second interlacing can be determined from a target line rate, a specified protection period, and a specified symbol size. An encoding schedule might be generated in advance of receiving the source symbols, with allocation of codewords in the encoding schedule to stagger completion times of the codewords, wherein a completion time of a given codeword is a time at which a decoder obtains, or is scheduled to obtain, a last symbol of the given codeword. The first memory and the second memory can be distinct memory locations in one common memory structure.

[0009] An encoder and a decoder operating using the interlacing methods are contemplated. An encoder for encoding data for transmission might comprise an input for receiving source symbols in a first sequence, a first memory having storage for the source symbols corresponding to a codeword, wherein the source symbols corresponding to the codeword are the symbols used to generate repair symbols for the codeword, logic for storing the source symbols of the codeword to the first memory in a second sequence, wherein the first sequence is a first interlacing relative to the second sequence, a repair encoder for generating repair symbols for the source symbols of the codeword, a second memory having storage for storing the repair symbols in a third sequence, an interlacer that interlaces the repair symbols and the source symbols into an output stream as a stream of encoded symbols, wherein the repair symbols appear in the output stream in a fourth sequence, wherein the fourth sequence is a second interlacing relative to the third sequence, and an output for outputting the stream of encoded symbols.

[0010] A decoder for decoding data for transmission might comprise an input for receiving received encoded symbols from a communication channel in a transmitted first sequence, wherein the received encoded symbols are logically associated with a codeword, a first memory having storage for the received encoded symbols, logic for storing received encoded symbols of the codeword to the first memory in a second sequence, wherein the transmitted first sequence is a first interlacing relative to the second sequence, a pass-through for passing received source symbols through to an output buffer, logic for determining whether any source symbols of the codeword are missing in the first memory, a repair decoder for generating recovered source symbols corresponding to the source symbols, if any, of the codeword that are missing in the first memory, and a second memory having storage for caching cached source symbols that are later in a stream when outputting recovered source symbols that are earlier in the stream.

[0011] Decoding data for transmission can comprise receiving encoded symbols from a communication channel in a transmitted first sequence, wherein the encoded symbols are logically associated with a codeword, storing received encoded symbols of the codeword to a first memory in a second sequence, wherein the transmitted first sequence is a first interlacing relative to the second sequence, passing received source symbols through to an output buffer, determining whether any source symbols of the codeword are missing in the first memory, generating recovered source symbols corresponding to the source symbols, if any, of the codeword that are missing in the first memory, and caching source symbols that are later in a stream when outputting recovered source symbols that are earlier in the stream.

[0012] The following detailed description together with the accompanying drawings will provide a better understanding of the nature and advantages of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above-mentioned aspects, as well as other features, aspects, and advantages of the present technology will now be described in connection with various implementations, with reference to the accompanying drawings. The illustrated implementations, however, are merely examples and are not intended to be limiting. Throughout the drawings, similar symbols typically identify similar components, unless context dictates otherwise. Note that the relative dimensions of the following figures may not be drawn to scale.

[0014] FIG. 1 is a block diagram of a transmission system and exemplary components.

[0015] FIG. 2 is a block diagram of a transmitter as might be used in the transmission system of FIG. 1.

[0016] FIG. 3 is a block diagram of a receiver as might be used in the transmission system of FIG. 1.

[0017] FIG. 4 illustrates consumption of symbols at an encoder.

[0018] FIG. 5 is a transmission timeline illustrating consumption of symbols at an encoder in more detail.

[0019] FIG. 6 illustrates an ordering of information symbols.

[0020] FIG. 7 illustrates an exemplary pattern of information symbols and repair symbols.

[0021] FIG. 8 illustrates an ordering pattern involving nearly constant shift staggering of codewords. [0022] FIG. 9 illustrates a transmission sequence corresponding to the example of FIG. 8 using the pattern in FIG. 7.

[0023] FIG. 10 illustrates an example encoder and operation thereof.

[0024] FIG. 11 illustrates the decoder and operations thereof.

[0025] FIG. 12 illustrates the uses of the first decoder memory and the repair decoder in additional detail.

[0026] FIG. 13 illustrates a typical process for generating slices.

[0027] FIG. 14 illustrates a decode timeline.

DETAILED DESCRIPTION

[0028] In the following detailed description, reference is made to the accompanying drawings, which form a part of the present disclosure. The illustrative implementations described in the detailed description, drawings, and claims are not meant to be limiting. Other implementations may be utilized, and other changes may be made, without departing from the spirit or scope of the subject matter presented here. It will be readily understood that the aspects of the present disclosure, as generally described herein, and illustrated in the figures, can be arranged, substituted, combined, and designed in a wide variety of different configurations, all of which are explicitly contemplated and form part of this disclosure.

[0029] In a specific example, a transmitter includes an encoder that encodes source data as it is received that is transmitted before all of the source data to be transmitted is received at the transmitter and one or more receivers each has a decoder that receives symbols, recovers symbols that are lost in transmission if possible, and outputs the received data such that the received data is the same as the source data and is output with little delay relative to when the transmitter received the source data.

[0030] The source data that is to be sent from a transmitter to a receiver (or to more than one receiver simultaneously) can be thought of as being partitioned into symbols. An encoder is a computer system, device, electronic circuit, or the like, that generates encoded symbols from a sequence of source symbols and a decoder is the counterpart that recovers a sequence of source symbols from received or recovered symbols. In some cases, the encoder and/or the decoder have hardware limitations, such as the need to operate within the constraints of a portable and/or mobile device, such as a smartphone or other size and power constrained device, yet still provide good performance, robust error recovery, low latency, and small power consumption. [0031] The source symbols can be grouped into codewords, wherein the repair symbols for a codeword are usable for recovery of source symbols of that codeword. For example, k source symbols might be grouped into a codeword and r repair symbols generated for that codeword. A encoder would output N=k+r encoded symbols as the codeword and upon receiving the N encoded symbols or some subset of them, the decoder would use the received symbols to attempt to output the k source symbols, using the r repair symbols as needed.

[0032] FIG. 1 is a block diagram of a transmission system 100 and exemplary components. In this example, communication may occur over an optical beam channel from a transmitter to a receiver having an optical beam receiver. There might be multiple receivers (not shown in FIG. 1) and instead of optical beams, radio frequency (RF) antennae might be used to transmit wirelessly using radio frequency (RF) signals. It should be understood that the transmission system might also have applicability to other types of communication channels where erasure of transmitted data is possible.

[0033] As illustrated in FIG. 1, a data source 102 provides data to a transmitter 104, which in turn transmits a signal through a channel 106 and that signal, with some alterations possible, is received at a receiver 108, which attempts to recover the data that transmitter 104 encoded into the signal and output that recovered data to a data consumer 110. The particulars of the transmitter 104 and receiver 108 are constructed, as explained herein, to provide for low latency and high throughput with high decoder and encoder utilization.

[0034] The data source is the system or device or process that has data that needs to be available to the data consumer. As one specific example, the source of data frames might be an edge server that is serving up video content that a subscriber of a video streaming service requested and the data consumer is a video player running on a device owned or controlled by the subscriber, such as a mobile application for video streaming that runs on a smartphone where the smartphone also runs the receiver and decoder. In another specific example, the source of the data is an Internet Service Provider (ISP) and the consumer of the data is a router or gateway in a system for providing over-the-air Internet connectivity. Herein, the data might be organized into packets, wherein a packet is a unit of data that is either received entirely correctly or discarded entirely as a result of lower level network protocols. A packet might include multiple symbols, a single symbol per packet, a symbol distributed over multiple packets, or some combination.

[0035] Receiver 108 outputs data, preferably exactly the data received by transmitter 104, preferably using available decoder hardware efficiently and preferably with a low latency between when transmitter 104 receives the data and when receiver 108 outputs the data. Low latency might be important where the transmitter 104 is not able to get the data in advance and yet data consumer 110 expects the data to be available shortly after it is made available to transmitter 104.

[0036] FIG. 2 illustrates additional detail of transmitter 104. As shown there, transmitter 104 has a network interface 202, as might be used to get data from a data source in the form of source symbols that can be grouped into groups of k source symbols per codeword period. Those source symbols are provided to an encoder 204 that outputs N=k+r encoded symbols for each k source symbols to a packetizer 206 that fills lower level protocol packets with the N encoded symbols and outputs packets to a transmit unit 208 that generates the signal that transmitter 104 outputs.

[0037] Encoder 204 of embodiments comprises a first memory, a source symbol deinterlace memory 210, a repair symbol generator 212, a second memory, a repair symbol interlace memory 214, and a multiplexer 216. Source symbol deinterlace memory 210 takes source symbols in a first sequence and outputs them in a second sequence, as detailed below, while repair symbol interlace memory 214 takes repair symbols in a third sequence and outputs them in a fourth sequence, as encoded symbols. Repair symbol generator 212, such as might be a RaptorQ encoder or other erasure coding module, generates r repair symbols for a codeword comprising k source symbols, resulting in N=k+r encoded symbols. Multiplexer 216 multiplexes the repair symbols and the source symbols for output of encoder 204. With a source symbol pass-through, the source symbols can appear at the output of encoder 204 without any reordering delay. The encoded symbols are then further processed and transmitted as the transmitted signal.

[0038] FIG. 3 illustrates additional detail of receiver 108. As illustrated there, the signal is received at a receive unit 302 and passed as packets to a depacketizer 304. Depacketizer 304 extracts data from packets that are correctly received, passing them on to a decoder 306 while discarding corrupted packets. In this manner, decoder 306 can operate as an erasure decoder. Decoder 306 outputs the source symbols it recovers to a network interface 308.

[0039] Decoder 306 of embodiments includes a protection buffer memory 310, a symbol recovery unit 312, a multiplexer 314 and a contention buffer memory 316. Received symbols are provided on a pass-through to contention buffer memory 316 and can be passed through to multiplexer 314 and out to network interface 308 without delay as they are received. However, if it is desirable to have source symbols emitted from decoder 306 in the same order as they were presented to encoder 204, then if there is a lost source symbol that has yet to be recovered, the source symbols that come later are buffered in contention buffer memory 316.

[0040] Symbol recovery unit 312 might be a RaptorQ decoder or other erasure recovery module. Symbol recovery unit 312 operates on received symbols, which are source symbols and repair symbols, taking into account the interlacing that occurred at the transmitter, thus doing the inverse of that interlacing. When lost symbols are recovered, or as constant stream of lost and not lost symbols, symbols are output by symbol recovery unit 312 and multiplexer 314 might prioritize which symbols get output first as between symbols from symbol recovery unit 312 and symbols from contention buffer memory 316 based on the order of occurrence of the symbols.

[0041] Referring to FIG. 2 and FIG. 3, encoder 204 has sufficient information to determine an encoding schedule in advance of receiving each k source symbols, whereas decoder 306 might wait until receipt or non-receipt of encoded symbols to determine a decoding schedule, as a decoding schedule typically depends on which source symbols were lost and are in need recovery. Of course, a streaming application will likely send multiple codewords, each having k source symbols and N encoded symbols total, and as explained herein, the interlacing of the symbols provides desirable properties.

[0042] In an exemplary embodiment, the transmitted symbols are viewed as an interlacing of / interlaces. Codewords are interlaced in a staggered fashion to facilitate decoder pipelining and to provide a wider protection period for a codeword. In operation according to embodiments, a codeword is transmitted on a single interlace. The transmission of a codeword comprises transmitting information symbols followed by transmission of repair symbols usable for recovery or redundancy. The repair symbols of one codeword may be transmitted in time overlapping with the transmission of source symbols of subsequent codewords being transmitted on the same interlace. The number of interlaces can be chosen as a design consideration in conjunction with symbol size, transmission rate, transmission protection period etc.

[0043] As an example, suppose that because of transmission conditions it is desirable that the transmission of a codeword occur over a protection period, T _tr seconds, over which the codeword is distributed for protection against losses. Assume that codewords are N symbols long and that the codeword symbols are approximately uniformly spaced in time during the protection period. Assume that I interlaces are cyclically used in the transmission, i.e., every 7-th transmitted symbol is from the same interlace. Then the length of the protection period corresponds to the transmission time of N7 symbols and the relation N * I * T = T _tr * R holds, where R is the line rate in bits per second and T is the symbol size in bits. The information rate, the rate at which bits are arriving at the encoder for encoding, is k N times the line rate. Assume each codeword comprises k information symbols followed by r repair symbols, which can be simple parity symbols or more complex redundant symbols that have values that are usable to decode or infer, possibly along with other information available at a receiver, values for one or more of the k information symbols. Notably, if none of the k information symbols are lost, the r repair symbols are not needed.

[0044] With each codeword comprising k information symbols followed by r repair symbols, on average only a first fraction, k/N, of the I interlaces are transmitting information symbols, while a second fraction, r/N, are transmitting repair symbols. Assuming information symbols are forwarded for transmission with minimal delay, information symbols are not arriving at the encoder in a cyclic fashion for each interlace. There are gaps in time, associated with the transmission of repair symbols for that interlace, during which information symbols are not accumulated for that interlace. Thus, at the encoder, the incoming symbols will not sample the interlaces cyclically, but will instead skip interlaces that are associated with transmission of repair symbols at that point.

[0045] FIG. 4 illustrates the consumption of symbols at the encoder. In the example shown, 1=6, £=10, r=6, N=16. The cross-hatched slots represent information symbols, the stippled slots represent repair symbols, and the order of symbols is from right to left. The transmit order of symbols is vertically, top to bottom, and then right to left, as indicated by the symbol numbers 0 through 9 in FIG. 4. One complete codeword from each interlace is highlighted (darker than surrounding codewords). It can be observed that starting and ending positions of codewords are approximately uniformly spaced. The starting points of codewords are offset symbol-wise by 0, 17, 16, 16, 15, 16, 16, i.e., if the first information symbol of the first codeword starts at 0, then the first information symbol of the next codeword will start 17 symbols later, the second information symbol of the third codeword will start 16 symbols after that, and so on. Note that the entire structure is periodic. In this example, the gap in time between the last information symbol in a codeword and the first repair symbol in a codeword is equal to the transmission time used for / symbols. In some embodiments, it might be desirable to lengthen this gap to allow more time for encoding operations.

[0046] In this example, one codeword is spread over one protection period, T _tI , and since there are N codeword symbols, on average a new encoded symbol from the codeword is encountered by an encoder or decoder every TJI seconds, which is referred to herein as the "sample period." Thus, on a per codeword basis, the processor time allotted, r _proc , for processing the codeword is around T _pmc =T _tI /I. This is assuming that encoding and decoding processing dedicated to this interlaced stream operates at a rate just sufficient to achieve the line rate throughput.

[0047] So, for a given T, N, and T _tI , the number of interlaces, /, can be selected according to the line rate. Typically N and / will be chosen to satisfy the above relation approximately and the transmission protection interval will be adjusted accordingly. In order to later characterize the relation between encoding and decoding latency and transmission periods, consider a parameter, a, that is determined according to:

N = aVT _tr * R/T and/or / = ^T _tr * R/T

[0048] As mentioned above, in the current example, the time allotted for encoding without delaying information symbols is equal to T _proc /a ² . For large values of a, this represents an over-provisioning requirement on the encoder, since the time allotted is shorter than the average time allotted. Alternate embodiments of the interleaving of information and repair symbols can alleviate this problem.

[0049] The encoder might take into account, or be programmed for, coherence bandwidths suitable for the channel and a suitable protection period. This may be designed into the encoder and decoder or it might be programmable at runtime, or other variation. The coherence bandwidth might be an uncontrollable factor in a communication channel, but where it is predictable, the encoder and decoder in a communication system can be designed to assume a particular coherence bandwidth. For example, the communication system might be designed with an assumed coherence bandwidth of 5 to 10 ms (milliseconds). An example protection period might be 100 to 200 ms, which would provide between around 10 to 40 coherence intervals per protection period. The number of symbols per encoded codeword, N, might be selected to provide sampling coherence intervals at a fine granularity with N encoded symbols distributed across a protection period. In one example, N=400, but larger or smaller numbers for N could be used depending on what is needed. Each symbol has a symbol size, T, which might be a value such as 8 kilobytes ("KB") (64 K bits, or "64 Kb"), 32 KK (256 Kb), 128 KB (1,024 Kb), or 128 megabytes (1,024 Mb). For some

implementations, 8 KB to 128 KB is likely a more practical range given interlacing and processor requirements.

[0050] As one specific example, given design parameters of T=32 KB, N=400, and T _tr =130 ms, to achieve a line rate of 100 Gb/s, / might be set at / = 127 (100 Gb/s is about 256 Kb * 400 * 127 / 130 ms). In this example, the sample period would be 130 ms / 127 = 1.02 ms. Using the design parameter a, the number, N, of symbols in an encoded codeword might be set to approximately a * 225, so for N=400, a would be equal to around 1.78. As another example, with r _tr =150 ms, R=100 Gb/s, and Γ=128 kB, N is approximately a* 121. It can be assumed that a>l, so N and / are also greater than 1.

[0051] In a specific hardware embodiment, a transmitter is implemented into a compact optical transmitter board with a network interface capable of receiving data at a rate of up to 100 Gb/s (gigabits per second), perhaps using a parallel array of ten 10 gigabit Ethernet channels. The interlacing operation may be performed on the entire 100 Gb/s link or on a sub portion of that entire link, such as one or several of the ten gigabit Ethernet links. The optical transmitter board might include an array of ten transceivers, a field programmable gate array (FPGA chip) for performing the encoding, another FPGA for converting the data stream to an optical signal and outputting it. The compact optical transmitter board might be bi-directional, wherein the board implements both a transmitter and a receiver, possibly using some components for both directions of traffic. The encoder and decoder might operate using a RaptorQ encoding scheme for generating repair symbols. [0052] FIG. 5 is a transmission timeline illustrating this in more detail. As illustrated, every sample period, there are / symbols, one symbol per interlace. The protection period has about N * / symbol intervals. Every N symbols, a codeword completes, as they are evenly spaced. At the encoder, when the receipt of the k source symbols is complete, the codeword information is known to the encoder and the r repair symbols can be generated shortly thereafter. At the decoder, when the receipt of the N receive symbols is complete, the codeword finishes and decoding can begin for recovery of missing source symbols. Decoding may begin earlier if a sufficient number of symbols have been received, but generally the decoder is designed with an assumption that decoding might not begin until the end of reception.

[0053] In order to relieve the constraint on encoding time, the interlacing might be such that on one interlace the repair symbols for a codeword do not immediately follow the source symbols for that codeword. This can be used to insert a gap in time between the last information symbol of a codeword and the first repair symbol of the same codeword to allow for encoding processing. In an exemplary embodiment, this can be provided by having two sets of interlaces, one for source symbols and one for repair symbols. The two sets of interlaces are themselves interleaved, so that on average for every k information symbols, there are r repair symbols. The ordering of interlaces on both information symbols and repair symbols could be the same as in the previous example, but now the repair symbol stream could be independently shifted in time to allow greater encoding time.

[0054] In general, the encoder would track the symbols to be able to flag when the last source symbol of a codeword is received, and the decoder would track the systems to be able to flag when a first repair symbol for a codeword is received and when a last repair symbol for a codeword is received. In the illustration of FIG. 5, the arrows below the timeline indicate last symbols for codewords. Note that they are approximately evenly distributed.

[0055] At the encoder, an encoding point is a point in the sequence when all k source symbols for a codeword have arrived at the encoder and that is when the encoder can kick off the encoding process for that lace. Encoding points occur on average every k source symbols (and correspondingly every N transmit symbols). In the example of regularly cyclically sampled interlaces, if N and / are coprime, then a codeword could complete every N transmitted symbols regularly and the end points would cycle through all the streams regularly.

[0056] If / and N are not coprime, then the encoder/decoder can perturb the encoding points to have a separation that varies among N-l , N, N+l, for example. In the example of FIG. 4, / and N are not coprime (N=16 and 1=6). If / divides N, then other approaches can be taken, but it is not difficult to arrange encoding so that / does not divide N. For example, / might be set to 7=139 and N set to some number not a multiple of 139, so that they are coprime.

[0057] The symbol counts between encoding points in the transmit sequence (e.g., 0, 17, 16, 16, 15, 16, 16 from the example of FIG. 4) form a periodic sequence of period N * I. In the case where I does not divide N, then let d>l be the greatest common divisor of I and N. A repeating pattern such as the following suffices:

(N+l) ^d_1 (N) ^//d_1 ((N- l) (N) ^ΙΙά - ² ) ^άΛ Ν

(N+l) symbols d times, and then N symbols I/d- l times, etc.

[0058] In the case where I divides N, a variation to use might be N+2, N+l, N, N- l, N-2.

I even: (N+2) ^//2~1 (N+l)(N-2) ^//2_1 (N- 1)

/ odd: (N+2) ^(/"1)/2 (N-l)(N-2) ^(/"3)/2 (N- l)

Each of these sequences gives an average of N and hits each stream exactly once every / rounds.

[0059] For example, if l<d<I, the sequence of decoding points is:

0, N+l , (d- l)(N+l), (d-l)(N+l)+N (d-l)(N+l)+(I/d- l)N, (d- l)(N+l)+(//d-l)N+N- l, . . .

[0060] In that example, there are / terms in the sequence and each is distinct modulo /. The sequence then repeats periodically with a shift of N * /.

[0061] This can be verified as follows. If d is the greatest common divisor of k and /, denote N/d mod I/d as p. Then p is coprime to I/d. Hence the integers modulo / have a unique representation (j,r) j=0, . . . , I/d-l and r=0, d- l where (j,r) is equivalent to j p d + r. It follows that (j,r) + N = (j+l ,r). If d=l (N and / are coprime) then we may simply take the sequence N ⁷ which clearly suffices.

[0062] Assume 1 < d < I and consider the sequence (N+l) ^dA (N) " ^dA ((N-l) (N) ^Ild'2 ) ^dA N. Modulo / we obtain in the above representation (0,0), (1 , 1), . . . , (d- l ,d-l) followed by (d,d-l), (d+l ,d-l), ·■· , (d-2+Ild,d-V)=(d-2,d- V). This (including (d-l ,d- l)) covers all (j,r) with r=<i-l. Following this we have (d-l,d-2),...,(d-3+I/d,d-2)=(d-3,d-2) which together with (d-2,d-2) covers all (j,r) with r=d-2. Following this we have (d-2,d- 3),...,(d- +Ild,d-3)=(d- ,d-3) which together with (d-3,d-3) covers all (j,r) with r=d-3. Continuing inductively in the last step, we have (1,0),...,(-l+7/<i,0) which together with (0,0) covers all (j,r) with r=0. The final additional step of size N takes (-l+7/<i,0) back to (0,0) completing the cycle. The case d=I is simpler. When 7 is even, the sequence (N+2) ^//2"1 (N+l)(N-2) gives, modulo 7, the sequence 0,2,4,...,1-4,1-2,1- 1,1- 3,...,1,0. When 7 is odd, the sequence (N+2) ^(/"1)/2 (N-l)(N-2) ^(/"3)/2 (N-l) gives, modulo 7, the sequence 0,2,4,... J-3J-1 ,7-2,7-4,· . ·, 1,0.

[0063] Once the transmission sequence is determined then the order in which incoming information symbols are assigned to interlaces follows directly. FIG. 6 shows the ordering of information symbols corresponding to the example in FIG. 4. In FIG. 6, 7=6, £=10, r=6, and N=16. The order in which information symbols are assigned to interlaces is affected by the transmission structure.

[0064] After encoding, the symbol rate increases. As mentioned, the above example, with cyclically sampled interlaces at transmission, has the potential disadvantage of requiring either delayed transmission of information symbols. An alternative approach is to have separate streams for information and repair symbols that are interleaved together. With N=k+r encoded symbols for each k source symbols, one approach is to use a repeated pattern of N symbols where k are source symbols and r are approximately uniformly interleaved repair symbols. This can guarantee good interleaving between information and repair symbols so that the transmission of information symbols can proceed regularly with minimal additional delay.

[0065] FIGS. 7, 8 and 9 illustrate an example of a design for positioning the repair symbols according to two interleaved sequences. If the throughput of the encoder is not substantially overprovisioned, then the time for encoding will be approximately the time for k source symbols. On the transmit stream, this corresponds to N symbol times. Since the encoding points are nearly uniformly placed and it is desirable to have the decoding points uniformly spaced, the design of the encoder might be such that the placement of the repair symbols reflects this, while leaving sufficient gap to allow encoding operations for each stream. By way of explanation, assume a transmission structure in which r repair symbols are interleaved with every k source symbols. [0066] FIG. 7 illustrates an exemplary pattern with £=10, r=6, and N=16. This pattern of N symbols is repeated in a periodic fashion. For purposes of ordering and staggering interlaces, the encoder/decoder can use a more regular, or arbitrary arrangement of the staggering of the codewords.

[0067] FIG. 8 illustrates an example with a simple transmission structure involving nearly constant shift staggering of the codewords. There, 1=6, £=10, r=6, and N=16. The cross-hatched slots represent information symbols and the stippled slots represent repair symbols. The transmit order of symbols is vertically, top to bottom, and then right to left. In this case, however, the encoder and decoder are programmed or configured to use the structure to define information and repair symbol order independently. For actual transmission, the two streams are mapped into a sequence of symbols as in FIG. 7. In this way an offset (delay) between the end of the information symbols and the beginning of the repair symbols can be introduced to allow more time for encoding. The numerals in FIG. 8 indicate transmit order separately for information and repair symbols.

[0068] Alternate orders of the interlaces can give slightly more uniform spacing of the decoding points, such as the ordering in FIGS. 4 or 6. In addition, schemes in which the shifts from codeword to codeword could be constant might also be used. Depending on the values of N and /, only certain transmission protection periods could be realized this way and the transmission structure may fail to be periodic over single codeword transmissions in each interlace. In such a case, the notion of cyclically sampled interlaces itself may no longer apply and instead the transmission could be understood as a sequence of codewords. Due to the finiteness of the parameters in the construction, the structure would be periodic but the period could be significantly longer than the protection period. In FIG. 8, the shifts of the codewords are not constant so that after / shifts, the total shift is equal to N, thus creating a periodic structure of length NI.

[0069] FIG. 9 illustrates the transmission sequence corresponding to the example in FIG. 8 using the pattern in FIG. 7. The transmission sequence indicated is the one directly induced by the ordering in FIG. 8. In FIG. 9, "I" indicates an information symbol and "P" indicates a parity (repair) symbol. Also, the first number indicates the interlace and the second number indicates the position of the symbol within the codeword. Because the information and parity streams are handled separately, however, an additional delay can be introduced into the parity sequence by shifting the parity transmission sequence some number of symbols in the parity sequence. Note that the shading of FIG. 9 matches the pattern of FIG. 7.

[0070] FIG. 10 illustrates an example encoder and operation thereof. The memory elements shown might be memory dedicated to single purposes or usable for multiple purposes. The first memory might be a double data rate (DDR) memory structure capable of storing twice the throughput of the system (R) over the protection period. Thus, where R=100 Gb/s and the protection period is 130 ms, the structure would store about 26 gigabits. For other values of throughput, protection period, etc., that number may vary.

[0071] As illustrated in FIG. 10, the source symbols (the symbols received at an input of the encoder/transmitter from the data source) are in a first sequence (order). This may be the order in which the source symbols are consumed, but in any case, it is a preferable order in which the source symbols might be output by the decoder. The encoder passes the source symbols through to an output stream to an interleaver to be interleaved with repair symbols. However, the encoder also stores the source symbols in a first memory in a second sequence. For that second sequence, one source symbol per sample period is obtained and stored with other symbols from other sample periods, so that a codeword of k source symbols is stored in the first memory in the second sequence, which is a deinterlacing of the first sequence.

[0072] Once all the source symbols for a codeword are available, the encoder passes those to a repair symbol generator, such as the RaptorQ encoder illustrated. In the meantime, there are other codewords (from other interlaces) for which symbols are accumulating in the first memory. As a result, the operation of the repair symbol generator is relatively smooth and sees a new codeword every N symbol periods or so.

[0073] A second memory, which might be part of the same physical memory chip or structure that implements the first memory, buffers the generated repair symbols. The encoder then interleaves the repair symbols and the source symbols. Note that the interlacing is such that the repair symbols for a codeword need not be adjacent to the source symbols for that codeword and in fact typically are not. Logically, the output of the encoder can be considered as / distinct substreams, with one symbol from each substream every / symbols in the output stream.

[0074] FIG. 11 illustrates the decoder and operations there. As shown, the decoder receives symbols that were transmitted, possibly with some missing. The decoder includes a pass-through for the source symbols and also stores received symbols in a first decoder memory in a deinterlaced fashion. They are stored so that the decoder can easily pass the received symbols grouped by codeword to a repair decoder, shown here as a RaptorQ decoder. Thus, the repair decoder receives source symbols for a codeword, followed by the repair symbols for that codeword, then the source symbols for the next codeword, and so on.

[0075] The repair decoder outputs recovered source symbols. The repair decoder could also output some received source symbols, but that is not necessary with the pass-through. The repair decoder might determine just which source symbols are missing and output only those source symbols. Where symbols are operated on within the transmission system using electronic symbol identifiers (ESIs), then symbols need not be identified solely by their position within a stream.

[0076] Where the output of the decoder to the data consumer(s) is in source stream order, matching the order in which the data source supplied them to the transmitter, source symbols can be buffered at a second decoder memory so that received source symbols are held while recovery is occurring for other source symbols. The second decoder memory might also be used as a buffer to deal with the situation where there was a lag and now the decoder is able to output symbols at a rate greater than the line rate. In such cases, there might be contention between the passed-through source symbols and the recovered source symbols.

[0077] FIG. 12 illustrates the uses of the first decoder memory and the repair decoder in additional detail. As shown there, the vertical slices of memory correspond to portions of codewords and are processed from right to left. In the case of a RaptorQ decoder, there is a first stage of the repair decoder that computes the RaptorQ

intermediate symbols and a second stage that uses a chain reaction decoding to generate any missing symbols.

[0078] Where limited FPGA internal memory precludes loading a complete codeword into the FPGA for processing, the complete codeword might be stored in the first decoder memory and processing broken up into multiple slices. The slice size might be determined from the amount of parallelism needed to meet the required throughput. In this example, one processing slice contains a portion of bits from all symbols in a codeword. An internal FPGA buffer might be dimensioned to hold a two processing slices at a time. Completed output symbols can then be built up from multiple completed slices in the second decoder memory, shown here as DDR output buffer. In one example, there are 200 source symbols per codeword (£=200), 7=32KB, and T _pioc = 1 ms. This would result in a slice size of 7 kilobits/symbol * (k+e) ~= I A3 megabits, for some small ε.

[0079] A parallelism parameter, P, is chosen so that processing rate can support the line rate. The FPGA buffer would be able to store around k * P bits.

Intermediate RaptorQ symbols are generated based on those k * P bits and written to an intermediate symbol buffer in around 32 * k clock cycles. Slices of repair/missing symbols are then generated over around 8 * k cycles and written out to the second decoder memory.

[0080] FIG. 13 illustrates a typical process for generating slices.

[0081] FIG. 14 illustrates a decode timeline. A decoder that is provisioned to just meet the throughput requirement will take nearly N = a I transmit symbol periods to decode. Shortening the latency would require over-provisioning the decoder. A typical codeword transmission spans NI symbol periods, so the latency/transmission ratio for minimally provisioned decoding is III. For example, in the case of a protection period of 150 ms and 30 interlaces, the decoding latency will be approximately 5 ms. For the parameters above, this would correspond to approximately N=364. With 20 interlaces, the decoding latency would be 7.5 ms and a suitable design value would be N=546.

[0082] As described it takes 7*N symbol periods (approximately one protection period) to cover a starting point for each stream. For a synchronous start design, the source stream could be padded with zeros prior to the actual starting point. The first I codewords would then be at an effectively lower code rate. An alternative would be some more complex packing of possibly smaller codewords to initiate the transmission.

[0083] In other variations, the encoder can operate with fixed interval codewords and variable interval codewords. In some variations, the decoder does not necessarily provide in-order packet delivery.

[0084] Using one or more of the elements, techniques and/or components described above, a suitable data transmission system, transmitters and receivers can be designed. Further embodiments can be envisioned to one of ordinary skill in the art after reading this disclosure. In other embodiments, combinations or sub-combinations of the above disclosed invention can be advantageously made. The example arrangements of components are shown for purposes of illustration and it should be understood that combinations, additions, re- arrangements, and the like are contemplated in alternative embodiments of the present invention. Thus, while the invention has been described with respect to exemplary embodiments, one skilled in the art will recognize that numerous modifications are possible.

[0085] The terminology used herein is for the purpose of describing particular implementations only and is not intended to be limiting of the disclosure. It will be understood by those within the art that if a specific number of a claim element is intended, such intent will be explicitly recited in the claim, and in the absence of such recitation, no such intent is present. For example, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises," "comprising," "includes," and "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Expressions such as "at least one of," when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.

[0086] For example, the processes described herein may be implemented using hardware components, software components, and/or any combination thereof. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. It will, however, be evident that various modifications and changes may be made thereunto without departing from the broader spirit and scope of the invention as set forth in the claims and that the invention is intended to cover all modifications and equivalents within the scope of the following claims.

[0087] Operations of processes described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. Processes described herein (or variations and/or combinations thereof) may be performed under the control of one or more computer systems configured with executable instructions and may be implemented as code (e.g., executable instructions, one or more computer programs or one or more applications) executing collectively on one or more processors, by hardware or combinations thereof. Further embodiments include a non-transitory processor-readable medium on which is stored processor- executable instructions configured to cause a computing device to perform operations of processes described herein. The use of any and all examples is intended merely to better illuminate embodiments of the invention and does not pose a limitation on the scope of the invention unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the invention.