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Title:
INTERLEAVED SIGNAL GENERATING CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2022/188354
Kind Code:
A1
Abstract:
An interleaved signal generating circuit is provided, comprising: an interleaved pulse generating circuit (300) which generates a first pulse signal (ActClk) according to a first control signal (ActEn) and generates a second pulse signal (PreClk) according to a second control signal (PreEn), wherein the first control signal (ActEn) is the inverse of the second control signal (PreEn) and the first pulse signal (ActClk), and the first pulse signal (ActClk) and the second pulse signal (PreClk) are interleaved pulse signals; and a delay signal output circuit, comprising G signal output circuits (500), wherein G is an integer greater than or equal to 2. Non-first-stage signal output circuits receive delay output signals output by preceding-stage signal output circuits as input signals of current-stage signal output circuits. A first-stage signal output circuit receives an initial input signal as the input signal of the first-stage signal output circuit to generate the period-adjustable first pulse signal (ActClk) and second pulse signal (PreClk), and generates a delay-controllable delay signal according to the first pulse signal (ActClk) and the second pulse signal (PreClk). The area of the circuit layout is small, and the power consumption of the circuit is small.

Inventors:
WANG JIA (CN)
Application Number:
PCT/CN2021/112026
Publication Date:
September 15, 2022
Filing Date:
August 11, 2021
Export Citation:
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Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H03K19/017; G06F13/40; H03K19/0175; H03K19/0185; H03L7/07
Foreign References:
CN101102109A2008-01-09
CN106506001A2017-03-15
CN103840796A2014-06-04
CN208797912U2019-04-26
CN110428048A2019-11-08
CN103944568A2014-07-23
JP2014060669A2014-04-03
US20060152994A12006-07-13
KR20110076672A2011-07-06
Attorney, Agent or Firm:
CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)
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