Title:
INTERPOLATION CIRCUIT OF AN ENCODER
Document Type and Number:
WIPO Patent Application WO/1989/012798
Kind Code:
A1
Abstract:
Position data of 2M bits are divided into data of lower M bits and data of higher M bits. The data of lower M bits are stored in a lower memory region (14a) of a ROM (14), the data of higher M bits are stored in a higher memory region (14b), the most significant bit of address data is set to "0", "1" successively by an address changing unit (15), the data of lower and higher M bits are read out from the lower memory region (14a) and the higher memory region (14b) and are synthesized together through a synthesizing unit (17) to obtain position data of 2M bits.
Inventors:
TANIGUCHI MITSUYUKI (JP)
Application Number:
PCT/JP1989/000607
Publication Date:
December 28, 1989
Filing Date:
June 16, 1989
Export Citation:
Assignee:
FANUC LTD (JP)
International Classes:
G01D5/244; G01D5/245; (IPC1-7): G01D5/245; G01D5/36
Foreign References:
| JPS62110113A | 1987-05-21 |
Other References:
Shirodo Yoshio (Zukai Digital IC no Subete) 20 January 1988 (20. 01. 88) Tokyo Denki Daigaku p. 212 - 213
See also references of EP 0379589A4
See also references of EP 0379589A4
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