Title:
INTERRUPT CONTROL METHOD AND INTERFACE DEVICE
Document Type and Number:
WIPO Patent Application WO/2018/008103
Kind Code:
A1
Abstract:
In a computer system, a memory has a plurality of issuance queues in which issuance commands from a processor to an interface device are stored and a plurality of completion queues in which completion commands from the interface device to the processor are stored. When dequeuing an issuance command from an issuance queue, the interface device transmits the issuance command to an external device, and holds command information relating to the issuance command in a storage area. Upon reception of a completion command from the external device, the interface device enqueues the received completion command to a certain completion queue, holds an ID of the completion queue, and deletes the command information relating to the issuance command corresponding to the received completion command from the storage area.
Inventors:
MARUYAMA TAKAFUMI (JP)
Application Number:
PCT/JP2016/069983
Publication Date:
January 11, 2018
Filing Date:
July 06, 2016
Export Citation:
Assignee:
HITACHI LTD (JP)
International Classes:
G06F13/12; G06F13/24; G06F13/36
Domestic Patent References:
| WO2016059692A1 | 2016-04-21 | |||
| WO2016056140A1 | 2016-04-14 |
Attorney, Agent or Firm:
WILLFORT INTERNATIONAL PATENT FIRM (JP)
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