Title:
INTERRUPT CONTROL METHOD, MULTI-CORE PROCESSOR SYSTEM, AND INTERRUPT CONTROL PROGRAM
Document Type and Number:
WIPO Patent Application WO/2012/014285
Kind Code:
A1
Abstract:
A CPU (#0), which is the master CPU, detects an interrupt signal from a device (201#0) by means of a writing unit (301), and writes first data describing the detection of the interrupt signal in an interrupt flag table (204#0). After writing, the CPU (#0) communicates an execution request for an interrupt process associated with the interrupt signal to CPUs (#1-#3) by means of a notification unit (302). The CPU (#0) runs the notification unit (302) by implementing coherency on the cache memory of CPUs (#1-#3) by means of a cache coherency mechanism (203). The first data is maintained in the interrupt flag table (204#1), and the CPU (#1), which received the notification for an execution request, executes the interrupt process by means of an execution unit (304). The CPU (#1) writes second data describing the non-detection of an interrupt signal in an interrupt flag table (204#1) by means of a writing unit (303).
Inventors:
YAMASHITA, Koichiro (1-1 Kamikodanaka 4-chome, Nakahara-ku, Kawasaki-sh, Kanagawa 88, 〒2118588, JP)
山下 浩一郎 (〒88 神奈川県川崎市中原区上小田中４丁目１番１号 富士通株式会社内 Kanagawa, 〒2118588, JP)
YAMAUCHI, Hiromasa (1-1 Kamikodanaka 4-chome, Nakahara-ku, Kawasaki-sh, Kanagawa 88, 〒2118588, JP)
山内 宏真 (〒88 神奈川県川崎市中原区上小田中４丁目１番１号 富士通株式会社内 Kanagawa, 〒2118588, JP)
山下 浩一郎 (〒88 神奈川県川崎市中原区上小田中４丁目１番１号 富士通株式会社内 Kanagawa, 〒2118588, JP)
YAMAUCHI, Hiromasa (1-1 Kamikodanaka 4-chome, Nakahara-ku, Kawasaki-sh, Kanagawa 88, 〒2118588, JP)
山内 宏真 (〒88 神奈川県川崎市中原区上小田中４丁目１番１号 富士通株式会社内 Kanagawa, 〒2118588, JP)
Application Number:
JP2010/062626
Publication Date:
February 02, 2012
Filing Date:
July 27, 2010
Export Citation:
Assignee:
FUJITSU LIMITED (1-1 Kamikodanaka 4-chome, Nakahara-ku Kawasaki-sh, Kanagawa 88, 〒2118588, JP)
富士通株式会社 (〒88 神奈川県川崎市中原区上小田中４丁目１番１号 Kanagawa, 〒2118588, JP)
YAMASHITA, Koichiro (1-1 Kamikodanaka 4-chome, Nakahara-ku, Kawasaki-sh, Kanagawa 88, 〒2118588, JP)
山下 浩一郎 (〒88 神奈川県川崎市中原区上小田中４丁目１番１号 富士通株式会社内 Kanagawa, 〒2118588, JP)
YAMAUCHI, Hiromasa (1-1 Kamikodanaka 4-chome, Nakahara-ku, Kawasaki-sh, Kanagawa 88, 〒2118588, JP)
富士通株式会社 (〒88 神奈川県川崎市中原区上小田中４丁目１番１号 Kanagawa, 〒2118588, JP)
YAMASHITA, Koichiro (1-1 Kamikodanaka 4-chome, Nakahara-ku, Kawasaki-sh, Kanagawa 88, 〒2118588, JP)
山下 浩一郎 (〒88 神奈川県川崎市中原区上小田中４丁目１番１号 富士通株式会社内 Kanagawa, 〒2118588, JP)
YAMAUCHI, Hiromasa (1-1 Kamikodanaka 4-chome, Nakahara-ku, Kawasaki-sh, Kanagawa 88, 〒2118588, JP)
International Classes:
G06F9/48; G06F12/08
Attorney, Agent or Firm:
SAKAI, Akinori (A. SAKAI & ASSOCIATES, 20F Kasumigaseki Building, 2-5, Kasumigaseki 3-chome, Chiyoda-k, Tokyo 20, 〒1006020, JP)
Download PDF:
Claims:
Previous Patent: METHOD OF GENERATING TEST SCENARIO, TEST SCENARIO GENERATING SYSTEM AND TEST SCENARIO GENERATING PRO...
Next Patent: LIGHT MODULE
Next Patent: LIGHT MODULE