CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to United States Patent Application No. 15/840,517, filed on December 13, 2017, which is a continuation-in- part of United States Patent Application No. 15/622,202 filed on June 14, 2017 which claims the benefit of U.S. Provisional Application No. 62/349,731 filed on June 14, 2016. The entire disclosures of the above applications are incorporated herein by reference.

FIELD

[0002] The present disclosure relates to an intraocular pressure sensor.

BACKGROUND

[0003] Intraocular pressure is the fluid pressure inside the eye. Intraocular pressure is an important measure in the diagnosis of patients at risk of glaucoma. Recently, implantable sensors have been developed to measure intraocular pressure inside the eye. Given the implantable nature of these sensors, it is imperative that sensors implantable in the eye consume low power to enable battery and energy harvesting to be miniaturized and obtain a small enough device to allow implantation. Therefore, it is desirable to provide an implantable intraocular pressure sensor having very low power consumption.

[0004] This section provides background information related to the present disclosure which is not necessarily prior art.

SUMMARY

[0005] This section provides a general summary of the disclosure, and is not a comprehensive disclosure of its full scope or all of its features.

[0006] An intraocular pressure sensor is presented that achieves very low power consumption. The intraocular pressure sensor takes the form of an implantable assembly configured to be implanted in an eye of a subject. Specifically, the implantable assembly is comprised of a capsular tension ring attached to a flexible printed circuit board. The flexible printed circuit board includes a cutout that is sized to encircle the pupil of the eye. One or more electrical components are also mounted onto the flexible printed circuit board.

[0007] In one embodiment, a pressure sensing element, a voltage reference generator, a power management unit and a controller are mounted to the implantable assembly. The pressure sensing element operates to output a measureable value, such that the measureable value changes in response to pressure applied to the pressure sensing element. The controller is interfaced with the pressure sensing element and receives the output from the pressure sensing element. In response to receiving the output, the controller converts the output to a digital form and stores the digital form of the output in a data store residing on the implantable assembly. The voltage reference generator generates a voltage that drives the controller and the power management unit is interconnected between the voltage reference generator and the controller.

[0008] In one aspect, the voltage reference generator includes a first metal-oxide semiconductor field-effect transistor (MOSFET) and a second MOSFET in a stacked arrangement, such that a body terminal of the first MOSFET is biased with a voltage that is different than voltage at a source terminal of the first MOSFET and voltage at a drain terminal of the first MOSFET. More specifically, the first MOSFET of the voltage reference generator has a source terminal, a drain terminal, a gate terminal and a body terminal, where the gate terminal of the first MOSFET is coupled to the source terminal of the first MOSFET; and the second MOSFET of the voltage reference generator has same type of charge carrier as the first MOSFET and is configured with the first MOSFET such that a reference voltage is generated at a node interconnecting the first MOSFET to the second MOSFET, where threshold voltage of the first MOSFET and threshold voltage of the second MOSFET are designed to be the same and the gate terminal of the second MOSFET is coupled to the drain terminal of the second MOSFET. The voltage reference generator may further include a bias circuit configured to bias the body terminal of the first MOSFET with a bias voltage that changes with temperature changes so that the reference voltage is temperature independent.

[0009] Further areas of applicability will become apparent from the description provided herein. The description and specific examples in this summary are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure. DRAWINGS

[0010] The drawings described herein are for illustrative purposes only of selected embodiments and not all possible implementations, and are not intended to limit the scope of the present disclosure.

[0011] Figure 1 is a perspective view of an intraocular pressure sensor;

[0012] Figures 2A and 2B are a front view and a cross-section side view of an eye, respectively, illustrating the placement of the intraocular pressure sensor in the eye of a subject;

[0013] Figure 3 is a block diagram of the components comprising the intraocular pressure sensor;

[0014] Figure 4 shows a simplified circuit of proposed voltage reference circuit;

[0015] Figure 5 is a graph showing how Vbody tracks Vdd change and creates constant VBS for the first MOSFET;

[0016] Figure 6 is a schematic of the proposed voltage reference circuit with stacked PMOS diodes;

[0017] Figure 7 is a schematic of a variant of the voltage reference circuit implemented with n-type transistors;

[0018] Corresponding reference numerals indicate corresponding parts throughout the several views of the drawings.

DETAILED DESCRIPTION

[0019] Example embodiments will now be described more fully with reference to the accompanying drawings.

[0020] Figure 1 depicts an example embodiment for an intraocular pressure sensor 10 that is configured to be implanted in an eye of a subject. In an example embodiment, an implantable assembly is comprised of a capsular tension ring 12 coupled to a flexible printed circuit board 14. The flexible printed circuit board 14 may include a cutout that is sized to encircle the pupil of the eye. In addition, the printed circuit board has a“C” shape such that one section of the circular form remains open to the cutout. This allows one end of the capsular tension ring to be inserted through an incision in the eye and fed into the eye in circular motion to encircle the pupil of the eye. This allows the size of the necessary incision in the eye to be limited to only the width of the printed circuit board and not the width of the entire implantable assembly. One or more electrical components 16 are in turn mounted onto the flexible printed circuit board 14 such that the electrical components are mounted along periphery of the assembly and do not interfere with the subject’s vision. For example, the electrical components may be epoxied onto the circuit board 14. For further details regarding an exemplary implantable assembly, reference may be had to the EYEMATE® sensor manufactured by Implandata Ophothalmic Products GmbFI.

[0021] Figures 2A and 2B illustrate the placement of the intraocular pressure sensor 10 in the eye 20 of the subject. More specifically, the intraocular pressure sensor 10 is placed behind the iris 21 and pupil 22 of the eye in the posterior chamber. It is understood that different type of medical procedures may be used to place the intraocular pressure sensor 10 in the eye but such procedures fall outside the scope of this disclosure.

[0022] Components which comprise the intraocular pressure sensor 10 are further described in relation to Figure 3. In the example embodiment, the intraocular pressure sensor 10 is comprised of a pressure sensing element 31 , a voltage reference generator 32, a power management unit 33 and a controller 34. Each of these components is further described below. It is to be understood that these components are required, but that other components may be needed to control and manage the overall operation of the sensor.

[0023] The pressure sensing element 31 is attached to the implantable assembly and operates to output a measureable value (e.g., capacitance or resistance), such that the measureable value changes in response to pressure applied to the pressure sensing element. In one embodiment, the pressure sensing element is a piezoelectric membrane that changes resistance as it deflects due to the applied pressure. In another embodiment, it is a conductive membrane that covers a vacated cavity and causes the capacitance between the membrane and the cavity to change as the membrane deflects due to the applied pressure. Other types of pressure sensing elements also fall within the scope of this disclosure.

[0024] A controller 34 is interfaced with the pressure sensing element 31 and configured to receive the output from the pressure sensing element 31. In response to receiving the output, the controller 34 converts the output to a digital form and stores the digital form of the output in a data store (e.g., a transitory or non-transitory memory). In an exemplary embodiment, the controller 34 is implemented as a microcontroller. It should be understood that the logic for the controller 34 can be implemented in hardware logic, software logic, or a combination of hardware and software logic. In this regard, controller 34 can be or can include any of a digital signal processor (DSP), microprocessor, microcontroller, or other programmable device which are programmed with software implementing the above described methods. It should be understood that alternatively the controller is or includes other logic devices, such as a Field Programmable Gate Array (FPGA), a complex programmable logic device (CPLD), or application specific integrated circuit (ASIC). When it is stated that controller 34 performs a function or is configured to perform a function, it should be understood that controller 34 is configured to do so with appropriate logic (such as in software, logic devices, or a combination thereof).

[0025] The voltage reference generator 32 operates to generate a voltage that drives the controller 34. As will be further described below, the voltage reference generator 32 is implemented by a circuit that provides inherently low process variation and low power consumption. The power management unit 33 is interconnected between the voltage reference generator 32 and the controller 34. In one embodiment, the power management unit 33 is a voltage regulator circuit. The voltage regulator circuit receives a reference voltage from the voltage reference generator 32 and provides a stable voltage to the controller 34. Those skilled in the art will recognize that suitable regulator circuits are readily found in the art. In another embodiment, the power management unit 33 converts an input voltage within a 0.9-to-4V range to 3 fixed output voltages: 0.6V, 1.2V and 3.3V. Further details regarding such a unit are described by Wanyeong Jung et. al. in“A 60%- Efficiency 20nW-500pW Tri-Output Fully Integrated Power Management Unit with Environmental Adaptation and Load-Proportional Biasing for loT Systems,” IEEE International Solid-State Circuits Conference (ISSCC), February 2016 which is incorporated in its entirety herein.

[0026] The intraocular pressure sensor 10 also includes a power source. The power source supplies power to the power management unit 33. The power source may take different forms. In one form, the power source is a battery. In another form, the power source is comprised of a harvesting subsystem that charges a rechargeable energy storage device 35, such as a capacitor or a battery. The harvesting subsystem may include a harvesting element 36 (e.g., a photovoltaic cell) that generates electrical power and a regulator circuit 37 interfaced with the harvesting element. The regulator circuit converts the electrical power from the harvesting element to a suitable form for charging the rechargeable energy storage device 35. The rechargeable energy storage device 35 can in turn be used to supply power to one or more of the other components of the sensor.

[0027] One embodiment of the regulator circuit 27 is a switched-capacitor DC- DC converter which converts the voltage of the harvesting element 37 to the voltage for the energy storage device 35 through a series of voltage multiplications. Each voltage multiplication can be accomplished by constructing two inverter based ring oscillators, where the outputs of each inverter in one ring is coupled to the output of the corresponding inverter in the second ring. For further details regarding an exemplary switched-capacitor DC-DC converter, reference may be had to U.S. Patent Publication No. 2017/0170722 entitled “Self-oscillating Switched-Capacitor DC-DC Converter” and which is incorporated in its entirety by reference.

[0028] In some embodiments, the intraocular pressure sensor 10 may further include a communication interface. For example, the communication interface may be an LED or another type of light source serving as an optical transmitter 38. In another example, the communication interface may be an RF transmitter or transceiver 39. In either case, the controller 34 cooperatively operates with the optical transmitter or the RF transmitter to transmit the digital form of the output to a device located outside of the eye. In the case of the LED, the external device may be a photodetector, or in the case of the RF transmitter, the external device may be an RF receiver. It is readily understood that these are merely examples of the types of wireless interfaces that may be incorporated into the sensor.

[0029] Similarly, the intraocular pressure sensor 10 may include an optical communication receiver which allows communication from an external device to the sensor 10. In this case, an optical sensor 41 is interfaced via an optical interface 42 to the controller 34. The optical sensor may be a photo sensor or photo voltaic cell which transforms received light to an electrical signal. The controller 34 cooperatively operates with the optical communication interface 42 to receive a digital form of an input from a device located outside of the eye.

[0030] Figure 4 depicts an example embodiment for the voltage reference circuit 32. The proposed voltage reference circuit is comprised of two metal-oxide semiconductor field-effect transistors (MOSFETs) M1 , M2 in a stacked arrangement and a bias circuit 44. In the stacked arrangement, the two MOSFETs M1 , M2 are configured with one of the source terminal and the drain terminal of the first MOSFET M1 coupled to a first supply voltage VDD, and the other of the source terminal and the drain terminal of the first MOSFET is coupled to one of the source terminal and the drain terminal of the second MOSFET M2. The other of the source terminal and the drain terminal of the second MOSFET M2 is coupled to a second supply voltage (e.g., ground). The first MOSFET M1 and the second MOSFET M2 have the same type of charge carrier and the particular terminal connections will depend upon the type of charge carrier as further described below.

[0031] Additionally, the gate terminal of the first MOSFET M1 is coupled to the source terminal of the first MOSFET M1 and the gate terminal of the second MOSFET M2 is coupled to the drain terminal of the second MOSFET M2. Of note, the body terminal of the first MOSFET M1 is biased with a voltage that is different than the voltage at either the source terminal or the drain terminal of the first MOSFET M1. It is also noted that the threshold voltage Vthi of the first MOSFET M1 and threshold voltage Vth2 of the second MOSFET M2 are designed and manufactured to be the same.

[0032] In a first example embodiment, the first MOSFET M1 and second MOSFET M2 are p-type as seen in Figure 4. In the stacked arrangement, source terminal of the first MOSFET M1 is electrically coupled to the upper supply voltage (Vdd) while the drain terminal of the first MOSFET M1 is electrically coupled to the source terminal of the second MOSFET M2 and the drain terminal of the second MOSFET M2 is electrically coupled to the lower supply voltage (e.g., ground). The reference voltage Vref is generated at an output node interconnecting the first MOSFET M1 to the second MOSFET M2.

[0033] In operation, the first MOSFET M1 is forward-biased and provides sub-threshold current flowing through the second MOSFET (i.e. , bottom PMOS diode) M2. The second MOSFET M2 is in an off state. The current equations of M1 and M2 are expressed as in equation (1 ). By solving equation (1 ), V _ref can be expressed as equation (3). As M1 and M2 are the same type of charge carrier (i.e, PMOS), the difference between Vmi and V comes solely from the body bias effect of M1. Random Vm mismatch is kept negligible by upsizing (e.g., > 20 pm ² ) of all 4 devices in this reference circuit.

[0034] The bias circuit 42 is configured to output the voltage that biases the body terminal of the first MOSFET M1. In the example embodiment, the bias circuit 44 is comprised of transistors having the same type of charge carrier as the first MOSFET M1 and the second MOSFET M2. That is, the third MOSFET M3 and the fourth MOSFET M4 are p-type as well. More specifically, the third MOSFET M3 and the fourth MOSFET M4 are in a stacked arrangement, such that the drain terminal of the third MOSFET M3 is electrically coupled at a bias node to the source terminal of the fourth MOSFET M4. The bias node is also electrically coupled to the body terminal of the first MOSFET to supply the bias voltage thereto.

[0035] In operation, the third MOSFET M3 and the fourth MOSFET M4 generate the required body bias for first MOSFET M1. More specifically, the fourth MOSFET M4 is an off-state PMOS; whereas, the third MOSFET is a PMOS diode. The current equations of M3 and M4 are expressed above in equation (2). As the third MOSFET and the fourth MOSFET M3 and M4 are also the same type of PMOS, Vm and Vm are essentially identical. The combination of the third MOSFET M3 and the fourth MOSFET M4 provides a body-bias voltage V _body that tracks V _M and creates a constant VBS ( V _body -V _dd ) for first MOSFET M1 as shown in Figure 5. If the current through third MOSFET M3 (k) is much larger than the parasitic diode current (I _di o) from the source to the N-well of M1 , V _ref can be expressed by equation (4). The left term of Equation (4) is complementary to temperature; whereas, the right term is proportional to temperature. With proper sizing of the four transistors, the first-order temperature dependency can be cancelled out. That is, the bias is circuit can be configured to bias the body terminal of the first MOSFET with a bias voltage that changes with temperature changes so that the reference voltage is temperature independent. Moreover, the threshold voltage Vm does not play a role in equation (4) because each pair (M1/M2 and M3/M4) uses the same type of PMOS, thus significantly reducing process variation. Since I _dio is not well modeled, k is designed to be three orders of magnitude larger than I _dio to minimize the effect of I _dio. Proper sizing of these transistors can be determined using a global optimization tool.

[0036] Variants of this proposed design are contemplated by this disclosure. Referring to Figure 6, two or more stacked diodes can replace the second MOSFET M2 and the third MOSFET M3 to generate a higher reference voltage. Multiple voltage reference levels can be generated in this manner. In Figure 6, three stages of PMOS diodes are used in the design to realize an approximately 1V output reference voltage. MIM capacitors CO and C1 (both set to 1.78pF) are used to isolate the reference voltage from high-frequency power supply noise. Except with respect to the differences discussed herein, the voltage reference circuit 60 may be substantially the same voltage reference circuit 32 described above.

[0037] Figure 7 depicts a variant of the voltage reference circuit 70 employing n-type transistors. In this variant, the drain terminal of the first MOSFET M1 is electrically coupled to the upper supply voltage while the source terminal of the first MOSFET M1 is electrically coupled to the drain terminal of the second MOSFET M2. The source terminal of the second MOSFET M2 is electrically coupled to the lower supply voltage, where magnitude of the upper supply voltage is larger than the lower supply voltage. Except with respect to the differences discussed herein, the voltage reference circuit 70 may be substantially the same voltage reference circuit 32 described above.

[0038] The foregoing description of the embodiments has been provided for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure. Individual elements or features of a particular embodiment are generally not limited to that particular embodiment, but, where applicable, are interchangeable and can be used in a selected embodiment, even if not specifically shown or described. The same may also be varied in many ways. Such variations are not to be regarded as a departure from the disclosure, and all such modifications are intended to be included within the scope of the disclosure.