Title:
INVERTER SYSTEM AND INVERTER SYSTEM CONTROL METHOD
Document Type and Number:
WIPO Patent Application WO/2020/255528
Kind Code:
A1
Abstract:
Provided is an inverter system including a level-skip preventing control unit 3 which outputs a gate signal on the basis of a voltage level command V*, the gate signal driving an inverter 4. The level-skip preventing control unit 3 sets a counter C such that, when an output voltage level V of a certain phase has become UP, the output voltage level V of the phase is prohibited from becoming UP for a predetermined time, and such that, for another phase, an output voltage level V is prohibited from becoming DOWN for a predetermined time. The level-skip preventing control unit 3 also sets a counter C such that, when an output voltage level V of a certain phase has become DOWN, the output voltage level V of the phase is prohibited from becoming DOWN for a predetermined time, and such that, for another phase, an output voltage level V is prohibited from becoming UP for a predetermined time. In this way, in an inverter system having an arbitrary number of phases and an arbitrary number of levels, a level-skip of line voltage is suppressed.
Inventors:
OGAWA RYUICHI (JP)
HAMADA SHIZUNORI (JP)
HAMADA SHIZUNORI (JP)
Application Number:
PCT/JP2020/014732
Publication Date:
December 24, 2020
Filing Date:
March 31, 2020
Export Citation:
Assignee:
MEIDENSHA ELECTRIC MFG CO LTD (JP)
International Classes:
H02M7/48
Foreign References:
| JP2018117423A | 2018-07-26 | |||
| JP2015220765A | 2015-12-07 | |||
| JP2015002639A | 2015-01-05 | |||
| JP2006109688A | 2006-04-20 |
Attorney, Agent or Firm:
KOBAYASHI, Hiromichi et al. (JP)
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