Title:
INVERTIBLE LOGIC CIRCUIT DEVICE
Document Type and Number:
WIPO Patent Application WO/2019/208581
Kind Code:
A1
Abstract:
Provided is an invertible logic circuit device wherein the circuit can easily be configured by means of hardware. This invertible logic circuit device is configured so as to be equipped with a plurality of nodes, including nodes 11(x), 12(y), and 13(z) corresponding to an input terminal and an output terminal of a computation circuit, and a Boltzmann machine in which a weight coefficient value and a coupling coefficient value are set on the basis of an input/output relationship of the computation circuit. The node corresponding to the output terminal 13(z) has a fixed output circuit 114 for which the output value is fixed as 1 or 0, and the nodes 11(x) and 12(y) corresponding to the input terminal have a probability computation block (11a, 11b) that uses an output value from another coupled node and a random number from the outside, as well as the weight coefficient and the coupling coefficient, to carry out a stochastic computation in accordance with a prescribed algorithm based on the function of the Boltzmann machine, and that outputs a bit value of the computation result as an output value for the relevant node.
Inventors:
HANYU TAKAHIRO (JP)
ONIZAWA NAOYA (JP)
GROSS WARREN J (CA)
SMITHSON SEAN (CA)
LUGOSCH LOREN (CA)
ONIZAWA NAOYA (JP)
GROSS WARREN J (CA)
SMITHSON SEAN (CA)
LUGOSCH LOREN (CA)
Application Number:
PCT/JP2019/017276
Publication Date:
October 31, 2019
Filing Date:
April 23, 2019
Export Citation:
Assignee:
UNIV TOHOKU (JP)
International Classes:
G06N3/063
Foreign References:
| US20150039546A1 | 2015-02-05 |
Other References:
CAMSARI, K. Y. ET AL.: "Stochastic p-bits for Invertible Logic", PHYSICAL REVIEW X, 21 July 2017 (2017-07-21), pages 1 - 19, XP055647853
MOMOI, A. ET AL.: "Implementation of a Large Scale Hardware Neural Network System based on Stochastic Logic", PROCEEDINGS OF 2004 IEEE INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORKS, 29 July 2004 (2004-07-29), pages 2671 - 2675, XP010759369, ISBN: 0-7803-8359-1, DOI: 10.1109/IJCNN.2004.1381070
BROWN, B.D. ET AL.: "Stochastic Neural Computation I: Computational Elements", IEEE TRANSACTIONS ON COMPUTERS, vol. 50, no. 9, September 2001 (2001-09-01), pages 891 - 905, XP055324010, ISSN: 0018-9340, DOI: 10.1109/12.954505
ARDAKANI, A. ET AL.: "VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing", IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, vol. 25, no. 10, 1 February 2017 (2017-02-01), pages 2688 - 2699, XP011661467, ISSN: 1063-8210, DOI: 10.1109/TVLSI.2017.2654298
KATAGIRI, D. ET AL.: "Design of a Stochastic Gabor Filter for Highly Parallel Feature-Extraction Hardware", IEICE TECHNICAL REPORT, vol. 115, no. 318, 13 November 2015 (2015-11-13), Japanese, pages 35 - 40, ISSN: 0913-5685
KIKUCHI, Y. ET AL.: "An Execution System of Logic Programming Language Using Neural Networks - An Improvement of the Transformation Algorithm Proceedings of IECON", ANNUAL CONFERENCE OF THE IEEE INDUSTRIAL ELECTRONICS SOCIETY, 4 September 1998 (1998-09-04), pages 40 - 45, XP010308130, ISBN: 0-7803-4503-7
KIKUCHI, Y. ET AL.: "An Execution System of Logic Programming Language Using Neural Networks", IEICE TECHNICAL REPORT, vol. 97, 30 January 1998 (1998-01-30), Japanese, pages 37 - 44, ISSN: 0913-5685
MOMOI, A. ET AL.: "Implementation of a Large Scale Hardware Neural Network System based on Stochastic Logic", PROCEEDINGS OF 2004 IEEE INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORKS, 29 July 2004 (2004-07-29), pages 2671 - 2675, XP010759369, ISBN: 0-7803-8359-1, DOI: 10.1109/IJCNN.2004.1381070
BROWN, B.D. ET AL.: "Stochastic Neural Computation I: Computational Elements", IEEE TRANSACTIONS ON COMPUTERS, vol. 50, no. 9, September 2001 (2001-09-01), pages 891 - 905, XP055324010, ISSN: 0018-9340, DOI: 10.1109/12.954505
ARDAKANI, A. ET AL.: "VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing", IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, vol. 25, no. 10, 1 February 2017 (2017-02-01), pages 2688 - 2699, XP011661467, ISSN: 1063-8210, DOI: 10.1109/TVLSI.2017.2654298
KATAGIRI, D. ET AL.: "Design of a Stochastic Gabor Filter for Highly Parallel Feature-Extraction Hardware", IEICE TECHNICAL REPORT, vol. 115, no. 318, 13 November 2015 (2015-11-13), Japanese, pages 35 - 40, ISSN: 0913-5685
KIKUCHI, Y. ET AL.: "An Execution System of Logic Programming Language Using Neural Networks - An Improvement of the Transformation Algorithm Proceedings of IECON", ANNUAL CONFERENCE OF THE IEEE INDUSTRIAL ELECTRONICS SOCIETY, 4 September 1998 (1998-09-04), pages 40 - 45, XP010308130, ISBN: 0-7803-4503-7
KIKUCHI, Y. ET AL.: "An Execution System of Logic Programming Language Using Neural Networks", IEICE TECHNICAL REPORT, vol. 97, 30 January 1998 (1998-01-30), Japanese, pages 37 - 44, ISSN: 0913-5685
Attorney, Agent or Firm:
EICHI PATENT & TRADEMARK CORP. (JP)
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