Title of Invention: AN ION SENSITIVE FIELD EFFECT

TRANSISTOR

[ 1 ] FIELD OF INVENTION

[2] The present invention relates to an ion sensitive field effect transistor (ISFET).

[3] BACKGROUND OF THE INVENTION

[4] Silicon-based chemical sensors are quite popular technology nowadays because of their advantages which are simplicity in function, fast response, small size, rigid design, and projected low cost. Additionally, the silicon technology is a good platform for system integration of chemical sensors because of the process compatibility with integrated circuit (IC) technology. Ion sensitive field effect transistor (ISFET) pH sensor is a silicon based device. A conventional ISFET structure is similar to Metal- Oxide-Semiconductor Field Effect Transistor (MOSFET) but without gate electrode deposited on gate insulator exposing the insulator layer (sensing membrane) to an electrolyte solution. The basic idea of an ISFET is to remove the metal plate of an MOSFET and expose the oxide insulator to an electrolyte. This insulator will then interact with the solution and creates an electrolyte-insulator interfacial potential which is directly modulate the channel conductivity between the source and the drain terminal. Basically the amount of current flowing through the channel between the source and the drain is a measure of the amount of inversion charge in the channel which, by charge neutrality of the entire device, the inversion charge must be equal to the amount of charges on the upper side of the insulator layer. It can be seen as a charge sensor device. To ensure high signal-to-noise ratio (SNR), sufficient sensing area must be exposed to the electrolyte. Currently the planar membrane has limited exposed area to the ions in the sample to be tested hence limiting the sensitivity and efficiency of the device. Miniaturization of ISFET for integrated micro and nano-sensor system will further reduce the gate size and minimize the sensing area which will degrade the sensor signal.

[5] One of the examples isEP 1706734which relates toanon sensitive field effect

transistor pH sensor is provided with an improved sensor gate configuration.

Specifically, a tantalum oxide-sensing gate is disposed on top of an alumina layer. The tantalum oxide-sensing gate provides advantageous sensitivity, while the alumina barrier layer increases sensor longevity in situations where the sensor is exposed to caustic cleaning processes such as Clean In Place processes.

[6] Miniaturization of ISFET for integrated micro and nano-sensor system would further reduce the gate size and minimize the sensing area which would also degrade the sensor signal.

[7] Therefore there is a need for an invention which provides solution to the problem.

[8] SUMMARY OF THE INVENTION

[9] According to an aspect of the present invention, the present invention provides an ion sensitive filed effect transistor comprising: a semiconductor substrate (101); a channel region (103) havingdoped polysilicon layer of at least 5el6 per cubic centimeter for conducting the current,formed over the semiconductor substrate (101); a drain region (105); a source region (107), wherein the source region (107) and the drain region (105) vertically connected to the channel region (103); a gate insulating layer (109); and a sensing membrane layer (111); characterized in that the gate insulating layer (109) and the sensing membrane layer (111) are formed along substantially all of the side walls of the channel region (103) to create a vertical multigate electrodes.

[10] The above provision is advantageous as the polysilicon layer is used as an active region predetermined channel for a transistor to build vertical field effect transistor. The present invention provides ISFET with multi-dimensional sensing membrane (111). It is an improvement of the current ISFET design which uses planar structure for the sensing membrane. The built-up of the multi-gate vertical ISFET of the present invention increases the membrane's surface area thus improving the sensitivity of the device.

[11] BRIEF DESCRIPTION OF THE DRAWINGS

[12] Figure 1 illustrates cross section view of the present invention.

[13] Figure 2 illustrates flowchart of a method for producing the present invention.

[14] Figure 3 illustrates procedural diagrams of the method for producing the present invention.

[15] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[16] The present invention relates to field effect transistors particularly to vertical multi- gate ion sensitive field effect transistors and a method of producing them. Referring to Figure 1, generally, the present invention provides an ion sensitive filed effect transistor comprising: a semiconductor substrate (101); a channel region (103) having adoped polysilicon layer (104) of at least 5el6 per cubic centimeter for conducting the current,formed over the semiconductor substrate (101); a drain region (105); a source region (107), wherein the source region (107) and the drain region (105) vertically connected to the channel region (103); a gate insulating layer (109); and a sensing membrane layer (111); characterized in that the gate insulating layer (109) and the sensing membrane layer (111) are formed along substantially all of the side walls of the channel region (103) to create a vertical multigate electrodes. The sensing membrane layer (111) further comprising silicon nitride and metal oxides in which the metal oxides further comprising Aluminium Oxide; Tantalum Pentoxide; and Hafnium Oxide, or the like.

[17] The present invention comprises of polysilicon layer (104) implanted with high

doping n-type or p-type layer on top for source region and light doping with opposite type dopant at the bottom. The transistor is designed in vertical order, which the drain region (105) is created by ion implantation in silicon substrate (101).

[18] Generally, the methodfor manufacturing a multigate electrode ion sensitive filed

effect transistor comprising: providing semiconductor substrate (201); forming a drain region (203); forming a channel region (205); forming a source region (207); forming a gate insulating layer on the channel region (209); forming a sensing membrane layer on the gate insulating layer (211); and forming special contact holes to connect source and the channel region together (213). The flowchart of the method is illustrated in Figure 2.

[19] Detailed explanations on the process flow with diagram is illustrated in Figure 3, in which the process is started with Step 1. Step 1 is n-type ion implantation on silicon substrate (101) to create drain region (105). The dopant ion used is arsenic or phosphorus. Step 2 is polysilicon deposition. Lightly doped p-type polysilicon layer (104) is used for channel region (103). Step 3 is ion implantation on polysilicon surface for source region (107). The same dopant type and dose as drain region (105) is used. Step 4 is polysilicon gate etch to define active or channel region (103) for the ISFET. The channel region (103) can be fabricated by micro or nano-fabrication techniques, which can be by lithographic patterning, pattern transfer or by thin film deposition and etching methods. Step 5 is gate oxidation/gate insulating layer (109) and sensing membrane layer (111) deposition on polysilicon (104) and sidewalk Both of these layers are performed consecutively with typically same dielectric thickness.

Membranes, which are used as sensor elements themselves or as filters, are key component in many types of sensing devices. There are many types of sensing membrane for FET-based chemical sensor for wide range of sensing applications. The role of a chemical coating in a potentiometric sensor is to make the device selective and sensitive to analytes of interest. As for example in biosensor, enzymes and antibodies based membrane are often used to render a sensor biocompatible or as an inert matrix for active sensor components. But only the inorganic gate materials can be made easily, and the technology is compatible with standard IC technology. For gate oxidation, monocrystalline and poly crystalline silicon surface were oxidized at high temperature, dry process (thermal growing of Si02) to receive target thickness of Si02 layer. Afterwards, for pH sensors a chemosensitive silicon nitride layer is deposited from two gaseous phases in Low Pressure Chemical Vapor Deposition (LPCVD) process. The silicon nitride is formed in the pyrolytic reaction between dichlorosilane and ammonia at high temperature and typically low pressure. Step 6 is when contact holes are created and followed by metallization steps. Special contact for source and polysilicon is created to short the source and channel substrate (PSUB) in single contact hole.

Although the invention has been described with reference to particular embodiment, it is to be understood that the embodiment is merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiment that other arrangements may be devised without departing from the scope of the present invention as defined by the appended claims.