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Title:
AN IONIZATION CHAMBER CHIP FOR A NANO-APERTURE ION SOURCE, METHOD OF FABRICATION THEREOF, AND A PROTON BEAM WRITING SYSTEM
Document Type and Number:
WIPO Patent Application WO/2019/022672
Kind Code:
A1
Abstract:
An ionization chamber chip, a nano-aperture ion source, a proton beam writing system, and a method of fabricating an ionization chamber chip. The method comprises the step of providing a first substrate comprising a first depression formed in a back surface thereof; providing a backing element attached at the back surface of the first substrate such that a chamber is formed comprising at least the first depression; forming a gas inlet in the first substrate in fluid communication with the chamber; and forming a first aperture structure in the first substrate in fluid communication with the chamber.

Inventors:
VAN KAN, Jeroen Anton (Faculty of Science/Department of Physics,,21 Lower Kent Ridge Road, Singapore 7, 119077, SG)
XU, Xinxin (Faculty of Science/Department of Physics,,21 Lower Kent Ridge Road, Singapore 7, 119077, SG)
PATTABIRAMAN, Santhana Raman (Faculty of Science/Department of Physics,,21 Lower Kent Ridge Road, Singapore 7, 119077, SG)
PANG, Rudy (Faculty of Science/Department of Physics,,21 Lower Kent Ridge Road, Singapore 7, 119077, SG)
Application Number:
SG2018/050378
Publication Date:
January 31, 2019
Filing Date:
July 27, 2018
Export Citation:
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Assignee:
NATIONAL UNIVERSITY OF SINGAPORE (21 Lower Kent Ridge Road, Singapore 7, 119077, SG)
International Classes:
H01J27/20; H01J37/08; H01J37/317; H01J49/14
Foreign References:
US20140001372A12014-01-02
Other References:
JUN, D.S.: "Development of the Nano-Aperture Ion Source (NAIS)", DOCTORAL THESIS, 6 November 2014 (2014-11-06), pages 65 - 79, ISBN: 9789461863843, Retrieved from the Internet [retrieved on 20180925]
LIU NANNAN: "DEVELOPMENT OF AN ELECTRON IMPACT GAS ION SOURCE FOR PROTON BEAM WRITING APPLICATIONS", A THESIS SUBMITTED FOR THE DEGREE OFDOCTOR OF PHILOSOPHY, 30 September 2015 (2015-09-30), pages 60 - 65, XP055569337, Retrieved from the Internet [retrieved on 20180925]
XU XINXIN: "DEVELOPMENT AND OPTIMIZATION OF HIGH BRIGHTNESS NANO- APERTURE ION SOURCE FOR PROTON BEAM WRITING APPLICATIONS", THESIS, 25 August 2017 (2017-08-25), pages 112 - 114, 126-128, XP055569358, Retrieved from the Internet [retrieved on 20180925]
Attorney, Agent or Firm:
VIERING, JENTSCHURA & PARTNER LLP (P.O. Box 1088, Rochor Post Office,,Rochor Road, Singapore 3, 911833, SG)
Download PDF:
Claims:
CLAIMS

What is claimed is:

1. An ionization chamber chip for a nano-aperture ion source, the ionization chamber chip comprising:

a first substrate comprising a first depression formed in a back surface thereof;

a backing element attached at the back surface of the first substrate such that a chamber is formed comprising at least the first depression;

a gas inlet formed in the first substrate in fluid communication with the chamber; and a first aperture structure formed in the first substrate in fluid communication with the chamber.

2. The ionization chamber of claim 1, further comprising an electrode layer formed on the back surface of the first substrate, the electrode layer extending into the first depression.

3. The ionization chamber of claims 1 or 2, wherein the first aperture structure comprises an array of beams/grids formed in a bulk material of the first substrate and an aligned array of aperture holes formed in a material layer forming the back surface of the first substrate.

4. The ionization chamber of any one of the preceding claims, wherein the backing element comprises a sheet.

5. The ionization chamber of any one of the preceding claims, comprising pillars formed on the back surface of the first substrate configured to reduce deformation of the sheet in the region adjacent the first aperture structure.

6. The ionization chamber of claim 5, wherein the pillars are formed as one integral layer etched down into the back surface of the first substrate.

7. The ionization chamber of claim 5, wherein the pillars are formed as one integral layer patterned in a high-resolution resist.

8. The ionization chamber of any one of the preceding claims, wherein the backing element comprises an array of aperture holes formed therein and aligned with the aperture holes formed in the material layer.

9. The ionization chamber of any one of the preceding claims, comprising an array of secondary electron emitters disposed in the first substrate or in the backing element.

10. The ionization chamber of any one of the preceding claims, wherein the backing element comprises a second substrate comprising a second depression formed in a back surface thereof, wherein the first and second substrates are attached to each other at the respective back surfaces such that the chamber comprises the adjoining first and second depressions, and

wherein the second aperture structure comprises an array of beams/grids formed in a bulk material of the second substrate and an aligned array of aperture holes formed in a material layer forming the back surface of the second substrate.

11. The ionization chamber of any one of claims 1 to 9, wherein the backing element comprises a second substrate comprising a second depression formed in a back surface thereof; wherein the first and second substrates are attached to each other at the respective back surfaces such that a chamber is formed comprising the adjoining first and second depressions; and

wherein the first and second aperture structures are formed a double aperture structure extending through respective thicknesses of the first and second substrates in fluid

communication with the chamber.

12. The ionization chamber of any one of the preceding claims, further comprising

a first electrode layer formed on a front surface of the first substrate opposite to the back surface; and

a second electrode layer formed on a front surface of the second substrate opposite to the back surface.

13. The ionization chamber of claim 12, wherein the first electrode layer extends at least partially along a wall of the gas inlet and a wall of the double aperture and wherein the second electrode layer extends at least partially along the wall of the double aperture.

14. The ionization chamber of any one of the preceding claims, wherein the gas inlet comprises an inlet aperture extending through the thickness of the first substrate.

15. The ionization chamber of any one of the preceding claims, wherein the second substrate comprises a filled depression at a corresponding lateral position to the inlet aperture, relative to the attached back surfaces.

16. A nano-aperture ion source comprising the ionization chamber chip of any one of the preceding claims.

17. A proton beam writing system comprising the nano-aperture ion source of claim 16.

18. A method of fabricating an ionization chamber chip for a nano-aperture ion source, the method comprising the steps of:

providing a first substrate comprising a first depression formed in a back surface thereof;

providing a backing element attached at the back surface of the first substrate such that a chamber is formed comprising at least the first depression;

forming a gas inlet in the first substrate in fluid communication with the chamber; and forming a first aperture structure in the first substrate in fluid communication with the chamber.

19. The method as claimed in claim 18, further comprising forming an electrode layer on the back surface of the first substrate, the electrode layer extending into the first depression.

20. The method as claimed in claims 18 or 19, wherein the first aperture structure comprises an array of beams/grids formed in a bulk material of the first substrate and an aligned array of aperture holes formed in a material layer forming the back surface of the first substrate.

21. The method as claimed in any one of claims 18 to 20, wherein the backing element comprises a sheet.

22. The method as claimed in any one of claims 18 to 21, comprising forming pillars on the back surface of the first substrate configured to reduce deformation of the sheet in the region adjacent the first aperture structure.

23. The method as claimed in claim 22, wherein the pillars are formed as one integral layer etched down into the back surface of the first substrate.

24. The method as claimed in claim 22, wherein the pillars are formed as one integral layer etched patterned in a high-resolution resist.

25. The method as claimed in any one of claims 18 to 24, wherein the backing element comprises an array of aperture holes formed therein and aligned with the aperture holes formed in the material layer.

26. The method as claimed in any one of claims 18 to 25, comprising disposing an array of secondary electron emitters in the first substrate or in the backing element.

27. The method as claimed in any one of claims 18 to 26, wherein the backing element comprise a second substrate comprising a second depression formed in a back surface thereof, wherein the first and second substrates may be attached to each other at the respective back surfaces such that the chamber comprises the adjoining first and second depressions, and wherein forming the second aperture structure comprises forming an array of beams/grids in a bulk material of the second substrate and forming an aligned array of aperture holes in a material layer forming the back surface of the second substrate.

28. The method as claimed in any one of claims 18 to 26, wherein the backing element comprises a second substrate comprising a second depression formed in a back surface thereof; wherein the first and second substrates are attached to each other at the respective back surfaces such that a chamber is formed comprising the adjoining first and second depressions; and

the method further comprises forming a double aperture comprising the first and second aperture structures, the double aperture extending through respective thicknesses of the first and second substrates in fluid communication with the chamber.

29. The method as claimed in any one of claims 18 to 28, further comprising

forming a first electrode layer on a front surface of the first substrate opposite to the back surface; and

forming a second electrode layer on a front surface of the second substrate opposite to the back surface.

30. The method as claimed in claim 29, wherein the first electrode layer extends at least partially along a wall of the gas inlet and a wall of the double aperture and wherein the second electrode layer extends at least partially along the wall of the double aperture.

31. The method as claimed in any one of claims 18 to 30, wherein the gas inlet comprises an inlet aperture extending through the thickness of the first substrate.

32. The method as claimed in any one of claims 18 to 31, comprising forming a filled depression in the second substrate at a corresponding lateral position to the inlet aperture, relative to the attached back surfaces.

33. The method as claimed in any one of claims 18 to 32, wherein the first and second substrates are batch processed prior to being attached to each other at the respective back surfaces.

34. The method as claimed in claim 33, wherein the batch processing comprises simultaneously forming respective portions of the double aperture in the first and second substrates.

35. The method as claimed in claims 33 or 34, wherein the batch processing comprises simultaneously forming a portion of the gas inlet and a corresponding depression in the first and second substrates, respectively.

36. The method as claimed in any one of claims 33 to 35, wherein the batch processing comprises simultaneously forming the first and second electrode layers on the front surfaces of the first and second substrates, respectively.

Description:
AN IONIZATION CHAMBER CHIP FOR A NANO-APERTURE ION SOURCE, METHOD OF FABRICATION THEREOF, AND A PROTON BEAM WRITING

SYSTEM

TECHNICAL FIELD

[0001] This invention relates broadly to an ionization chamber chip, a nano-aperture ion source, to a proton beam writing (c-PBW) system, in particular to a compact c-PBW system, and to a method of fabricating an ionization chamber chip.

BACKGROUND

[0002] Any mention and/or discussion of prior art throughout the specification should not be considered, in any way, as an admission that this prior art is well known or forms part of common general knowledge in the field.

[0003] Proton beam writing (PBW) is a direct-write lithographic technique developed in the Centre for Ion Beam Applications, National University of Singapore (CIBA-NUS), which employs focused protons, for fabricating three-dimensional nano-structures [1-3]. Compared with electron beam lithography (EBL), the advantage of PBW is that a proton is ~ 1800 times heavier than an electron, which makes a proton transferring less energy to secondary electrons and thus penetrating further into the material, depositing a constant energy along its path in the resist [4]. With these unique features, PBW can fabricate nano-structures without proximity effects, and having smooth sidewalls [3,5] . Currently, the performance of PBW in terms of spot size and throughput is limited by low brightness -20 A/(m 2 srV) of the radio frequency (RF) ion source, available in current PBW systems [6,7]. Therefore, a high brightness ion source is desirable to further improve the performance of PBW systems.

[0004] The reduced brightness is an important parameter to exemplify beam quality, like beam current density, beam angular spread, and beam energy spread [8,9]. Reducing the virtual source size is a practical way to obtain a high brightness ion source [10]. High brightness ion sources, like liquid metal ion source (LMIS) and gas field ionization source (GFIS), have small virtual source sizes. LMIS is the most widely used high brightness ion source, which has a liquid metal reservoir on top of a sharp tip [11-13]. A strong electric field is used to pull the liquid metal to a sharp electrospray cone, known as Taylor cone [14]. [0005] Meanwhile this strong electric field also generates ions at the tip of the Taylor cone by field evaporation. The most often used LMIS is Ga- LMIS but several other metals (e.g. Al, In, Sn, Cs, Bi, Au) as well as alloy metals (Au-Si, Au-Ge, Si-Be-Au, Ni-B-Pt) are also used [11]. The typical virtual source size of Ga-LMIS is about 50 nm and the reduced brightness is about 10 6 A/(m 2 srV) with typical energy spread of around 5 eV [11,15,16]. However, the choice of ions from the LMIS is limited to metallic ions, and the energy spread results in high chromatic aberration. GFIS has recently emerged as a possible choice for high brightness ion source, which is based on the field ionization created by strong electric field [17-19]. A strong electric field is concentrated at the apex of a pyramidal tip, which terminates with three atoms. GFIS has been mostly used for generating He and Ne ions [19,20]. For He-GFIS, the reduced brightness can reach as high as 10 9 A/(m 2 srV) with a 1 eV energy spread [21]. The small virtual source size (< 1 nm), due to the three-atom terminated tip, results in having high brightness [22,23]. While the GFIS can deliver an extremely high brightness ion beam, it is limited by the variety of available ion species. Another approach to obtain a high brightness ion source is to reduce the beam angular spread, which can be achieved by reducing the source operating temperature (<100 μΚ). Such ion sources, operating at low temperatures (usually achieved by laser cooling), are called cold atom ion sources. These ion sources have a theoretical reduced brightness of around 10 7 A/(m 2 srV), with < 0.5 eV energy spread [24-27]. Using laser-cooled Cr atoms and Li atoms, beams with reduced brightness of 2.25 x 10 4 A/(m 2 srV) [28] and 6 x 10 3 A/(m 2 srV) [29] have been achieved, respectively. Although these ion sources can deliver high brightness ion beams, they are not designed to produce high brightness proton beams. A nano-aperture ion source (NAIS) with an estimated brightness of 10 6 A/(m 2 srV) has been reported by the Charged Particle Optics group at Delft University of Technology [30]. This NAIS is expected to generate high brightness proton beams. Thus NAIS is a prospective candidate for a sub-10 nm PBW system, which can deliver high throughput. This system is expected to achieve writing speed comparable to those in EBL without the unwanted proximity effect [31].

[0006] Embodiments of the present invention seek to address one or more of the above- mentioned needs. SUMMARY

In accordance with a first aspect an ionization chamber chip for a nano-aperture ion source is provided, the ionization chamber chip comprising:

a first substrate comprising a first depression formed in a back surface thereof;

a backing element attached at the back surface of the first substrate such that a chamber is formed comprising at least the first depression;

a gas inlet formed in the first substrate in fluid communication with the chamber; and a first aperture structure formed in the first substrate in fluid communication with the chamber.

In accordance with a second aspect a nano-aperture ion source is provided comprising the ionization chamber chip of the first aspect.

In accordance with a third aspect proton beam writing system is provided comprising the nano-aperture ion source of the second aspect.

In accordance with a fourth aspect a method of fabricating an ionization chamber chip for a nano-aperture ion source is provided, the method comprising:

providing a first substrate comprising a first depression formed in a back surface thereof;

providing a backing element attached at the back surface of the first substrate such that a chamber is formed comprising at least the first depression;

forming a gas inlet in the first substrate in fluid communication with the chamber; and forming a first aperture structure in the first substrate in fluid communication with the chamber.

DETAILED DESCRIPTION

[0007] The mechanism of NAIS is to extract ions from electron-gas collision, which creates ionization, in a sub-micron ionization chamber. This is a simple and reliable ionization approach to generate various types of ions. The superiority of NAIS is to reduce the virtual source size to sub-micrometer while maintaining a strong electric field (~ 10 7 V/m) with a small chip bias (~ 1 V), resulting in an ion energy spread of 1 eV [30]. Furthermore, the versatility of NAIS makes it convenient to select different ion species spanning from low Z to heavy Z gaseous elements, catering to different applications. The inventors have recognized that these virtues critically depend on the ionization chamber to deliver high brightness ions. The inventors found that the ion brightness of existing NAIS was critically limited by large dimension (600 nm height) of the ionization chamber, thick silicon nitride membranes (1 μm), and a large double-aperture (1.5 μm) [32,33]. Therefore, a modified ionization chamber is fabricated according to example embodiments of the present invention described herein to further improve the performance of NAIS.

[0008] In one non-limiting example embodiment, an approximately or exactly 7 mm x 1 mm x 300 nm NAIS ionization chamber is fabricated by bonding, in an example embodiment by gluing, two chips 202, 204 with respective silicon nitride membranes 203, 205, as shown in Fig. 1. A microelectromechanical system (MEMS) technique may be used in the example embodiment. The step-by- step fabrication procedure according to a non-limiting example embodiment is schematically shown in Fig. 2. As illustrated in step (e), the ionization chamber 200 is formed from top and bottom chips 202, 204 of an approximately or exactly 400 μm thick <100> silicon wafer, respectively. The silicon wafer was double- side-polished with an approximately or exactly 280 nm low-pressure chemical vapor deposited (LPCVD) silicon nitride on both sides, according to an example embodiment. To advantageously enable batch production, the top and bottom chips 202, 204 are designed to be identical to each other, according to an example embodiment. In order to create the gas inlet 206, electron beam inlet 208 window, and ion beam outlet 209 window (inlet 208 window and outlet 209 window jointly also referred to as double-aperture 211 hereinafter), the front side of each wafer 202, 204 is spin-coated in an example embodiment with approximately or exactly 2.5 μm thick AZ 1518 photoresist (not shown), followed by an approximately or exactly 50 s soft bake at 100 °C. Subsequently, the photoresist is exposed in an example embodiment with an approximately or exactly 405 nm laser to pattern mask regions for the windows. The photoresist with the exposed mask regions is developed in AZ 400k developer diluted to 1:4 with DI water for approximately or exactly 1 min in an example embodiment. The patterned opening for the windows are then transferred to the silicon nitride layer 210 of the top and bottom chips 202, 204 forming openings 212, 214, in an example embodiment through deep reactive ion etching (DRIE) with process parameters of approximately or exactly 48 seem CHF 3 , approximately or exactly 5 seem O 2 , approximately or exactly 15 Pa pressure, and approximately or exactly 250 W RF power, as shown in step (a). This is followed by stripping of the residual AZ 1518 resist in acetone, opening up access holes 216, 218 by etching the exposed Si in KOH in an example embodiment (step (b)) creating a freestanding silicon nitride membrane 220, and electrode formation by depositing a conductive layer 219 (in an example embodiment approximately or exactly 10 nm Cr and 20 nm Au) via magnetron sputtering in an example embodiment on the side of the wafers 202, 204 where the openings 212, 214 and access holes 216, 218 are formed (step (c)), hereinafter referred to as the front side for ease of reference. On completing the process steps at the front side of the wafers 202, 204, a fabrication process is carried out at the back side of the wafers 202, 204 (i.e. the side opposite to the side of the wafers 202, 204 where the openings 212, 214 and access holes 216, 218 are formed) to create the ionization chamber 200. For the back side, in an example embodiment the wafers 202, 204 are spin-coated with approximately or exactly 5 μm thick AR-P 3250 photoresist followed by approximately or exactly 2 min soft bake at approximately or exactly 95 °C. The ionization channel pattern is exposed in an example embodiment using an approximately 365 nm ultraviolet (UV) and developed in an example embodiment in AR 300-26 developer diluted to approximately or exactly 3:2 in DI water for approximately or exactly 1.5 min. The back side of the wafers 202, 204, i.e. the silicon nitride membrane 220 in an example embodiment is dry-etched down to approximately or exactly 150 nm depth in a selected window 222 (see step (d)). The two chips 202, 204 are then bonded back face to back face to form the overall NAIS chip 224 (see step (e)) to create an ionization chamber with, in an example embodiment, a dimension of approximately or exactly 7 mm x 1 mm x 300 nm. In an example embodiment the gas inlet aperture 206 and the double-aperture 211 (i.e. the electron inlet 208 window and the ion beam outlet 209 window) are created with the aid of gallium FIB milling (FEI Quanta Dual Beam). The double-aperture 211 size in an example embodiment is set to be approximately or exactly 500 nm. The opening 221 at the side of the NAIS chip 224 on which, in use, the ion beam exits the ionization chamber 200, hereinafter referred to as the bottom side of the NAIS chip 224, is sealed off in an example embodiment using vacuum glue for retaining better gas pressure within the ionization chamber 200. Step (f) shows a photograph of a fabricated NAIS chip 224 with an approximately or exactly 300 μm x 300 μm gas inlet aperture 206 and 50 μm x 50 μm double-aperture 211.

[0009] From an experimental standpoint, the reduced brightness is defined as [34,35]

[0010] where I a is the ion beam current, A s is the virtual source area, Ω is the solid angle which defines the beam divergence, V is the beam acceleration potential, A a is the angular aperture area, and L is the distance between virtual source and the angular aperture.

[0011] To set up the reduced brightness measurement, a JEOL JSM-5600 tungsten scanning electron microscopy (SEM) is used as an electron injector in an example embodiment. This SEM is operated at approximately or exactly 1 keV with an electron beam current of a few tens of nA. The brightness measurement setup 300 is positioned inside the SEM chamber (not shown), as shown in Fig. 3. Focused electrons 302 are injected into the NAIS chip 224 through the double-aperture 211 (compare Fig. 2) to ionize the gas 304. A regulator valve (not shown) is used in an example embodiment to control inlet gas pressure between approximately or exactly 1 mbar and 1 bar. The reduced brightness measurement is performed with argon ions in an example embodiment (Ar + approximately or exactly 95%, the rest are Ar n + , n = 2 to 4) [36] to examine the performance of the NAIS chip 224 according to a non-limiting example embodiment. The electric field, across the chip bias electrode 306 and the ground electrode 308, inside the ionization chamber 200 (compare Fig. 2) is varied by tuning the bias across the NAIS chip 224 from approximately or exactly 0 to 100 V in an example embodiment. The extractor 310 is set at a negative potential (< -1 kV) to accelerate the ion beam 312 and also to advantageously prevent the injected electron beam 302 from travelling further downstream into the setup 300 in an example embodiment. For the purpose of measuring the brightness of the ion source, i.e. the performance of the source, an angular aperture 314 (approximately or exactly 95 μm x 112 μm, 10 mm downstream from the NAIS chip 224 in an example embodiment) to define the solid angle is kept at the same potential as the extractor 310 in an example embodiment. The angular aperture 314 is fabricated by a similar process as described above with reference to Fig. 2 for the NAIS chip's 224 double aperture 211 (compare Fig. 2) in an example embodiment. This angular aperture 314 (maintained at equipotential with the extractor 310 in an example embodiment) is mounted on a piezo-XY linear stage (SmarAct® SLC-1720-S-HV) in an example embodiment and scanned through the ion beam to find the peak axial beam current as measured in a Faraday cup 316. Downstream of the angular aperture 314, a suppressor electrode 318 (at equipotential with the extractor 310 in an example embodiment) is used to maintain a preferably field-free region for ions. The Faraday cup 316 is biased at approximately or exactly -90 V in an example embodiment to advantageously aid ion beam-landing.

[0012] It was previously reported that increasing the inlet gas pressure in NAIS results in generating a higher ion beam current [33]. Accordingly, in the current experiment the inlet Ar gas pressure is set to be approximately or exactly 860 mbar in an example embodiment. The Knudsen number K n , which is defined as the ratio of the molecular mean free path length to the ionization chamber height, under those conditions is around 0.2. Further increase in the inlet gas pressure may lead to undesired ion-gas collisions. Chip bias is used to repel ions out of NAIS chip 224 in an example embodiment. This chip bias is varied from approximately or exactly 0 to 100 V to obtain maximum output current from the NAIS chip 224. In the NAIS's chip 224 mechanical design in an example embodiment, a misalignment of about 100 μm is inherited between the double-aperture 211 (compare Fig. 2) and the extractor 310, resulting in off-axis aberration. This can cause a negative influence on the reduced brightness measurement, especially for high extraction potential [37]. Therefore, the extractor 310 potential is deemed to be optimal at -1.2 kV in an example embodiment. With the following parameters: inlet gas pressure of approximately or exactly 860 mbar, chip bias of approximately or exactly 23 V, and an extractor 310 potential of approximately or exactly -1.2 kV, an axial peak current of about 230 pA is observed in an example embodiment. It is noted that the chip bias can advantageously be reduced in preferred embodiments of the present invention as will be described below with reference to Figs. 4 to 10. On substituting these values in Eq. (1), a reduced brightness for Ar + is found to be about 9.1 x 10 3 A/(m 2 srV). Here, the value of virtual source size is considered to be the same as the double-aperture size (approximately or exactly 500 nm). Since the virtual source size of a planar emitter is expected to be smaller than the real source size [32], the actual reduced brightness in an example embodiment can be expected to be much higher.

[0013] The injected electron beam 302, used to ionize Ar gas molecules in an example embodiment, has a relatively larger spot size with respect to the double-aperture 211 (compare Fig. 2). This can induce clogging on the surface of the NAIS chip 224 at the entrance of double- aperture 211 (compare Fig. 2), due to electron beam-induced deposition (EBID). To preferably prevent this clogging effect, a fine focused electron beam is used in preferred example embodiments. [0014] As recognized by the inventors, the ionization chamber 200 (compare Fig. 2) is critical to achieve a high brightness ion beam. To improve the performance of the reported prototype NAIS [32, 33], a modified NAIS chip 224 is fabricated and tested in example embodiments described herein. The modified NAIS chip 224 has an integral ionization chamber 200 inside silicon nitride membranes 220. The double-aperture 211 (compare Fig. 2) of the NAIS chip 224 is reduced to approximately or exactly 500 nm in diameter in an example embodiment. The fabrication process according to an example embodiment is advantageously designed for batch production using MEMS fabrication techniques. With the modified NAIS chip 224, a reduced brightness of about 9.1 x 10 3 A/(m 2 srV) of Ar + has been achieved in an example embodiment, which is one (1) order higher than the reported prototype NAIS [32,33] and three (3) orders higher than the RF source in the existing PBW system [7]. Better mechanical alignment of the NAIS chip 224 and extractor 310, higher electron beam 302 current density, determination of more appropriate virtual source size, and fine tuning of other parameters can be reasonably expected to result in further enhanced reduced brightness according to further example embodiments of the present invention.

[0015] According to Equation (1), injected electrons of IkeV can produce a proton beam with a reduced brightness of about 10 6 A/(m 2 srV) with about 500 pA current through an 60 nm virtual source size according to a non-limiting example embodiment.

[0016] Embodiments of the present invention are preferably capable of creating an approximately or exactly 50-200 nm high ionization chamber with small (< lOnm) deformation for NAIS with high brightness and low energy spread. In preferred embodiments, supporting beams/grids adhered to the wall of the ionization chamber can facilitate this advantage. In the following, two such preferred embodiments will be described by way of example only. In one of these embodiments, the NAIS chip comprises two bonded chips, while in the other embodiment the NAIS chip has a ~ 10-100 nm thick graphite layer to seal the ionization chamber.

[0017] Fig. 4 shows the chip 400 which can be integrated as NAIS according to one embodiment. The gas inlet window 402 and electron injected/ ion extracted window 404 are formed in a <100> silicon wafer 406 with an approximately or exactly 50-500 nm nanometer double side coated silicon nitride 408a, b. The bottom side silicon nitride 408b serves as the ionization chamber wall to constrain the gas and holds the pressure difference between gas (~ 1 bar) and vacuum. The top side silicon nitride 408a acts as a mask for desired patterning followed by DRIE. The pyramid shape of the windows 402, 404 in the silicon 406 can be formed in the potassium hydroxide (KOH) solution and accurately controlling the etching depth for approximately or exactly 15 μm thick residual silicon. The residual silicon is milled by focused ion beam (FIB), or FIB followed by KOH etching, or lithographic pattering followed by DRIE etching, to create supporting beams/grids 410. Because the silicon nitride 408b is very thin, it is desirably that the milling process stops before reaching the silicon nitride 408b membrane, with thin μm protective silicon layer left. This protective silicon layer 406 can be removed by DRIE with a suitable recipe or by KOH etching, as understood in the art. As shown in Fig. 5, the supporting beams/grids 410 are orthogonally distributed with approximately or exactly 10 μm spacing arrangement in a non-limiting example embodiment.

[0018] Next, the fabrication process is carried out at the back side of the wafer 406 to create the ionization chamber 500. The ionization chamber 500 is created by RIE for approximately or exactly 50 - 200 nm depth in the example embodiment, followed by approximately or exactly 10 nm gold 600 deposition to create the electrodes, as shown in Fig. 6. An approximately or exactly 10 nm chromium serves as an adhesion layer between gold and silicon nitride 408b. Electrodes are chosen to have no-contact to each other when bonding two chips together, as will be described below.

[0019] Once the chips 400 are fabricated, one embodiment of a NAIS chip 700 is fabricated by bonding two chips 400a, b as depicted in Fig. 7. These two chips 400a, b can be precisely aligned according to the supporting beams/grids 410. The electron injection apertures 800 and ion exit apertures 802 are milled by FIB resulting in well aligned sub- micron size apertures 800, 802, as shown in Fig. 8. Fig. 9 illustrates that the gas is fed through window 900 and maintains a reasonable pressure inside the ionization chamber 500 due to the small apertures 800, 802 (compare Fig. 8) of the electron injection window and ion exit window, respectively.

[0020] Another embodiment of NAIS chip 1001 is illustrated in Fig. 10 a), comprising of one chip 400c and graphite 1000 with ion exit apertures 1002. The ionization chamber is formed inside chip 400c with a port made of silicon nitride membrane. The rigidity of graphite 1000 film of approximately or exactly 10 - 100 nm thickness is preferably strong enough to hold about or exactly 1 bar pressure with small deformation. To reduce the deformation of the graphite 1000 film in the electron inlet/ion outlet region, silicon nitride pillars 1004 are formed on the back side of the wafer 406 as one integral layer etched down into the Si 3 N 4 408b as shown in Fig 10 d) or patterned in HSQ. Advantageously, the graphite 1000 film also serves as an electrode in the example embodiment. The graphite 1000 film is transferred from a substrate (not shown) that has pre-deposited graphite on it, according to an example embodiment. The electron-injection window apertures 800 and the ion exit apertures 1002 of the double-aperture are milled by FIB in an example embodiment.

[0021] A different embodiment of the NAIS chip 1005, which uses a different configuration to create the electrons, which in turn are used for ionizing the gas in the ionization chamber 500, is shown in Fig 10 b), comprising one chip 400c, graphite 1000 film and an array of efficient secondary electron emitters 1003 disposed within the Si 3 N 4 408b. Thus, a sealed continuous layer (i.e. Si 3 N 4 408b) is present at the electron entry opposite the ion exit apertures 1002 in this embodiment. A beam of primary electrons directed towards Si 3 N 4 408b will induce an avalanche of secondary electrons, from the array of secondary electron emitters 1003. In such embodiments, the current density of the electrons that are suitable to ionize the gas can advantageously be increased, thereby increasing the output ion current through the ion exit aperture 1002. In a different embodiment, the entrance of primary electrons and the exit of the ion beam are swapped, by placing the array of secondary electron emitters 1003 within graphite 1000 film and forming the ion exit apertures 1002 in the Si 3 N 4 408b layer, as shown in Fig 10 c).

[0022] Figure 15 a) shows a schematic drawing of another embodiment of a NAIS chip 1500 similar to the embodiment described above with reference to Figure 10 a). Figure 15 b) shows a schematic drawing of another embodiment of a NAIS chip 1502, being a modification of the embodiment of Figure 10 a), namely with the electron entry and ion exit swapped. Figure 15 c) shows a schematic drawing of another embodiment of a NAIS chip 1504 similar to the embodiment described above with reference to Figure 10 c). Figure 15 d) shows a schematic drawing of another embodiment of a NAIS chip 1506 similar the embodiment described above with reference to Figure 10 b).

[0023] Application to provide a c-PBW system with NAIS, according to an example embodiment

[0024] Layout of a c-PBW system according to an example embodiment

[0025] In accordance with an example embodiment, a c-PBW system that employs a high brightness NAIS chip according to an example embodiment for sub- 10 nm lithography can be provided. A NAIS chip "b" for a proton beam with 10 6 A/(m 2 srV) reduced brightness, 500 pA current, and 60 nm virtual source size is adopted according to a non-limiting example embodiment to evaluate the c-PBW system performance. The layout of the c-PBW system 1100 according to an example embodiment is shown in Fig. 11. Protons are generated by electron-gas collisions (electrons provided by electron injector "a") in the NAIS chip "b", and extracted using an extractor "c" with a tunable extraction voltage in the range of approximately or exactly -5 kV to -10 kV. Subsequently, a condenser lens "d" is used to shape the beam. The converged beam is then passed through an acceleration column or tube "e", where it gains a final energy of approximately or exactly 200 keV. A collimator aperture 1102 is used to prevent further transmission of high angular scattered ions, while mostly allowing less divergent ions to enter into the focusing lenses "g". An electrostatic scanner "f" is used, before the focusing lenses "g", to scan the beam after it is collimated. Three or four electromagnetic quadrupole lenses are employed in example embodiments to focus the beam into the end-station with sub- 10 nm resolution. Considering a 2 μm inaccuracy in sample positioning (at image plane "h"), with a preset upper limit of the beam half angle a to 0.25 mrad, can advantageously ensure that the beam broadening is not more than lnm. The reduced brightness is given as

[0026] where Ip (>0.2 pA) is the proton beam current, Ao is the beam area, dp (<10 nm) is the beam diameter at the focal plane, Ω is the solid angle, α (<0.25 mrad) is the beam half- angle divergence, and V (200 kV) is the beam terminal voltage at the image plane. It is noted that with off the shelf position sensors inaccuracy in positioning the sample within the image plane can be adjusted to considering a 0.1 micron inaccuracy. This will lead to higher Ip available for writing in preferred embodiments. With the limitation explained above, an ion source with a reduced brightness of more than 5 x 10 4 A/(m 2 srV) can achieve fast writing speed using the c-PBW system according to an example embodiment, with the NAIS chip "b" according to example embodiments as the ion source.

[0027] Lens configuration and probe beam evaluation of the c-PBW system according to an example embodiment

[0028] In addition to providing for a high source reduced brightness, optimizing the focusing lens configuration has been recognized by the inventors to play a critical role in determining the capability to reach sub- 10 nm proton beam resolution. Particle Beam Optics Laboratory 3.0 (PBO Lab) [38] is used to study the focusing capability of different lens configurations. The two commonly used lens configurations: the low excitation Russian quadruplet [39] and the spaced Oxford triplet [40] configurations 1200, 1202 are shown in Figs. 12a) and b), respectively. The Russian quadruplet configuration 1200 has the same demagnification in both X and Y, while the spaced Oxford triplet configuration 1202 has different demagnifications in X and Y. Four magnetic lenses 1 to 4 make up the Russian quadruplet configuration 1200, where the separation between all lenses is fixed at 25 mm with the exception of lens 2 and 3 ( L 2,3 ). L 2,3 is varied to evaluate the focusing performance of this configuration 1200. For the spaced Oxford triplet configuration 1202, three magnetic lenses 1 to 3 were used with a fixed separation of 25 mm between lens 2 and 3. The distance between lens 1 and 2 ( L 1,2 ) is varied to investigate the focusing performance. In the c-PBW system according to an example embodiment, protons are extracted and accelerated to approximately or exactly 200 keV to reach the object plane. In the simulations, the object beam size (d v ) is considered to be the same as the virtual source size for simplicity. The distance between object plane and collimator aperture is set to be 2 m. The working distance L 2 is fixed at 30 mm for both lens configurations 1200, 1202. A 200 keV proton beam is considered to have 2 eV beam energy spread, caused by the combined effect of the NAIS source energy spread (<1 eV) and <10 ppm acceleration power instability (<2 V for 200 kV). The instability of the magnetic field from the focus lens is 1 ppm.

[0029] A systematic approximation by root-power-sum algorithm for full width 90% (FW90, the width including 90% of proton beam current) proton beam diameter d p at image plane is described as [41],

[0030] where di is demagnified virtual source size, and is given by

[0031] (where d v is the proton virtual source diameter, Dem is the demagnification of the focusing lens), d A , d s , and d c are the contributions from diffraction aberration, spherical aberration, and chromatic aberration, respectively. The contribution from the diffraction aberration is negligible, because the de Broglie wavelength of 200 keV proton is small (~6 x 10 -14 m). The contribution from spherical and chromatic aberrations are,

[0032] α e is the proton beam half angle before entering the focusing lens, C s and C c are the spherical and chromatic aberrations, and δU is the beam energy spread.

[0033] PBO Lab calculates the lens demagnification (Dem), chromatic (C c ), and spherical (Cs) aberrations. These parameters are expressed in two orthogonal directions (X and Y) for an astigmatic lens system. The characteristic values obtained from PBO Lab for Russian quadruplet configuration 1200 are summarized in Table 1. The coulomb effect is neglected here, and will be discussed in detail below.

[0034] The final probe beam FW90 width at the image plane is shown in Figs. 13a and b, as a function of L 2,3 and L 1,2 , respectively. The most ideal lens distances for obtaining sub- 10 nm beam spot sizes in Russian quadruplet and spaced Oxford triplet are L 2,3 = 25 mm and L 1,2 = 105 mm, respectively. With the preferred lens spacing for both configurations 1200, 1202, beam widths and divergences are examined according to different beam currents, as shown in Figs. 13c-f. From Fig. 13c, one can see that the beam spot size remains sub- 10 nm up to 15 pA. The different beam currents are obtained by changing the collimator aperture 1102 (compare Fig. 11), resulting in the change of beam half angle a. From Fig. 13d, it is clear that in order not to exceed the preset upper limit of beam half angle α (0.25 mrad), the beam current preferably does not exceed 2 pA for the Russian quadruplet lens configuration 1200.

[0035] Since the spaced Oxford triplet configuration 1202 has different demagnification in X and Y directions, there are two different preset upper limits for the beam half angle, α x and αy respectively. From Fig. 13f, one can have a beam current of 0.5 pA while maintaining α y well below 0.25 mrad. Whereas due to the high demagnification in X direction, the upper limit of α x can be increased up to 2 mrad (still maintaining a sub- 10 nm focus in X, see Fig. 13e), while yielding a beam current of 0.5 pA. Table 2 summarizes the performance of these two lens configurations for the c-PBW system according to example embodiments, compared with current PBW and EBL systems. It shows a promising high-throughput for the c-PBW system according to example embodiments in the sub- 10 nm regime that is faster than in EBL.

[0036] In lithography, the possibility of having a large scan size (~10's μm) in the image plane is generally desirable. In the PBO simulation, a scanner is located 20 mm upstream from the first lens for both lens configurations 1200, 1202. As shown in Figs. 14a) and b), the Russian quadruplet lens configuration according to an example embodiment can achieve sub- 10 nm beam size with a 400 x 400 μm 2 scan size, while the spaced Oxford triplet lens configuration according to an example embodiment can only have a 30 x 30 μm 2 scan size, which is limited by the larger off-axis aberration (all simulations were performed with 0.2 pA).

[0037] Coulomb effect of a c-PBW system according to example embodiments

[0038] An ion beam is not only affected by external fields but also influenced by the charged particles that introduce fields with neighboring ions, named as Coulomb effects. Generally, Coulomb effects consist of three different type of effects: a space charge effect, a Boersch effect, and a trajectory displacement effect [9]. Space charge effect is a deflection of a charged particle acted upon by the self -field generated by the beam. Usually, for a round beam with uniform distribution, the space charge effect can be compensated by the external lens due to the linear force in the transverse plane, and therefore neglected. Boersch effect and trajectory displacement effect are stochastic effects which are introduced by pair-wise interactions between charged particles. Trajectory displacement creates more spread towards the trans- verse energy of the beam, which in turn degrades the beam brightness. Meanwhile, the longitudinal beam energy gets broadened towards the thermodynamic equilibrium with the change of transverse energy, and this causes the total beam energy spread known as Boersch effect. These stochastic effects cannot be compensated by adjusting external focus fields. In most scenarios, at the high current density region, which is normally located at the source part [11], stochastic Coulomb effects can be important. To surmount the Coulomb effect in the source region, a stronger electric field is applied in order to reduce the interaction time. This will generally lead to a larger energy spread. However, in the NAIS chip setup according to example embodiments, a strong field is generated across a sub- micron spacer using a small bias potential difference (~1 V). This NAIS chip geometry advantageously limits the energy spread to less than 1 eV. Considering a typical ionization chamber designed for a Schottky electron injector, the electric field inside the chamber is approximately or exactly 107 V/m. This electric field preferably ensures that all the ions generated in the ionization chamber are guided towards the extraction plane. In this scenario the time taken by H + and H 2 + to escape from the source is less than 100 ps. With such a flight time, there is only one ion expected to reside in the ionization chamber at a given point of time (this assumption is valid for ion currents up to ~2 nA [11]), and therefore the Coulomb interactions can advantageously be neglected inside the ion source according to example embodiments.

[0039] While the design considerations of a c-PBW systems according to the above described example embodiments are a conservative estimate, they already suggest a competitive writing speed coupled with minimal proximity effect.

[0040] In one embodiment, an ionization chamber chip for a nano-aperture ion source is provided, the ionization chamber chip comprising a first substrate comprising a first depression formed in a back surface thereof; a backing element attached at the back surface of the first substrate such that a chamber is formed comprising at least the first depression; a gas inlet formed in the first substrate in fluid communication with the chamber; and a first aperture structure formed in the first substrate in fluid communication with the chamber.

[0041] The ionization chamber can further comprise an electrode layer formed on the back surface of the first substrate, the electrode layer extending into the first depression.

[0042] The first aperture structure may comprise an array of beams/grids formed in a bulk material of the first substrate and an aligned array of aperture holes formed in a material layer forming the back surface of the first substrate.

[0043] The backing element may comprise a sheet.

[0044] The ionization chamber may comprise pillars formed on the back surface of the first substrate configured to reduce deformation of the sheet in the region adjacent the first aperture structure. The pillars may be formed as one integral layer etched down into the back surface of the first substrate. The pillars may be formed as one integral layer patterned in a high-resolution resist.

[0045] The backing element may comprise an array of aperture holes formed therein and aligned with the aperture holes formed in the material layer.

[0046] The ionization chamber may comprise an array of secondary electron emitters disposed in the first substrate or in the backing element.

[0047] The backing element may comprise a second substrate comprising a second depression formed in a back surface thereof, wherein the first and second substrates may be attached to each other at the respective back surfaces such that the chamber comprises the adjoining first and second depressions, and wherein the second aperture structure may comprise an array of beams/grids formed in a bulk material of the second substrate and an aligned array of aperture holes formed in a material layer forming the back surface of the second substrate.

[0048] The backing element may comprise a second substrate comprising a second depression formed in a back surface thereof; wherein the first and second substrates may be attached to each other at the respective back surfaces such that a chamber is formed comprising the adjoining first and second depressions; and wherein the first and second aperture structures may be formed a double aperture structure extending through respective thicknesses of the first and second substrates in fluid communication with the chamber.

[0049] The ionization chamber may further comprise a first electrode layer formed on a front surface of the first substrate opposite to the back surface; and a second electrode layer formed on a front surface of the second substrate opposite to the back surface. The first electrode layer may extend at least partially along a wall of the gas inlet and a wall of the double aperture and wherein the second electrode layer extends at least partially along the wall of the double aperture.

[0050] The gas inlet may comprise an inlet aperture extending through the thickness of the first substrate.

[0051] The second substrate may comprise a filled depression at a corresponding lateral position to the inlet aperture, relative to the attached back surfaces.

[0052] In one embodiment, a nano-aperture ion source is provided comprising the ionization chamber chip of the preceding embodiment.

[0053] In one embodiment, a proton beam writing system is provided comprising the nano-aperture ion source of the preceding embodiment.

[0054] Figure 16 shows a flowchart 1600 illustrating a method of fabricating an ionization chamber chip for a nano-aperture ion source, according to an example embodiment. At step 1602, a first substrate comprising a first depression formed in a back surface thereof is provided. At step 1604, a backing element attached at the back surface of the first substrate such that a chamber is formed comprising at least the first depression is provided. At step 1606, a gas inlet is formed in the first substrate in fluid communication with the chamber. At step 1608, a first aperture structure is formed in the first substrate in fluid communication with the chamber.

[0055] The method may further comprise forming an electrode layer on the back surface of the first substrate, the electrode layer extending into the first depression. [0056] The first aperture structure may comprise an array of beams/grids formed in a bulk material of the first substrate and an aligned array of aperture holes formed in a material layer forming the back surface of the first substrate.

[0057] The backing element may comprise a sheet.

[0058] The method may comprise forming pillars on the back surface of the first substrate configured to reduce deformation of the sheet in the region adjacent the first aperture structure. The pillars may be formed as one integral layer etched down into the back surface of the first substrate. The pillars may be formed as one integral layer etched patterned in a high-resolution resist.

[0059] The backing element may comprise an array of aperture holes formed therein and aligned with the aperture holes formed in the material layer.

[0060] The method may comprise disposing an array of secondary electron emitters in the first substrate or in the backing element.

[0061] The backing element may comprise a second substrate comprising a second depression formed in a back surface thereof, wherein the first and second substrates may be attached to each other at the respective back surfaces such that the chamber comprises the adjoining first and second depressions, and wherein forming the second aperture structure may comprise forming an array of beams/grids in a bulk material of the second substrate and forming an aligned array of aperture holes in a material layer forming the back surface of the second substrate.

[0062] The backing element may comprise a second substrate comprising a second depression formed in a back surface thereof; wherein the first and second substrates may be attached to each other at the respective back surfaces such that a chamber is formed comprising the adjoining first and second depressions; and the method may further comprise forming a double aperture comprising the first and second aperture structures, the double aperture extending through respective thicknesses of the first and second substrates in fluid communication with the chamber.

[0063] The method may further comprise forming a first electrode layer on a front surface of the first substrate opposite to the back surface; and forming a second electrode layer on a front surface of the second substrate opposite to the back surface. The first electrode layer may extend at least partially along a wall of the gas inlet and a wall of the double aperture and the second electrode layer may extend at least partially along the wall of the double aperture.

[0064] The gas inlet may comprise an inlet aperture extending through the thickness of the first substrate.

[0065] The method may comprise forming a filled depression in the second substrate at a corresponding lateral position to the inlet aperture, relative to the attached back surfaces.

[0066] The first and second substrates may be batch processed prior to being attached to each other at the respective back surfaces. The batch processing comprises simultaneously forming respective portions of the double aperture in the first and second substrates. The batch processing may comprise simultaneously forming a portion of the gas inlet and a corresponding depression in the first and second substrates, respectively. The batch processing may comprise simultaneously forming the first and second electrode layers on the front surfaces of the first and second substrates, respectively.

[0067] The above description of illustrated embodiments of the systems and methods is not intended to be exhaustive or to limit the systems and methods to the precise forms disclosed. While specific embodiments of, and examples for, the systems components and methods are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the systems, components and methods, as those skilled in the relevant art will recognize. The teachings of the systems and methods provided herein can be applied to other processing systems and methods, not only for the systems and methods described above.

[0068] The elements and acts of the various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the systems and methods in light of the above detailed description.

[0069] In general, in the following claims, the terms used should not be construed to limit the systems and methods to the specific embodiments disclosed in the specification and the claims, but should be construed to include all processing systems that operate under the claims. Accordingly, the systems and methods are not limited by the disclosure, but instead the scope of the systems and methods is to be determined entirely by the claims.

[0070] Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise," "comprising," and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is to say, in a sense of "including, but not limited to." Words using the singular or plural number also include the plural or singular number respectively. Additionally, the words "herein," "hereunder," "above," "below," and words of similar import refer to this application as a whole and not to any particular portions of this application. When the word "or" is used in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list and any combination of the items in the list.

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