CLAIM FOR PRIORITY

[0001] This application claims the benefit of priority to U.S. Provisional App. 82/927,017, filed October 28, 2019, the entire contents of which are hereby incorporated by reference.

FIELD

[0002] The disclosure generally relates to precoding for wireless signal transmission.

BACKGROUND

[0003] The benefits of using multiple antennas at a wireless transmitter are well established. Multiple input, multiple output (MIMO) is an antenna technology for wireless communications in which multiple antennas are used at both the source (transmitter) and the destination (receiver(s)). The wireless signals at the receiver end are combined to minimize errors and optimize data speed.

[0004] Knowledge of the transmission channel can be used at the transmitter to improve performance of wireless signal transmission. Preceding is a technique that uses knowledge of the transmission channel to process data streams prior to wireless transmission, such that the data streams are mapped to transmitting antennas based on the transmission channel conditions. For example, a linear precoder may split the transmission signal into orthogonal spatial eigen-beams in which higher power is used for beams for which the channel is strong but lower or no power for beams for which the channel is weak.

[0005] Precoding uses digitai-to-analog converters (DACs). The power consumption of the DACs is a significant proportion of the total power consumption in a base station that uses precoding, such as a MlMO base station. Accordingly, it would be advantageous to reduce power demands imposed upon base stations - especially MlMO base stations - so as to simplify operations of such base stations and afford other operational benefits (faster processing via use of simplified processing demands, use of simpler, more cost effective processors, reduced heat mitigation requirements, and the like). Moreover, it would be advantageous to reduce signal distortion of a signal transmitted by a base station that uses precoding, while also reducing hardware cost and/or power demands.

BRIEF SUMMARY

[0008] According to one aspect of the present disclosure, there is provided an apparatus for transmitting wireless signals. The apparatus comprises a plurality of digitai-to-analog converters, a plurality of transmitters, and a processor in communication with the plurality of digitai-to-analog converters and with the plurality of transmitters. The processor is configured to calculate an initial iteration of a precoding vector. The processor is configured to iteratively re-calcuiate the precoding vector until a final precoding vector is generated. Iteratively re-calculating the precoding vector includes modifying a current iteration of the precoding vector based on an error vector magnitude (EVM) associated with the current iteration of the precoding vector when the current iteration of the precoding vector is not the final precoding vector. Iteratively re-calculating the precoding vector further includes adding random noise to the modified current Iteration of the precoding vector to generate a next iteration of the precoding vector. The processor is configured to input the final precoding vector into the plurality of digitai-to-analog converters to generate an analog precoding vector in response to determining that the final precoding vector is generated. The plurality of transmitters is configured to transmit the analog precoding vector.

[0007] Optionally, in any of the preceding aspects, the processor is further configured to calculate the initial iteration of the precoding vector by: determining a digital precoding vector for a desired signal vector; and adding random noise to the digital precoding vector to generate the initial iteration of the precoding vector.

[0008] Optionally, in any of the preceding aspects, the processor is further configured to multiply the current iteration of the precoding vector by a channel state information matrix to determine the EVM.

[0009] Optionally, in any of the preceding aspects, the processor is further configured to determine an error in the current iteration of the precoding vector based on the EVM associated with the current iteration of the preceding vector.

[0010] Optionally, in any of the preceding aspects, the processor is further configured to use a linear estimator to determine the error in the current iteration of the precoding vector.

[0011] Optionally, in any of the preceding aspects, the processor is further configured to apply at least one of a zero forcing matrix or a mean square error estimator matrix to the EVM to determine the error in the current iteration of the precoding vector.

[0012] Optionally, in any of the preceding aspects, the processor is further configured to apply a gain to the error in the current iteration of the precoding vector to determine the modified currenf iteration of the precoding vector.

[0013] Optionally, in any of the preceding aspects, the processor is further configured to modify the gain based on at least one of the error in the current iteration of the precoding vector or the EVM associated with the current iteration of the precoding vector.

[0014] Optionally, in any of the preceding aspects, the processor is further configured to decrease the gain with at least one of a decrease In the EVM associated with the current iteration of the precoding vector or with a decrease in the error in the current iteration of the precoding vector.

[0015] Optionally, in any of the preceding aspects, the processor is further configured to iteratively re-calculate the precoding vector for a pre-defermined number of iterations or until the EVM associated with the current iteration of the precoding vector is below a threshold.

[0018] Optionally, in any of the preceding aspects, the processor is further configured to iteratively re-calculate the precoding vector until the EVM associated with the current iteration of the precoding vector does not decrease from one iteration to the next iteration or the error in the current iteration of the precoding vector does not decrease from one iteration to the next iteration.

[0017] Optionally, in any of the preceding aspects, the plurality of digifa!-fo-ana!og converters are each one-bit digitai-to-analog converters.

[0018] Optionally, in any of the preceding aspects, the plurality of digital-to-ana!og converters are each multi-bit digitai-to-analog converters.

[0019] Optionally, in any of the preceding aspects, the processor is further configured to add random noise to the modified current iteration of the precoding vector by adding quantization noise that is independent of the modified current iteration of the precoding vector.

[0020] Optionally, in any of the preceding aspects, the apparatus further comprises comprising a random number generator configured to generate a random number, wherein the processor is further configured to combine the modified current iteration of the precoding vector with a random number from the random number generator in order to add random noise to the modified current iteration of the precoding vector.

[0021] A further aspect comprises a method for transmitting wireless signals by a communication system. The method comprises calculating an initial iteration of a precoding vector by the communication system. The method comprises iteratively recalculating the precoding vector by the communication system until determining that a final preceding vector is generated. Iteratively re-calculating the precoding vector includes modifying a current iteration of the precoding vector based on an error vector magnitude (EVM) associated with the current iteration of the precoding vector when the current iteration of the precoding vector is not the final precoding vector, iteratively re-calculating a precoding vector includes adding random noise to the modified current iteration of the precoding vector to generate a next iteration of the precoding vector. The method also includes inputting the final precoding vector into a plurality of digita!- to-anaiog converters of the communication system to generate an analog precoding vector in response to determining that the final preceding vector is generated. The method also includes transmitting the analog precoding vector using a plurality of transmitters of the communication system.

[0022] A further aspect comprises a multiple-input, multiple output (MIMO) communication system. The MIMO system comprises an input configured to receive K symbols for a corresponding K user devices, a plurality of digital-to-anaiog converters, a plurality of radio frequency transmitters, and a processor in communication with the input, the plurality of digital-to-analog converters, and with the plurality of radio frequency transmitters. The processor is configured to generate an initial precoding vector for the K symbols. The processor is configured to iteratively re-calcuiate the precoding vector by repeating the following until a final precoding vector is produced: modify a current Iteration of the precoding vector based on an error between the K symbols and a resultant signal vector from the current iteration of the precoding vector if the current iteration of the precoding vector is not the final precoding vector; and add random noise to the modified current iteration of the precoding vector to generate a next iteration of the precoding vector. The processor is configured to input the final precoding vector into the plurality of digital-to-analog converters to generate an analog precoding vector. The plurality of radio frequency transmitters are configured to transmit the analog precoding vector to the K user devices.

[0023] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. The claimed subject matter is not limited to implementations that solve any or all disadvantages noted in the Background.

BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Aspects of the present disclosure are illustrated by way of example and are not limited by the accompanying figures for which like references indicate elements.

[0025] FIG. 1 illustrates a wireless network for communicating data.

[0028] FIG. 2 illustrates example details of user equipment (UE) that may implement the methods and teachings according to this disclosure,

[0027] FIG. 3 illustrates an example base station (BS) that may implement the methods and teachings according to this disclosure.

[0028] FIG. 4 depicts one embodiment of a MlMO communication system.

[0029] FIG. 5 depicts further details of one embodiment of precoding logic connected to random DACs.

[0030] FIG. 6 depicts one embodiment of a dithering unit.

[0031] FIG. 7 is a diagram of one embodiment of an increment vector generator.

[0032] FIG. 8 is a flowchart of one embodiment of a process of a first iteration of determining a precoding vector.

[0033] FIG. 9 is a flowchart of one embodiment of a process of iteratively refining a precoding vector.

[0034] FIG. 10 is a flowchart of one embodiment of a process of modifying a current iteration of a precoding vector. DETAILED DESCRIPTION

[0035] The present disclosure will now be described with reference to the figures, which in general relate to an apparatus and method for iteratively searching for a precoding vector, in some embodiments, digital dithering is used when iteratively searching for the precoding vector. Embodiments of an apparatus are able to find a precoding vector that performs well with a relatively low number of iterations. Performance may be measured by the error vector magnitude (EVM) of the signal that arrives at the user device(s). in some embodiments, only about 20 iterations are needed to achieve a target EVM. Hence, a signal with low distortion can be generated with relatively low power consumption. Moreover, the low distortion provided by embodiments of precoding allows lower resolution DACs to be used, while still achieving a target EVM. In some embodiments, the DACs that are used to convert the precoding vector to an analog vector are one-bit DACs, which saves on cost and complexity. However, multi-bit DACs could be used to, for example, provide a lower distortion signal with an increase in hardware cost.

[0036] it is understood that the present embodiments of the disclosure may be implemented in many different forms and that claims scopes should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the inventive embodiment concepts to those skilled in the art. indeed, the disclosure is intended to cover alternatives, modifications and equivalents of these embodiments, which are included within the scope and spirit of the disclosure as defined by the appended claims. Furthermore, in the following detailed description of the present embodiments of the disclosure, numerous specific details are set forth in order to provide a thorough understanding. However, it will be dear to those of ordinary skill in the art that the present embodiments of the disclosure may be practiced without such specific details.

[0037] Precoding may be used within wireless networks for communicating data, but are not limited to wireless networks. FIG. 1 illustrates a wireless network for communicating data. The communication system 100 includes, for example, user equipment 110A, 110B, and 110C, radio access networks (RANs) 120A and 120B, a core network 130, a public switched telephone network (PSTN) 140, the Internet 150, and other networks 180. Additional or alternative networks include private and public data-packet networks including corporate intranets. While certain numbers of these components or elements are shown in the figure, any number of these components or elements may be included in the system 100. Some embodiments of signal power detectors are implemented in UE 110. Some embodiments of signal power detectors are implemented in RAN 120. Signal power detectors may be used elsewhere in the communication system 100.

[0038] In one embodiment, the wireless network may be a fifth generation (5G) network including at least one 5G base station which employs orthogonal frequency- division multiplexing (OFDM) and/or non-OFDM and a transmission time interval (TTI) shorter than 1 millisecond (e.g., 100 or 200 microseconds), to communicate with the communication devices. In general, a base station may also be used to refer any of the eNB and the 5G BS (gNB). In addition, the network may further include a network server for processing information received from the communication devices via the at least one eNB or gNB.

[0039] System 100 enables multiple wireless users to transmit and receive data and other content. The system 100 may implement one or more channel access methods, such as but not limited to code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), orthogonal FDMA (OFDMA), or single-carrier FDMA (SC-FDMA).

[0040] The user equipment (UE) 110A, 110B, and 110C, which can be referred to individually as a UE 110, or collectively as the UEs 110, are configured to operate and/or communicate in the system 100. For example, a UE 110 can be configured to transmit and/or receive wireless signals or wired signals. Each UE 110 represents any suitable end user device and may include such devices (or may be referred to) as a user equipment/device, wireless transmit/receive unit (UE), mobile station, fixed or mobile subscriber unit, pager, cellular telephone, personal digital assistant (PDA), smartphone, laptop, computer, touchpad, wireless sensor, wearable devices or consumer electronics device. [0041] In the depicted embodiment, the RANs 120A, 120B include one or more base stations (BSs) 170A, 170B, respectively. The RANs 120A and 120B can be referred to individually as a RAN 120, or collectively as the RANs 120. Similarly, the base stations (BSs) 170A and 170B can be referred individually as a base station (BS) 170, or collectively as the base stations (BSs) 170. Each of the BSs 170 is configured to wirelessly interface with one or more of the UEs 110 to enable access to the core network 130, the PSTN 140, the Internet 150, and/or the other networks 160. For example, the base stations (BSs) 170 may include one or more of several well-known devices, such as a base transceiver station (BTS), a Node-B (NodeB), an evolved NodeB (eNB), a next (fifth) generation (5G) NodeB (gNB), a Home NodeB, a Home eNodeB, a site controller, an access point (AP), or a wireless router, or a server, router, switch, or other processing entity with a wired or wireless network. Thus, the base stations 170 may be referred to as an apparatus for transmitting wireless signals.

[0042] in one embodiment, the BS 170A forms part of the RAN 120A, which may include one or more other BSs 170, elements, and/or devices. Similarly, the BS 170B forms part of the RAN 120B, which may include one or more other BSs 170, elements, and/or devices. Each of the BSs 170 operates to transmit and/or receive wireless signals within a particular geographic region or area, sometimes referred to as a “cell.” in some embodiments, multiple-input multipie-output (MIMO) technology may be employed having multiple transceivers for each cell, in some embodiments, the BSs 170 performing precoding, as described herein.

[0043] The BSs 170 communicate with one or more of the UEs 110 over one or more air interfaces (not shown) using wireless communication links. The air interfaces may utilize any suitable radio access technology.

[0044] It is contemplated that the system 100 may use multiple channel access functionality, including for example schemes in which the BSs 170 and UEs 110 are configured to implement the Long Term Evolution wireless communication standard (LTE), LTE Advanced (LTE-A), and/or LTE Multimedia Broadcast Multicast Service (MBMS). In other embodiments, the base stations 170 and user equipment 110A- 110C are configured to implement UMTS, HSPA, or HSPA+ standards and protocols. Of course, other multiple access schemes and wireless protocols may be utilized. [0045] The RANs 120 are in communication with the core network 130 to provide the UEs 110 with voice, data, application, Voice over internet Protocol (VoIP), or other services. As appreciated, the RANs 120 and/or the core network 130 may be in direct or indirect communication with one or more other RANs (not shown). The core network 130 may also serve as a gateway access for other networks (such as PSTN 140, Internet 150, and other networks 160). In addition, some or all of the UEs 110 may include functionality for communicating with different wireless networks over different wireless links using different wireless technologies and/or protocols.

[0048] The RANs 120 may also include millimeter and/or microwave access points (APs). The APs may be part of the BSs 170 or may be located remote from the BSs 170. The APs may include, but are not limited to, a connection point (an mmW CP) or a BS 170 capable of mmW communication (e.g., a mmW base station). The mmW APs may transmit and receive signals in a frequency range, for example, from 24 GHz to 100 GHz, but are not required to operate throughout this range. As used herein, the term base station is used to refer to a base station and/or a wireless access point.

[0047] Although FIG. 1 illustrates one example of a communication system, various changes may be made to FIG. 1. For example, the communication system 100 could Include any number of user equipment, base stations, networks, or other components in any suitable configuration, it is also appreciated that the term user equipment may refer to any type of wireless device communicating with a radio network node in a cellular or mobile communication system. Non-limiting examples of user equipment are a target device, device-to-device (D2D) user equipment, machine type user equipment or user equipment capable of machine-to-machine (M2M) communication, laptops, PDA, iPad, Tablet, mobile terminals, smart phones, laptop embedded equipped (LEE), laptop mounted equipment (LME) and USB dongles.

[0048] FIG. 2 illustrates example details of a UE 110 that may implement the methods and teachings according to this disclosure. The UE 110 may for example be a mobile telephone, but may be other devices in further examples such as a desktop computer, laptop computer, tablet, hand-held computing device, automobile computing device and/or other computing devices. As shown in the figure, the exemplary UE 110 is shown as including at least one transmitter 202, at least one receiver 204, memory 206, at least one processor 208, and at least one input/output device 212. The processor 208 can implement various processing operations of the UE 110. For example, the processor 208 can perform signal coding, data processing, power control, input/output processing, or any other functionality enabling the UE 110 to operate in the system 100 (FIG. 1). The processor 208 may include any suitable processing or computing device configured to perform one or more operations. For example, the processor 208 may include a microprocessor, microcontroller, digital signal processor, field programmable gate array, or application specific integrated circuit. The memory 206 is non-transitory memory storage, in one embodiment.

[0049] The transmitter 202 can be configured to modulate data or other content for transmission by at least one antenna 210. The transmitter 202 can also be configured to amplify, filter and a frequency convert RF signals before such signals are provided to the antenna 210 for transmission. The transmitter 202 can include any suitable structure for generating signals for wireless transmission.

[0050] The receiver 204 can be configured to demodulate data or other content received by the at least one antenna 210. The receiver 204 can also be configured to amplify, filter and frequency convert RF signals received via the antenna 210. The receiver 204 is an RF signal receiver, in some embodiments. The receiver 204 can include any suitable structure for processing signals received wirelessly. The antenna 210 can include any suitable structure for transmitting and/or receiving wireless signals. The same antenna 210 can be used for both transmitting and receiving RF signals, or alternatively, different antennas 210 can be used for transmitting signals and receiving signals.

[0051] It is appreciated that one or multiple transmitters 202 could be used in the UE 110, one or multiple receivers 204 could be used in the UE 110, and one or multiple antennas 210 could be used in the UE 110, Although shown as separate blocks or components, at least one transmitter 202 and at least one receiver 204 could be combined into a transceiver. Accordingly, rather than showing a separate block for the transmitter 202 and a separate block for the receiver 204 in FIG. 2, a single block for a transceiver could have been shown. [0052] The UE 110 further includes one or more input/output devices 212. The input/output devices 212 facilitate interaction with a user. Each input/output device 212 includes any suitable structure for providing information to or receiving information from a user, such as a speaker, microphone, keypad, keyboard, display, or touch screen.

[0053] In addition, the UE 110 includes at least one memory 206. The memory 206 stores instructions and data used, generated, or collected by the UE 110. For example, the memory 206 could store software or firmware instructions executed by the processor(s) 208 and data used to reduce or eliminate interference in incoming signals. Each memory 206 includes any suitable volatile and/or non-volatile storage and retrieval device(s). Any suitable type of memory may be used, such as random access memory (RAM), read only memory (ROM), hard disk, optical disc, subscriber identify module (SIM) card, memory stick, secure digital (SD) memory card, and the like.

[0054] FIG. 3 illustrates an example BS 170 that may implement the methods and teachings according to this disclosure. As shown in the figure, the BS 170 includes at least one processor 308, at least one transmitter 302, at least one receiver 304, one or more antennas 310, and at least one memory 306. The processor 308 implements various processing operations of the BS 170, such as signal coding, data processing, power control, input/output processing, or any other functionality. Each processor 308 includes any suitable processing or computing device configured to perform one or more operations. Each processor 308 could, for example, include a microprocessor, microcontroller, digital signal processor, field programmable gate array, or application specific integrated circuit The memory 306 is non-transitory memory storage, in one embodiment.

[0055] in some embodiments, the processor 308 performs precoding, as described herein, in some embodiments, the processor 308 iteratively searches for a precoding vector. The base station 170 includes random digital-to-analog converters (DACs) 320. In one embodiment, each random DAC contains a dithering unit that adds random noise to a precoding vector. Each random DAC also contains a DAC that converts a final preceding vector (after it has been dithered) to an analog precoding vector. The analog preceding vector is provided to the transmitter 302.

[0058] Each transmitter 302 includes any suitable structure for generating signals for wireless transmission to one or more UEs 110 or other devices. Each receiver 304 includes any suitable structure for processing signals received wirelessly from one or more UEs 110 or other devices. Although shown as separate blocks or components, at least one transmitter 302 and at least one receiver 304 could be combined into a transceiver. Each antenna 310 includes any suitable structure for transmitting and/or receiving wireless signals. While a common antenna 310 is shown here as being coupled to both the transmitter 302 and the receiver 304, one or more antennas 310 could be coupled to the transmitter(s) 302, and one or more separate antennas 310 could be coupled to the receiver(s) 304. Each memory 306 includes any suitable volatile and/or non-volatile storage and retrieval device(s).

[0057] FIG. 4 depicts one embodiment of a MIMO communication system 400. The MIMO system 400 is one embodiment of the base station 170. The MIMO system 400 has precoding logic 402, a number of random DACs 320(1) - 320(M), a corresponding number of transmitters 302(1) to 302(M), and a corresponding number of antennas 310(1) - 310(M). The MIMO system 400 transmits radio frequency signals to a number of user devices UE 110(1) - 110(K). Thus, the MIMO system 400 may be referred to as an apparatus for transmitting wireless signals, in this example, there are M random DACs 320 and K user devices 110. In some embodiments, M is substantially larger than K. For example, M could be In the hundreds or even in the thousands, whereas K might be 10 or 20. However, neither M nor K is limited to this example.

[0058] In one embodiment, each random DAC 320 has a dithering unit that adds random noise to a precoding vector. Each random DAC 320 has a DAC that receives a final version of the preceding vector (after random noise has been added). The DAC converts the final version of the precoding vector to an analog precoding vector, which is provided to the corresponding transmitter 302. Further details of one embodiment of a random DAC 320 are shown and described with respect to FIG. 5. in one embodiment, the random DACs 320 comprise one bit DACs. One bit DACs may be used in connection with one-bit precoding. In one embodiment, the random DACs 320 comprise multi-bit DACs. Multi-bit DACs may be used in connection with multi-bit precoding.

[0059] The precoding logic 402 receives signals that are to be transmitted to the user devices 110. In one embodiment, the signals comprise symbols, such as Orthogonal Frequency Division Multiplexing (OFDM) symbols. The precoding logic 402 inputs the K user signals and generates an S element digital vector, which is referred to herein as a digital precoding vector. Each element of the digital precoding vector is input to one of the random DACs 320. In some embodiments, the random DACs 320 are used in the process of iteratively searching for a precoding vector. Once a final precoding vector is determined, the random DACs are used to generate an analog version of the final precoding vector. Collectively, the random DACs 320(1) to 320(M) output the analog final precoding vector to the transmitters 302(1) - 302(M). The precoding vector will be referred to herein as S. Each random DAC 320 outputs one element of the final precoding vector to one of the transmitters 302. Hence, random DAC 320(1) outputs si to transmitter 302(1), DAC 320(2) outputs S2 to transmitter 302(2), random DAC 320(3) outputs s3 to transmitter 302(3), ... and random DAC 320(M) outputs SM to transmitter 302(M). Note that herein, in the context of vectors, an upper case letter will be used to refer to the vector, and lower case letters will be used to refer to elements of the vector. Herein, the term "precoding vector” may be used in general to refer to either a digital version of the precoding vector or to the analog precoding vector.

[0080] In one embodiment, the precoding logic 402 is implemented on the processor 308 of the base station 170. in general, the precoding logic 402 may be implemented with one or more or a microprocessor, microcontroller, digital signal processor, field programmable gate array, and/or application specific integrated circuit. In one embodiment, the precoding logic 402 may be referred to as a control circuit, in one embodiment, the precoding logic 402 in combination with the random DACs 320 may be referred to as a control circuit. In one embodiment, the precoding logic 402 in combination a portion of the circuitry within each random DAC 320 may be referred to as a control circuit. [0061] FIG. 5 depicts further details of one embodiment of precoding logic 402 connected to random DACs 320(1) - 320(M). The precoding logic 402 is configured to control what signals are input to the random DACs 320(1) - 320(M). The initial precoder 502 is configured to input a desired signal vector (Y) and to output an initial digital signal vector to one input of the input selector 504. The desired signal vector (Y) is a vector of the signals to be transmitted to the user devices 110. There is one element in the desired signal vector (Y) for each user device 110. Thus, in the example in which there are K user devices 110, the desired signal vector (Y) has K elements, in one embodiment, each element in the desired signal vector (Y) is a symbol, such as an OFDM symbol. The digital signal vector that is output by the initial precoder 502 has M elements. The input selector 504 is controlled to select either the digital signal vector or a vector that is output by the combiner 508. Thus, either the digital signal vector or the vector from the combiner 506 is provided to the dithering units 514 in the random DACs 320(1) - 320(M). The vector that is output by the combiner 506 will be discussed below. Note that there are M dithering units 514(1) - 514(M), such that each dithering unit 514 receives one element of the precoding vector.

[0062] Each random DAC 320 has a dithering unit 514 and a DAC 518. The dithering unit 514 is configured to add random noise to its input signal. Thus, the dithering units 514(1) - 514(M) are configured to add random noise to the signal from the input selector 504. The output of each dithering unit 514 is a digital signal. The output of the dithering units 514(1) - 514(M) is referred to herein as the current iteration of the precoding vector. As will be explained more fully below, the output of the dithering units 514(1) - 514(M) is iteratively re-caiculated until a final precoding vector is determined. The final precoding vector is provided to the DACs 516(1) to 516(M), which convert the final precoding vector to an analog precoding vector. In one embodiment, each DAC 516(1) - 516(M) receives a common enable signal, which is used to enable the DACs 516 when the final precoding vector is available. The analog precoding vector is provided to the transmitters 302. Each DAC 518 performs digitai-to-analog conversion. A DAC 516 may be any circuit or component that converts a digital signal to an analog signal. In one embodiment, the DACs 516 are each a one-bit DAC. In one embodiment, the DACs 516 are each a multi-bit DAC. [0063] The channel state information (CSi) matrix 508 contains information regarding the channel properties of the communication links between the base station 170 and UEs 110, The channel information is not required to be known perfectly. Typically, the estimates of the channel properties are imperfect. The CSI matrix 508 represents the downlink and is thus a downlink matrix. The CSI matrix 508 may be referred to as a CS!T (channel state information transmitter) matrix, as the information is known at the transmitter side. In one embodiment, the CSI matrix 508 comprises an M x K matrix (wherein M is the number of transmitters 302 and K is the number of UE 110). The CSI matrix 508 may be determined in any suitable manner. The CSI matrix 508 could be an instantaneous (or short term) matrix or a statistical (or long term) matrix.

[0064] The CSI matrix 508 is used to estimate the signal that is (or would be) received at the user devices 110 based on the precoding vector (S). Note that this is an estimate the signal that is received at the user devices 110, and hence does not require an actual measurement of the signal received at the user devices 110. Moreover, the estimate may be made based on an iteration of the precoding vector that is not transmitted to the UEs 110. Hence, it will be understood that the CSI matrix 508 may be used to estimate the signal that would be received at the UEs 110 if the precoding vector were to be transmitted to the UEs 110. Hence, a phrase such as “estimate of the signal received at the UEs 110” will be understood to include the condition in which the estimate is made for an iteration of the precoding vector that is not transmitted to the UEs 110. Herein, the vector for the estimates of the signals received at the user devices 110 is referred to as Ϋ. The term "resultant signal vector” may be used herein for Ϋ. Herein, Y will be used to refer to the desired signal vector. For example, Equation 1 may be used to estimate signals that are received at the user devices 110. [0065] In Equation 1 , y\ is the estimate of the signal received at user k. Thus, yk is the desired signal arriving at user k. In Equation 1 , s _m is the output of DAC m. Equation 1 also shows the CSI matrix, which is referred to herein as H.

[0086] The error measurement 510 is configured to determine an error (EY) between the desired signal vector Y and the estimate of the signal vector Ϋ. In one embodiment, the error measurement 510 determines an error vector magnitude (EVM). In one embodiment, the EVM is measured as in Equation 2.

[0067] The error measurement 510 outputs the EVM to the increment vector generator 512. The increment vector generator 512 is configured to calculate an increment vector based on the EVM. In other words, the increment vector generator 512 is configured to calculate an increment vector based on the error between the desired signal vector Y and the estimate of the signal vector Ϋ. The increment vector is used to correct an error (Es) in the precoding vector. The increment vector could have positive or negative values. Note that the input to the increment vector generator 512 is a K element error vector, and the output is an M element increment vector. Hence, the increment vector generator 512 may be configured to translate the error EY between the desired signal vector Y and the estimate of the actual signal vector Ϋ to an error Es in the precoding vector. Further details of one embodiment of an increment vector generator 512 are shown and described with respect to FIG. 7.

[0068] The increment vector is provided to the vector combiner 506. The vector combiner 506 combines the increment vector with the current precoding vector that is presently output by the dithering 514. In one embodiment, the combiner 506 is implemented using an adder. Thus, the vector combiner 506 could add the increment vector to the current preceding vector. However, operations other than addition are possible. The vector combiner 506 provides its output to one of the inputs of the input selector 504. Thus, the input selector 504 may be used to select either the output from the combiner 506 or the output of the initial precoder 502. [0069] In one embodiment, all or a portion of the circuitry within the precoding logic 402 may be referred to as a control circuit, in one embodiment, all or a portion of the circuitry within the precoding logic 402 in combination with the dithering units 514(1) - 514(M) may be referred to as a control circuit.

[0070] FIG. 6 depicts one embodiment of a dithering unit 514. The dithering unit 514 may be used in, for example, a random DAC 320 in a base station 170 or M!MG system 400. The random dithering unit 514 includes a random number generator 602 and a signal combiner 604. In one embodiment, the dithering unit 514 adds random noise that is independent of the input signal. In one embodiment, the output of the dithering unit 514 has quantization noise as a result of the added random noise.

[0071] The random number generator 602 is configured to generate a random signal (e.g., a random number). The output of the random number generator 602 is a digital signal. In one embodiment, the random signal exhibits a uniform (e.g., Gaussian) distribution. The range of the signal may be constrained within a predetermined magnitude (e.g., -0.5 to +0.5). The random number generator 602 inputs a seed and outputs the random signal to the signal combiner 604.

[0072] The signal combiner 604 combines the input signal with signal from the random number generator 602. The input signal is a digital signal. In one embodiment the signal combiner 604 adds the input signal with signal from the random number generator 602. Thus, the signal combiner 604 may comprise an adder. The adder comprises a digital circuit that is able to add two numbers. The numbers could have any of a number of different known formats such as, but not limited to, a binary format, in one embodiment, the signal combiner 604 may comprise an adder-subtractor that may be configured to either add or substrate the output of the random number generator 602 from the input signal. The output of the signal combiner 604 is a digital signal. In one embodiment, the digital signal is a one-bit digital signal. In one embodiment, the digital signal is a multi-bit digital signal.

[0073] FIG. 7 is a diagram of one embodiment of an increment vector generator 512. The increment vector generator 512 includes a linear estimator 702 and a gain circuit 704. The linear estimator 702 is able to translate the error between the desired signal vector Y and the estimate of the signal vector Ϋ to an error in the precoding vector (S). Stated another way, the linear estimator 702 is able to translate the EVM to an error in the precoding vector (S), In some embodiments, the linear estimator 702 multiplies the EVM by a linear matrix, in one embodiment, the linear estimator 702 multiplies the EVM by a zero forcing (ZF) matrix to produce the error in the precoding vector. Equation 3 is one example of a ZF matrix, as it relates to the CTI matrix (H) 508,

ZF = H ^H · inv ( H ^H · H) (3)

[0074] The linear estimator 702 is not limited to using the zero forcing (ZF) matrix, in one embodiment, the linear estimator 702 includes a minimum mean square error (MMSE) estimator, in one embodiment, the linear estimator 702 multiplies the error vector by a linear MMSE matrix to produce the error in the precoding vector,

[0075] The gain circuit 704 multiplies the precoding vector error by a factor referred to herein as alpha, thereby resulting in the increment vector. In some embodiments, alpha is fixed throughout the process of refining the precoding vector. In some embodiments, alpha changes from one iteration to the next, in one embodiment, the gain circuit 704 is configured to change alpha based on the error in S. in one embodiment, the gain circuit 704 is configured to change alpha based on the EVM (or Error in Y). in one embodiment, the gain circuit 704 is configured to decrease alpha In response to a decrease in the error in S. in one embodiment, the gain circuit 704 is configured to decrease alpha in response to a decrease in the EVM.

[0076] FIG. 8 is a flowchart of one embodiment of a process 800 of a first iteration of determining a precoding vector. The process 800 may be performed in, but is not limited to, base station 170 o Mr lMO system 400. Both the base station 170 and MlMO system 400 are examples of communication systems. The first iteration generates what is referred to herein as the initial (or first) precoding vector, which is referred to herein by the notation So. The initial precoding vector may also be referred to herein as the initial iteration of the precoding vector.

[0077] Step 802 includes accessing signals for K user devices 110. These signals are the desired signal vector, referred to herein as Y. In one embodiment, the signal for each user includes a symbol, such as an OFDM symbol. In one embodiment, the signal for each user includes a single symbol, such as an OFDM symbol. However, the signal for a user device 110 is not limited to being a single symbol.

[0078] Step 804 includes precoding the user signals to generate the digital input signals for the dithering units 514(1) - 514(M). In one embodiment, the desired user signal vector (Y) is multiplied by the zero forcing matrix to generate the digital input signals for the dithering units 514. With reference to FIG. 5, in one embodiment, the initial precoder 502 inputs the desired signal vector (Y) and provides a digital signal vector to one input of the input selector 504. The precoding logic 402 selects this input, such that the digital signal vector is provided to the dithering units 514(1) - 514(M) in the random DACs 320(1) - 320(M). The digital signal vector has M elements. Hence, one element of the digital signal vector is provided to each dithering units 514(1) — 514(M).

[0079] Step 806 includes adding random noise to the digital signal vector to generate a randomized digital signal vector. The dithering unit 514 in FIG. 6 will be referred to describe one embodiment of step 806. The input signal in FIG. 6 is one element of the digital signal vector. The random number generator 602 is used to add a random signal (e.g., a random number) to the element of the digital signal vector. In one embodiment, the random number is between -0.5 to +0.5. Step 806 is performed in the dithering unit 514 in each of the random DACs 320(1) to 320(M) in order to add random noise to the digital signal vector.

[0080] Equation 4 shows an expression for the initial precoding vector (So),

S ₀ = Random (ZF x Y) (4)

[0081] Equation 4 summarizes that the digital signal vector is input to the dithering units 514(1) - 514(M) to generate the initial precoding vector So, The expression (ZF x Y) summarizes one embodiment of step 804 in which the desired user vector (Y) is multiplied by the ZF matrix. Recall that Equation 3 defines the zero forcing matrix. The term “Random” that appears in Equation 4 corresponds to randomizing performed by the dithering units 514. [0082] FIG. 9 is a flowchart of one embodiment of a process 900 of iteratively recalculating a precoding vector, and wirelessly transmitting a final precoding vector. The process 900 may be performed in, but is not limited to, base station 170 or MIMO system 400. Process 900 is performed after an initial precoding vector So is generated. In one embodiment, process 800 is performed prior to process 900 to generate the initial precoding vector. However, a different process could be used to generate the initial precoding vector. Steps 902 - 904 describe one iteration of process 900. The process 900 repeats steps 902 - 904 until a final precoding vector is generated. Details of determining when to stop iterating are described below in connection with step 906.

[0083] Step 902 includes modifying a current iteration of the precoding vector Si based on an EVM. Note that the EVM is not required to be measured at the user equipment 110. in some embodiments, the EVM is estimated at the transmitting device (e.g., base station 170). In other words, the current iteration of the precoding vector Si is modified based on an error between the desired signal vector Y and an estimate of the signal vector Ϋ for the current iteration of the precoding vector. Note that the term “based on” includes both based directly on and based indirectly on. In one embodiment, the current iteration of the precoding vector Si is modified based on an error in the current iteration of the precoding vector Si. Equation 5 describes one formulation for the modification. S _iimod = S, + a - ZF x (Y - H · S _i ) (5)

[0084] In Equation 5, S _iimod is the vector that will be input to the random DACs 320(1) - 320(M) the next iteration. Alpha (a) is gain factor, which may be used to control the speed at which the process converges to a solution. Alpha may be made larger to increase the speed at which the process converges to a solution and smaller to decrease the speed at which the process converges to a solution (e.g., the final precoding vector). In one embodiment, alpha is larger for earlier iterations to increase the speed at which the process converges to a solution, and smaller for later iterations to avoid over-shooting the solution and to increase the precision of the solution, in some embodiments, alpha depends on the magnitude of the EVM associated with the current iteration of the precoding vector. In some embodiments, alpha depends on the magnitude of the error in the current iteration of the precoding vector. For example, a larger alpha may be used for a larger error in early iterations, with alpha decreasing as the error decreases from one iteration to the next.

[0085] Step 904 includes adding random noise to the modified a current iteration of the precoding vector to generate the next iteration of the precoding vector. The dithering unit 514 in FIG. 6 will be referred to in order to describe one embodiment of step 904. The input signal in FIG. 6 is one element of the modified current iteration S _iimod of the preceding vector. The random number generator 802 is used to add a random signal (e.g., a random number) to the element of S _iimod ·. In one embodiment, the random number is between -0.5 to +0.5, Step 904 is performed at the dithering unit 514 in each of the random DACs 320(1) to 320(M) in order to add random noise to the modified a current iteration S; _imod of the precoding vector.

[0086] Step 904 generates the next iteration of the precoding vector Si _+i . Equation 8 shows an expression for the next iteration of the precoding vector.

S _i+1 = Random (S _i + α · ZF x (Y - H . S _i ) (6)

[0087] The process 900 continues to iterate through steps 902 - 904 until a final precoding vector is generated. Note that what is described in Equation 6 as the next iteration of the precoding vector becomes the current iteration of the precoding vector in step 902.

[0088] Step 906 includes a determination of whether the final preceding vector has been generated. There are numerous techniques that can be used to determine when the final precoding vector has been generated. In one embodiment, steps 902 - 904 are performed for a pre-determined number of iterations. In one embodiment, steps 902 - 904 are performed until the error is less than a threshold. This could be determined based on the EVM. This could be determined based on the error in the preceding vector, in one embodiment, steps 902 - 904 are performed until the error does not decrease from one iteration to the next. As an alternative, steps 902 - 904 are performed until the error does not decrease for two (or some other number of) successive iterations.

[0089] After the final precoding vector is generated, the final precoding vector is input to the DACs 516 in each of the random DACs 320(1) to 320(M), in step 908. The DACs 320(1) to 32G(M) output an analog precoding vector.

[0090] Step 910 includes transmitting the analog precoding vector (also referred to as the final precoding vector) using the transmitters 302(1) - 302(M). In some embodiment, the transmitters 302 are radio frequency transmitters. The final precoding vector has M elements. One element of the final precoding vector is transmitted by each transmitter 302(1) - 302(M). Note that the final precoding vector is, or is at least based on, the output of the random DACs 320(1) to 320(M). There could be some further processing of the final precoding vector prior to transmission.

[0091] FIG. 10 is a flowchart of one embodiment of a process 1000 of modifying a current iteration of a precoding vector. Process 1000 describes further details of one embodiment of step 902 in FIG. 9.

[0092] Step 1002 includes multiplying the current iteration of the precoding vector Si by a CSI Matrix (H) 508 to determine an estimate of the signal vector Ϋ. Equation 7 describes one example of this operation.

[0093] Step 1004 includes measuring an error (EY) between the desired signal vector Y and the estimate of the signal vector Ϋ. Equation 8 describes one example of this operation. In one embodiment, step 1004 is performed by error measurement 510. The vector EY may also be referred to as the EVM.

[0094] Step 1006 includes determining an error (Es) in the precoding vector based on the error between the desired signal vector Y and the estimate of the actual signal vector Ϋ. Equation 9 describes one example of this operation. In one embodiment, step 1004 is performed by error measurement 510. Note that using the ZF matrix is one example, but other techniques could be used. In one another embodiment, the error vector (By) is multiplied by a linear MMSE matrix to produce the error (Es) in the precoding vector, in one embodiment, step 1006 is performed by linear estimator 702.

Es = ZF x EY (9)

[0095] Step 1008 includes applying a gain (a) to the error in the precoding vector to produce an increment vector Sine. Equation 10 describes one example of this operation. In one embodiment, step 1008 is performed by gain circuit 704.

S _inc = α · Es (10)

[0098] Step 1010 includes adding the increment vector to the current iteration of the precoding vector to produce the DAC input signal (S _imod ) for the next iteration. Equation 11 describes one example of this operation. In one embodiment, step 1010 is performed by vector combiner 506. S _iimod = + S _iinc (11 )

[0097] Thus, process 1000 produces the input to the dithering units 514(1) - 514(M) for the next iteration. The dithering units 514(1) - 514(M) may be used as described in step 904 of process 900 to generate the next iteration of the precoding vector.

[0098] The technology described herein can be implemented using hardware, software, or a combination of both hardware and software. The software used is stored on one or more of the processor readable storage devices described above to program one or more of the processors to perform the functions described herein. The processor readable storage devices can include computer readable media such as volatile and non-volatile media, removable and non-removable media. By way of example, and not limitation, computer readable media may comprise computer readable storage media and communication media. Computer readable storage media may be implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Examples of computer readable storage media include RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. A computer readable medium or media does (do) not include propagated, modulated or transitory signals.

[0099] Communication media typically embodies computer readable instructions, data structures, program modules or other data in a propagated, modulated or transitory data signal such as a carrier wave or other transport mechanism and includes any information delivery media. The term “modulated data signal” means a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. By way of example, and not limitation, communication media includes wired media such as a wired network or direct-wired connection, and wireless media such as RF and other wireless media. Combinations of any of the above are also included within the scope of computer readable media.

[00100] in alternative embodiments, some or ail of the software can be replaced by dedicated hardware logic components. For example, and without limitation, illustrative types of hardware logic components that can be used include Field-programmable Gate Arrays (FPGAs), Application-specific Integrated Circuits (ASICs), Application- specific Standard Products (ASSPs), System-on-a-chip systems (SGCs), Complex Programmable Logic Devices (CPLDs), special purpose computers, etc. In one embodiment, software (stored on a storage device) implementing one or more embodiments is used to program one or more processors. The one or more processors can be in communication with one or more computer readable media/ storage devices, peripherals and/or communication interfaces.

[00101] It is understood that the present subject matter may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this subject matter will be thorough and complete and will fully convey the disclosure to those skilled in the art. Indeed, the subject matter is intended to cover alternatives, modifications and equivalents of these embodiments, which are included within the scope and spirit of the subject matter as defined by the appended claims. Furthermore, in the following detailed description of the present subject matter, numerous specific details are set forth in order to provide a thorough understanding of the present subject matter. However, it will be dear to those of ordinary skill in the art that the present subject matter may be practiced without such specific details.

[00102] Aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatuses (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program Instructions. These computer program instructions may be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable instruction execution apparatus, create a mechanism for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

[00103] The description of the present disclosure has been presented for purposes of Illustration and description, but is not intended to be exhaustive or limited to the disclosure in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The aspects of the disclosure herein were chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill In the art to understand the disclosure with various modifications as are suited to the particular use contemplated.

[00104] For purposes of this document, each process associated with the disclosed technology may be performed continuously and by one or more computing devices. Each step in a process may be performed by the same or different computing devices as those used in other steps, and each step need not necessarily be performed by a single computing device. [00105] Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.