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Title:
JOINT TIME/FREQUENCY PROCESSING FOR WIRELESS RECEIVERS
Document Type and Number:
WIPO Patent Application WO/2011/004353
Kind Code:
A2
Abstract:
Channel estimation and/or equalization processing is performed m a wireless receiver in two stages. The first stage involves pre-filtering in the frequency domain to compact a grid-based representation of the net channel. The second stage involves implementing reduced-complexity time domain channel estimation and or equalization. According to one embodiment, a received signal transmitted over a net channel is processed by pre-filtering the received signal in the frequency domain The frequency domain pre-filtering compacts an N-tap effective grid-based representation of the net channel into a K-tap compacted grid-based representation of the net channel where K < N. The pre-filtered received signal is equalized in the time domain based on the K-tap compacted grid-based representation of the net channel generated by prc-fϊhering the received signal in the frequency domain.

Inventors:
CAIRNS, Douglas A. (3905 Springstop Lane, Durham, North Carolina, 27705, US)
WALLÉN, Anders (Tegnergatan 24, Ystad, S-271 31, SE)
REIAL, Andres (Barometergatan 44, Malmö, SE-211 17, SE)
Application Number:
IB2010/053163
Publication Date:
January 13, 2011
Filing Date:
July 09, 2010
Export Citation:
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Assignee:
TELEFONAKTIEBOLAGET L M ERICSSON (PUBL) (S- Stockholm, 164 83, SE)
CAIRNS, Douglas A. (3905 Springstop Lane, Durham, North Carolina, 27705, US)
WALLÉN, Anders (Tegnergatan 24, Ystad, S-271 31, SE)
REIAL, Andres (Barometergatan 44, Malmö, SE-211 17, SE)
International Classes:
H04L25/03
Attorney, Agent or Firm:
CAMERON, Michael G. et al. (Ericsson Inc, 6300 Legacy MS EVR 1-C-1, Plano Texas, 75024, US)
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Claims:
CLAIMS

1. A method of processing a received signal transmitted over a net channel, comprising:

pre-fiUering the received signal in the frequency domain to compact an N-tap effective grid-based representation of the net channel into a K-tap compacted grid- based representation of the mt channel where K < N; and

equalizing the pre-filtered received signal in the time domain based on the K-tap compacted grid-based representation of the net. channel generated by pre-fiUering the received signal in the frequency domain.

2. The method of claim 1 , comprising centering the N-tap effective grid-based representation of the net channel about an approximate center of gravity determined tor the net channel. 3. The method of claim 1, comprising centering the N-tap effective grid-based representation of the net channel about a strongest path delay determined for the net channel.

4. The method of claim 1, comprising spacing the N taps of the effective grid- based representation of the net channel at intervals of approximately Tc/2 where Tc corresponds to a chip interval of the received signal.

5. The method of claim 1 , comprising spacing the N taps of the effective grid- based representation of the net channel at intervals of approximately 3Tc/4 where Tc corresponds to a chip interval of the received signal.

6. The method of claim 1, comprising calculating pre-fitter coefficients based on the N-tap effective grid-based frequency domain representation of the net channel. 7. The method of claim 6, comprising transforming the pre-fϊlter coefficients to the frequency domain.

8. The method of claim 7, comprising multiplying the transformed pre-fHter coefficients and a frequency domain representation of the received signal.

9. The method of claim 1 , comprising equalizing the pre-filtered received signal in the time domain using a grid of path delays centered about a strongest path delay or an approximate center of gravity determined for the K-tap compacted grid-based representation of the net channel

10. The method of claim I, comprising estimating a medium channel response associated with the net channel based on the K-tap compacted grid-based representation of the net channel

1 1. A wireless receiver, comprising:

a first processing module operable to generate an N-tap effective grid-based representation of a net channel over which a received signal is transmitted and pre-fHter the received signal in the frequency domain to compact the N-tap effective grid-based representation of the net channel into a K-tap compacted grid-based representation of the net channel where K < N; and

a second processing module operable to equalize the pre-filtered received signal in the time domain based on the K-tap compacted grid-based representation of the net channel generated by the first processing module.

12. The wireless receiver of claim 11, wherein the first processing module comprises a path searcher operable to determine an approximate center of gravity of the net channel and a grid formulation component operable to center the N-tap effective grid-based representation of the net channel about the approximate center of gravity.

13. The wireless receiver of claim 1 1, wherein the first processing module comprises a path searcher operable to determine a strongest path delay for the net channel and a grid formulation component operable to center the N-tap effective grid- based representation of the net channel about the strongest path delay.

14. The wireless receiver of claim 1 1., wherein ώe first processing module is operable to space the N taps of the effective grid-based representation of the net channel at intervals of approximately Tc/2 where Tc corresponds to a chip interval of the received signal.

15. The wireless receiver of claim 1 1, wherein the first processing module is operable to space the N taps of the effective grid-based representation of the net channel at intervals of approximately 3Tc/4 where Tc corresponds to a chip interval of the received signal.

16. The wireless receiver of claim 11, wherein the first processing module comprises a coefficient calculator operable to calculate pre-filter coefficients based on the N-tap effective grid-based frequency domain representation of the net channel. 17. The wireless receiver of claim 16, wherein the first processing module comprises an FFT engine operable to transform the pre-filter coefficients to the frequency domain.

18. The wireless receiver of claim 17, wherein the FFT engine is operable to pre- filter the received signal in die frequency domain by multiplying the transformed pre- filter coefficients and a frequency domain representation of the received signal.

19. The wireless receiver of claim 11 , wherein the second processing module is operable to equalize the pre-filtered received signal in the time domain using a grid of path delays centered about a strongest path delay or an approximate center of gravity determined for the K-tap compacted grid-based representation of die net channel.

20. The wireless receiver of claim I I, wherein the second processing module is operable to estimate a medium channel response associated with the net channel based on the K-tap compacted grid-based representation of the net channel.

Description:
JOINT TIME/FREQUENCY PROCESSING FOR WIRELESS RECEIVERS

TECHNICAL FIELD

The present invention generally relates to received signal processing by wireless receivers, and more particularly relates to received signal processing in the time and frequency domains by wireless receivers.

BACKGROUND

CDMA (Code Division Multiple Access) signals experience interference in dispersive channels. The interference is composed of self-interference (i.e. intersymbol interference), multiple access interference (i.e. interference due to non-zero code cross correlation), and other cell (i.e. downlink) or other user (i.e. uplink) interference. The interference affects two inter-related aspects of receiver performance. The first effect of interference is that some form of equalization is required in order to achieve good throughput for high data rate services. For example, to meet the enhanced throughput requirements set by 3GPP for type 2 (i.e. single antenna) and type 3 (i.e. dual anienna) receivers, a linear equalizer is needed. Second, channel estimates obtained via dedicated pilot symbols or a pilot channel are degraded. Lower-quality channel estimates affect the ability of the receiver to accurately equalize and/or estimate signal quality via SINR (signal to interference plus noise ratio). Various conventional approaches are available for addressing interference in the context of a CDMA signal. Each of these approaches account for interference during channel estimation and equalization.

There are typically two types of channel coefficients: medium and net. Medium channel coefficients refer to the complex values (magnitude and phase) associated with the radio channel. Net channel coefficients refer to the complex values associated with the composite channel response that includes the transmit filter, the medium channel coefficients, and the receive filter. Medium coefficients are denoted herein by the vector g which is an LxI vector of complex values associated with L radio channel paths. Net channel coefficients are denoted herein by the vector h which is an MxI vector of complex values ( M≥L) associated with the M receiver fingers (i.e. path delays). One conventional approach which accounts for interference during channel estimation and equalization is employed for WCDMA (Wideband CDMA) downlink signals which contain a strong pilot channel. This approach employs a relatively simple net channel estimator based on the symbols for the ri h slot as given by:

where x(n,k) is a vector of despread pilot symbols corresponding to receiver fingers for the k th symbol during the slot, $(n,k) is the kf h symbol during the n th slot, and N ? is the number of pilot symbols per slot. This simple net channel estimator can be extended to reduce noise via a relatively simple filtering operation given by:

However, there tends to be too few pilot symbols per slot available with this conventional technique for suppressing interference and noise appreciably. If the averaging indicated by equation (2) is used, noise and interference are suppressed somewhat, but the method is then essentially useful only for low speed scenarios. Generally, this method is incapable of producing truly high-quality channel estimates.

Another conventional approach is an MMSE (Minimum Mean Square Error) estimator which relies on a model for the channel and the relationship between medium and net channel coefficients. Medium channel coefficients can be converted to net coefficients as given by:

where B is an MxL conversion matrix and the (/,/) element of B is given by:

Here, R 7x , M (Δ) is the convolution of the transmit and receive filters evaluated at Δ , U 1 is the delay of the /* receiver finger, and r, is the/* path delay. The conversion from net to medium coefficients is given by:

The MMSE channel estimator can be shown to be: In equation (6), R^ is & medium coefficient coirelation matrix (i.e. £$jg" }), R Λ is an impairment covariance matrix, arid h is the net channel estimate given in equation (1). MMSE estimators tend to be highly dependent on accurate knowledge of the channel delays. When such information is available, MMSE estimators perform relatively well. However, even small errors in channel delay estimation significantly reduce the effectiveness of MMSE estimators.

Still another conventional approach is an ML (Maximum Likelihood) estimator which treats the channel coefficients as unknown deterministic parameters. The channel coefficients can be estimated directly by solving a problem of the form min|Ax -b|£. The solution to this problem can be obtained by the least squares method. To form a least squares solution, the following matrix and vector from the Λ^ pilot symbol intervals in die current slot is provided:

A whitening transformation is then applied to A and b. The whitening transformation is typically the inverse of the Cholesky factor of the impairment covariance matrix R w .

The impairment covariance matrix is Cholesky factorized as given by:

and the inverse of either the lower triangular or upper triangular factor computed. The inverse Cholesky factor is applied to A and b to give:

The transformed matrices can be used to compute relatively high quality medium channel estimates as given by:

and the corresponding net channel estimates from:

Like MMSE estimators, ML estimators tend to be highly dependent on accurate knowledge of the channel delays, and thus also suffer from even small errors in channel delay estimation.

Other conventional approaches utilize linear equalization for suppressing interference in WCDMA receivers. Linear equalization is typically performed at either the chip level or symbol level Symbol level, equalization follows the traditional Rake architecture where received chip-level data is despread at multiple delays, and the multiple images combined. Chip level equalization reverses the order of these operations. That is, the received chip data is first combined using a linear filter and then despread at a single delay. Both approaches tend to be equivalent from a performance perspective.

The G-Rake receiver is representative of a conventional symbol-level equalization approach. G-Rake combining weights are used for coherent combining as well as interference suppression. The combining weights are given by:

where R Λ is the impairment covariance matrix and h is a vector of net channel coefficients. G-Rake receivers can be implemented parametrically or non- parametrically. Nonparametric G-Rake methods are blind, and estimate R 1 , directly from observed data. Parametric G-Rake methods assume an underlying model, and compute R v from model parameters.

With chip-level equalization, the received WCDMA signal at the chip level is given by:

r = Hc + v (13)

Here, r is a W+A - l block of received chips, H is the (N + L ••• l)xN) sized Toeptitz convolution matrix whose columns are time shifted versions of the channel impulse response n with delay spread L (chip or sub-chip spaced version of the net channel coefficients), v represents white Gaussian noise άa& to neighboring base stations and thermal noise, and c is the transmitted chip sequence. A chip equalizer filter f which suppresses interference is given by:

f ^ A l b (14) where

C p - NxS sized pilot scrambling and spreading matrix

p - pilot chip sequence

It is generally assumed that there are S pilot symbols per data block and the columns of matrix R are time-shifted versions of the chip level received signal r .

WCDMA linear equalization can be thought of as applying a filter to undo the effect of the channel-induced interference. Some conventional approaches partition the filter into two or more sub-fihers, an approach that can be thought of as split equalization. For example, a nonlinear equalizer may be required for certain applications such as EDGE (Enhanced Data rates for GSM Evolution) to meet particular performance targets. However, the complexity of a nonlinear equalizer is a function of the number of channel taps. Therefore, channel shortening (channel compacting) pre-filters have been designed to minimize the number of channel taps. Conventional pre-filters typically do not color the noise and interference, but simply concentrate the channel energy into a few taps. The pre-filter is followed by a DFSE (decision feedback sequence estimation) nonlinear equalizer. The combination of the pre-filter and DFSE equalizer performs the overall equalization task for an EDGE receiver.

Conventional split equalizers (pre-filter + DFSE) do not readily extend to WCDMA. It is typically assumed that the receiver has good information about the channel delays. For example, the receiver can hypothesize that there are either N or M symbol-spaced channel taps ( N≠M ). A pre-δlter is then provided for each hypothesized number of channel taps, and the pre-filter that gives the best performance is utilized. However, a WCDMA receiver does not have such accurate knowledge of channel tap locations, thus making implementation difficult. Linear equalizers for CDMA systems have generally been concentrated into one filter and implemented in the time domain. This limits the effective span of the equalizer and can inhibit the ability of the equalizer to handle dispersive scenarios. To obtain exact desired filter responses with time domain filtering, the required filter lengths often become unpractically long, and thus impose a significant computational load. In practice, the filter response length is typically limited in the actual implementation. Doing so lowers the filtering accuracy and causes unwanted noise enhancement, as the first filtering stage causes uncontrolled frequency response variations in the signal passband.

SUMMARY

According to the methods and apparatus disclosed herein, channel estimation and/or equalization processing is performed in a wireless receiver in two stages. The first stage includes pre-filtering the received signal in the frequency domain. The pre~ filtering operation involves compacting the net channel into a grid-based representation for subsequent processing. Pre-flltering in the frequency domain using the compacted grid-based representation of the net channel eliminates the need for precise channel delay information. In addition, pre-filtering in the frequency domain is relatively less complex compared to purely time domain processing of dispersive channels. The second stage of die signal processing techniques disclosed herein implements reduced- complexity time domain channel estimation and/or equalization. In one embodiment, the first stage is implemented as a chip-level pre-filter in the frequency domain and the second stage is implemented as a symbol-level channel estimator and/or equalizer in the time domain.

According to an embodiment of a method for processing a received signal transmitted over a net channel, the method includes pre-filtering the received signal in the frequency domain. The pre-fihering compacts an N-tap effective grid-based representation of the net channel into a K-tap compacted grid-based representation of the net channel where K < N. The pre-filtered received signal is equalized in the time domain based on the K-tap compacted grid-based representation of the net channel generated by pre-filtering the received signal in the frequency domain. Accordrøg to an embodiment of a wireless receiver, the receiver includes a first processing module and a second processing module. The first processing module is operable to generate an N-tap effective grid-based representation of a net channel over which a received signal is transmitted. The first processing module is also operable to pre-filter the received signal in the frequency domain to compact the N-tap effective grid-based representation of the net channel into a K-tap compacted grid-based representation of the net channel where K < N. The second processing module is operable to equalize the pre-fϊltered received signal in the time domain based on the K- tap compacted grid-based representation of the net channel generated by the first processing module.

Of course, the present invention is not limited to the above features and advantages. Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 illustrates a block diagram of an embodiment of a wireless communication system including a transmitter and a receiver.

Figure 2 illustrates a block diagram of an embodiment of signal processing modules included in the receiver of Figure 1.

Figure 3 illustrates an embodiment of a grid-based net channel representation compacted by the receiver of Figure I for implementing frequency domain pre-filtering and subsequent time domain processing.

Figure 4 illustrates an embodiment of a power delay profile for determining the COG of the net channel experienced by the receiver of Figure I .

DETAILED DESCRIPTION

Figure 1 illustrates an embodiment of a communication system in which a transmitter 100 communicates with a receiver 1 10 over a wireless channel 120. For downlink transmissions, the transmitter 100 can be a base station such as a Node B and the receiver 1 10 can be a mobile wireless device serviced by the base station such as

UE (user equipment). Conversely, the transmitter 100 can be a mobile wireless device and the receiver 1 10 a base station for uplink transmissions. In either case, the receiver i 10 has a baseband processor 130 for processing a received signal. A first processing module 140 included in or associated with die baseband processor 130 implements chip level pre-fiUering of the received signal in the frequency domain. A second processing module 150 included in or associated with the baseband processor 130 implements symbol level or chip level channel estimation and/or equalization in the time domain after pre~fιhering of the received signal. The two-stage, multi-domain signal processing implemented by the first and second processing modules 140, 150 eliminates the need for precise channel delay information while utilizing reduced complexity time domain processing for channel estimation and/or equalization.

Figure 2 illustrates an embodiment of the first and second processing modules 140, 150 which implement the two-stage, multi-domain signal processing. Front end circuitry 200 filters and do wn~con verts the received signal r(/) into a chip-level received signal r\t) , the term * chip ^ referring to the fundamental unit of transmission in CDMA. During the first processing stage, the chip-level received signal is pre-δltered in the frequency domain by the first processing module 140. To this end, the first processing module 140 generates a grid-based representation of the net channel which corresponds to the transmit filtering, radio channel 120 and receive filtering experienced by the transmitted signal. The first processing module 140 compacts the grid-based channel representation by concentrating the channel energy into the initial channel taps for use in pre-filtering the received signal in the frequency domain. The initial grid-based representation of the net channel has N taps (delays) spaced apart in accordance with a spacing interval /^ . The first processing module 140 includes a grid formulation component 210 for generating the grid-based representation of the net channel The grid formuiator 210 centers the grid based on coarse channel information provided by a path searcher component 220 of the first processing module 140.

Figure 3 illustrates an embodiment of the grid-based representation of the net channel generated by the grid formuiator component 210 of the first processing module

140. Each grid point, denoted by the label 'X' in Figure 3, represents a delay value. This grid-based channel representation is not generated based on precise channel delay information. That is, the grid points do not directly correspond to specific path delay values determined for the net channel. Instead, the grid is constructed based on coarse channel information provided by the path searcher 220. The grid formulator 210 uses the coarse channel information to center the grid. Once centered, adjacent grid points can be added which are spaced apart from one another in accordance with the spacing interval T ilaf(βi , 7^ 1 preferably being set near the Nyquist rate or less. Other grid spacing intervals can be used depending on the application. For example, T mβi can be set above the Nyquist rate if desired.

In one embodiment, the coarse channel information provided by the path searcher 220 for centering the grid-based representation of the net channel represents an approximate center of gravity (COG) of die net channel. The path searcher 220 can determine the COG of the net channel based on a power delay profile (PDP) for the net channel as shown in Figure 4. In another embodiment, the path searcher 220 identifies the strongest path delay associated with the net channel. Yet other techniques may be employed for centering the grid, e.g. as disclosed in U.S. Patent Application No. 12/408.939 filed on March 23. 2009, the content of which is incorporated herein by reference in its entirety, in each case, the grid-based representation of the net channel is centered based on coarse channel information, not precise channel delay information. Accordingly, errors in the COG or path delays do not have a significant adverse affect on the performance of the two-stage received signal processing performed by the first and second processing modules 140, 150.

In one embodiment, the grid formulation component 210 of the first processing module 140 builds out the grid by adding grid points which are spaced apart based on a sub-chip spacing interval of T^, = TJl , where T c corresponds to the chip interval of the received signal. Ln another embodiment, the grid formulator 210 employs a sub- chip spacing interval of 7^, - 3T β /4 for spacing the grid points. In each case, the first processing module 140 then compacts the N-tap effective grid-based representation of the net channel into a compacted grid-based net channel representation having K taps where K < N. Compacting the grid-based channel representation concentrates the channel energy into the leading channel taps, simplifying processing while maintaining a grid-based representation of the net channel . In one embodiment, the grid is compacted by generating pre-filter coefficients based on the net channel representation generated by the grid fbrmulator 210. To this end, the first processing module 140 includes a coefficient calculator 230 tor calculating the pre-filter coefficients. The pre-filter coefficients are designed to compact the net channel representation such that the compacted representation corresponds to a second grid having A' leading channel taps (delays) spaced apart by T 1110 ^ 2 , where T s(age2 can be less than, greater than or equal tof ' stage] . The coefficient calculator 230 performs the pre-filter response calculations in the time domain or the frequency domain. Various design criteria can be accounted for when calculating the pre-filter coefficients, e.g. as disclosed in U.S. Patent Nos. 6,608,862 and 6,826,226, the contents both of which are incorporated herein by reference in their entirety. The first processing module 140 then pre-filters the chip-level received signal r'(/) in the frequency domain using a frequency domain representation of the pre-filter coefficients.

The first processing module 140 includes an FFT (Fast Fourier Transform) engine 240 for implementing the frequency domain pre-fϊltering. In one embodiment, the receiver 110 is compatible with both WCDMA and LTE (Long Term Evolution), and thus makes use of the FFT engine already typically available for supporting LTE. The modulation / demodulation of an LTE signal is based on frequency domain processing, and thus the FFT engine of an LTE receiver can be reused to implement the frequency domain processing described herein, improving the performance and/or cost of the corresponding WCDMA receiver. Otherwise, the FFT engine 240 is added as a new component to the receiver 110. In either case, the FFT engine 240 pre-filters the received signal by multiplying a frequency domain representation of the pre-filter coefficients and a frequency domain representation of the received signal.

Following the first stage, the net channel energy is concentrated into A' taps having known locations spaced apart by 7^, . With this information, the second processing module 150 can equalize the received signal in the time domain. The second processing module 150 can also perform channel estimation during the second stage so that an estimate of the amplitude and phase shift caused by die wireless channel 120 is available. In one embodiment, the received signal is despread by a despreader component 250 of the second processing module 150. The despread samples are used by a channel estimation component 260 of the second processing module 150 to generate medium channel estimates such as MMSE estimates as disclosed in U.S. Patent Application No. 1 1/935,604, filed on November 6, 2007 or ML estimates as disclosed in U.S. Patent Application No. 12/027,492, filed on February 7, 2008, the contents both of which are incorporated herein by reference in their entirety.

The second processing module 150 also includes an equalizer component 270 for performing equalization at either the chip level or symbol level so that the interference due of the wireless channel 120 can be mitigated, allowing subsequent symbol demodulation. Equalization is performed with significantly reduced complexity since the net channel has been compacted as previously described herein. Equalization complexity is reduced because of the simple finger/tap (delay) placement made possible by the grid nature of the effective channel and because fewer lingers/taps (delays) are needed because the channel is relatively compact Using a compacted grid-based representation of the net channel enables the use of nonlinear equalization because the state space needed to implement a nonlinear equalizer reduces to a realistic size for nonlinear equalization techniques such as an MLSB (Maximum Likelihood Sequence Estimation).

Described next is an embodiment of a method for processing a signal received by die receiver 1 10 of Figure 1. According to this embodiment, steps are described for realizing a combination of linear symbol level equalization and ML channel estimation. The path searcher component 220 of the first processing module 140 performs a path search. The grid formulation component 210 of the first processing module 140 constructs a contiguous grid of pre-fllter taps (delays) centered on the COG or strongest reported path delay associated with the net channel. The grid points have a spacing interval of T s(age \ corresponding to N taps (delays). In some embodiments, the grid can be adaptively constructed responsive to the channel RMS (Root Mean Square) delay spread, e.g. as described in U.S. Patent Application No. 12/408,939.

The method continues with the coefficient calculator component 230 of the first processing module 140 computing pre-filter tap coefficients p(ι) based on the grid- based channel model generated by the grid formulator 210, e.g. based on the approach described in U.S. Patent No. 6,826,226. The received signal is then pre-filtered by the FFT engine 240. The pre-fϋtering operation is realized in the frequency domain by transforming the chip-level received signal r'(l) to the frequency domain as given by:

The pre-fiUer tap coefficients p(f) are also transformed to the frequency domain as given by:

The FFT engine 240 multiplies the transformed signals as given by:

{ { )

The FFT engine 240 applies appropriate zero padding so that (J 7) describes the frequency domain version of linear convolution, e.g. in. accordance with the Overlap- add' or Overlap-save' approaches described in A. Oppenheim, R. Scha/er, Discrete- Time Signal Processing, Prentice-Hall, Englewood Cliffs NJ, copyright 1989, the related content of which is incorporated herein by reference. The FFT engine 240 then transforms the pre-fUtered signal back to the time domain by applying an [FFT (Inverse FFT) to X(ω) as given by:

The pre-filtered time domain received signal .r(/)is then despread by the despreader component 250 of the second processing module 150. The channel estimator component 160 of the second processing module 150 performs medium channel estimation using the despread information, e.g. in accordance with the ML approach described in U.S. Patent Application No. 12/027,492 given the K effective compacted channel taps with grid spacing T mge 2 - 7 s t age)■

In addition or alternatively, the pre-filtered received signal x(l) output by the

FFT engine 240 can processed by the equalizer component 270 of the second processing module 150. The equalizer 270 can perform symbol-level parametric equalization using a grid of lingers (delays) centered on the COG or strongest path delay of the new effective channel (i.e., post pre-filtering), e.g. in accordance with US

Patent Application 2005/0201447, filed September 15, 2005, the content of which is incorporated herein by reference in its entirety. Alternatively, the equalizer 270 can perform non-parametric symbol-level equalization using the centered grid of fingers (delays), e.g. ix» accordance with US Patent Application 2008/0304554, filed December I I, 2008, the content of which is incorporated herein by reference in its entirety. The number of grid fingers (delays) can be optimized, e.g. offline to give very good performance for a known K-tep compacted net channel.

The receiver structure disclosed herein combines frequency domain and rime domain processing. The frequency-domain pre-filtering described herein allows the exact desired first stage response to be applied without introducing noise enhancement due to filter truncation. In addition, performing frequency domain pre-filtering via FFT processing is computationally efficient. Use of the grid-based pre-filtering for WCDMA signals eliminates the need to hypothesize all expected wideband channels. Furthermore, grid-based pre-filtering of WCDMA signals is less sensitive to path searcher inaccuracies. Even small path searcher inaccuracies can have significant impact on conventional model-based channel estimation/equalization algorithms. The receiver structure described herein also enables efficient implementation of MMSE and ML channel estimation. Highly dispersive channels can also be efrkiently equalized. Also, the receiver structure disclosed herein reduces the complexity of nonlinear equalization and is readily extend ble to other wireless communication technologies such as TDMA (Time Division Multiple Access).

With the above range of variations and applications in mind, it should be understood that the present invention is not limited by the foregoing description, nor is it limited by the accompanying drawings. Instead, the present invention is limited only by the following claims, and their legal equivalents.