LAMINATE STRUCTURE AND THIN-FILM TRANSISTOR

Title:

LAMINATE STRUCTURE AND THIN-FILM TRANSISTOR

Document Type and Number:

WIPO Patent Application WO/2024/029429

Kind Code:

A1

Abstract:

This laminate structure has an underlying insulating layer, a metal oxide layer disposed on the underlying insulating layer, and an oxide semiconductor layer disposed in contact with the metal oxide layer. The oxide semiconductor layer has a region in which a metal element, this metal element being the same as a metal element contained in the metal oxide layer, exhibits a concentration gradient, wherein the concentration gradient of the metal element exhibits an increase as the metal oxide layer/oxide semiconductor layer interface is approached.

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Inventors:

WATAKABE HAJIME (JP)
TSUBUKU MASASHI (JP)
SASAKI TOSHINARI (JP)
TAMARU TAKAYA (JP)
KAWASHIMA EMI (JP)
TSURUMA YUKI (JP)
SASAKI DAICHI (JP)

Application Number:

PCT/JP2023/027457

Publication Date:

February 08, 2024

Filing Date:

July 26, 2023

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Assignee:

JAPAN DISPLAY INC (JP)
IDEMITSU KOSAN CO (JP)

International Classes:

H01L21/363; C23C14/08; H01L29/786

Domestic Patent References:

WO2013021632A1	2013-02-14
WO2014136612A1	2014-09-12

Foreign References:

JP2017126693A	2017-07-20
JP2013102158A	2013-05-23
JP2011228695A	2011-11-10

Other References:

MIYAZAKI TORU: "The Formation of Microstructure in Materials and Its Theoretical Basis (IV) ~The Formation Process of Microstructure Based on Interdiffusion~", MATERIA JAPAN, NIHON KINZOKU GAKKAI, SENDAI, JP, vol. 53, no. 11, 1 January 2014 (2014-01-01), JP , pages 550 - 557, XP093134671, ISSN: 1340-2625, DOI: 10.2320/materia.53.550

Attorney, Agent or Firm:

TAKAHASHI, HAYASHI AND PARTNER PATENT ATTORNEYS, INC. (JP)

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