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Title:
LAMINATED CERAMIC CAPACITOR
Document Type and Number:
WIPO Patent Application WO/2012/120712
Kind Code:
A1
Abstract:
[Problem] To provide a laminated ceramic capacitor that can be baked at a temperature at or below 1030°C, and that, even if made thinner, has a high dielectric constant, favorable use life characteristics, and temperature characteristics satisfying X7R. [Solution] The present invention is structured in a manner such that, when the thickness of a dielectric ceramic layer sandwiched by inner electrodes is d, the grain size distribution of primary phase grains having BaTiO3 as the primary component satisfies D20 ≤ D50 × 0.7, D50 ≤ d/4, D95 ≤ d/2, and the CV value ((standard deviation of D20-D95)/D50) < 40%. Also, the present invention is structured in a manner such that secondary phase grains configured from at least Re (Re including at least one of Eu, Gd, Dy, Ho, Er, Yb, and Y), Ba, and Ti are present in the dielectric ceramic layer, and in any given 5 μm × 5 μm dielectric layer cross sectional region, there are on average at least five of the secondary phase having a grain size of at least 0.10 μm, and there are on average less than two of the secondary phase having a grain size of at least D80 of the primary phase grains.

Inventors:
TAKASHIMAI KENJI (JP)
TAKEOKA SHINSUKE (JP)
Application Number:
PCT/JP2011/071789
Publication Date:
September 13, 2012
Filing Date:
September 26, 2011
Export Citation:
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Assignee:
TAIYO YUDEN KK (JP)
TAKASHIMAI KENJI (JP)
TAKEOKA SHINSUKE (JP)
International Classes:
C04B35/468; H01B3/12; H01G4/12; H01G4/30
Foreign References:
JP2005217305A2005-08-11
JP2005162557A2005-06-23
JP2008072072A2008-03-27
JP2009256140A2009-11-05
JP2006327890A2006-12-07
JP2010052964A2010-03-11
JP2007331957A2007-12-27
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