Title:
LAMINATED CIRCUIT STRUCTURE FOR REDUCING PARASITIC INDUCTANCE
Document Type and Number:
WIPO Patent Application WO/2021/040152
Kind Code:
A1
Abstract:
The present invention relates to a laminated circuit structure and, more specifically, a laminated circuit structure for reducing parasitic inductance. A laminated circuit structure according to an embodiment of the present invention may comprise: a first layer having a first electrical path; a second layer having a second electrical path which is connected to the first electrical path to form a first loop; a third layer having a third electrical path; and a fourth layer having a fourth electrical path which is connected to the third electrical path to form a second loop. The laminated circuit structure according to the present invention can effectively reduce parasitic inductance through the formation of a plurality of loops.
Inventors:
KIM RAEYOUNG (KR)
YANG SISEOK (KR)
YANG SISEOK (KR)
Application Number:
PCT/KR2019/017693
Publication Date:
March 04, 2021
Filing Date:
December 13, 2019
Export Citation:
Assignee:
IUCF HYU (KR)
International Classes:
H05K1/02
Foreign References:
| JP2018182867A | 2018-11-15 | |||
| JP2017208531A | 2017-11-24 | |||
| KR20130044633A | 2013-05-03 | |||
| KR20170068273A | 2017-06-19 | |||
| JP2016503963A | 2016-02-08 |
Attorney, Agent or Firm:
CHUNG, Sungjoon (KR)
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