LAMINATED CIRCUIT SUBSTRATE - MURATA MANUFACTURING CO

Title:

LAMINATED CIRCUIT SUBSTRATE

Document Type and Number:

WIPO Patent Application WO/2014/125894

Kind Code:

A1

Abstract:

A laminated circuit substrate (101) in which a capacitor (C1) and a coil (L1) are provided, and which is manufactured by laminating sheets (11-15), and using an implement (90) to pressure bond the sheets from the vertical lamination direction while heating. The capacitor (C1) comprises a first conductive pattern (32A) and a second conductive pattern (33A) which oppose one another by sandwiching thermoplastic resin layers (22, 23). With respect to the laminated circuit substrate (101), a roughening process is performed on: a first main surface (91) of the first conductive pattern (32A), said first main surface opposing the second conductive pattern (33A); and a second main surface (92) of the second conductive pattern (33A), said second main surface opposing the first conductive pattern (32A).

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Inventors:

YOSUI KUNIAKI (JP)
OZAWA MASAHIRO (JP)

Application Number:

PCT/JP2014/051455

Publication Date:

August 21, 2014

Filing Date:

January 24, 2014

Export Citation:

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Assignee:

MURATA MANUFACTURING CO (JP)

International Classes:

H05K3/46; H01F17/00; H01G4/12; H01L23/12

Foreign References:

JP2012195423A	2012-10-11
JP2008160042A	2008-07-10
JP2012186451A	2012-09-27
JP2007317955A	2007-12-06
JP2012015239A	2012-01-19
JPH0735414Y2	1995-08-09

Attorney, Agent or Firm:

Kaede Patent Attorneys' Office (JP)
Patent business corporation Kaede Patent Attorneys' Office (JP)

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