Title:
LAMINATED WIRING BOARD AND PROBE CARD PROVIDED WITH SAME
Document Type and Number:
WIPO Patent Application WO/2015/151809
Kind Code:
A1
Abstract:
A laminated wiring board obtained by laminating a resin laminate on a ceramic laminate, wherein interfacial peeling between the ceramic laminate and the resin laminate is reduced. The laminated wiring board (1a) is provided with: a ceramic laminate (2) obtained by laminating a plurality of ceramic layers (3); a resin laminate (4) obtained by laminating a plurality of resin layers (4a), the resin laminate (4) being laminated on the ceramic laminate (2); via conductors (9a) provided to the uppermost ceramic layer (3), the upper end surface of the via conductors (9a) being exposed on the interface between the ceramic laminate (2) and the resin laminate (4); and via conductors (9b) provided on the lowermost resin layer (4a), the lower end surface of the via conductors (9b) being exposed on the interface between the ceramic laminate (2) and the resin laminate (4) and directly connected to the upper end surface of the via conductors (9a) in the uppermost ceramic layer (3). The lower end surface of the resin-layer-(4a)-side via conductors (9b) is formed so as to fit within the upper end surface of the ceramic-layer-(3)-side via conductors (9a) in plan view.
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Inventors:
TAKEMURA TADAJI (JP)
OTSUBO YOSHIHITO (JP)
OTSUBO YOSHIHITO (JP)
Application Number:
PCT/JP2015/057998
Publication Date:
October 08, 2015
Filing Date:
March 18, 2015
Export Citation:
Assignee:
MURATA MANUFACTURING CO (JP)
International Classes:
H05K3/46; G01R1/073; H01L21/66
Domestic Patent References:
| WO2012124362A1 | 2012-09-20 |
Foreign References:
| JP2005223225A | 2005-08-18 | |||
| JPH08255976A | 1996-10-01 | |||
| JP2013247336A | 2013-12-09 | |||
| JP2010003871A | 2010-01-07 | |||
| JP2003198130A | 2003-07-11 | |||
| JP2011119615A | 2011-06-16 | |||
| JP2005203680A | 2005-07-28 |
Attorney, Agent or Firm:
YANASE, Yuji et al. (JP)
Yuji Yanase (JP)
Yuji Yanase (JP)
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