Title:
LAMP SIGNAL GENERATION CIRCUIT AND CMOS IMAGE SENSOR
Document Type and Number:
WIPO Patent Application WO/2013/073585
Kind Code:
A1
Abstract:
This lamp signal generation circuit (21) is provided with a plurality of unit circuits (221 to 22N), which have a capacitor (26) in which the potential of one end (26a) is fixed and a current source (27) which is connected to the other end (26b) of the capacitor (26), wherein each of the other ends (26b) of the capacitors (26) possessed by the plurality of unit circuits (221 to 22N) are connected to one another by wiring members (W).
Inventors:
KAWAHITO SHOJI (JP)
IMAI KAITA (JP)
IMAI KAITA (JP)
Application Number:
PCT/JP2012/079535
Publication Date:
May 23, 2013
Filing Date:
November 14, 2012
Export Citation:
Assignee:
UNIV SHIZUOKA NAT UNIV CORP (JP)
International Classes:
H03M1/56; H03K4/02; H04N5/378
Foreign References:
| JP2008309811A | 2008-12-25 | |||
| JP2009130828A | 2009-06-11 | |||
| JP2007088971A | 2007-04-05 |
Other References:
YONG LIM ET AL.: "A 1.1 Temporal Noise 1/3.2-inch 8Mpixel CMOS Image Sensor Using Pseudo-Multiple Sampling", ISSCC 2010 DIG. TECH. PAPERS, 2010, pages 396 - 398
SAKKARAPANI BALAGOPAL ET AL.: "An On-chip Ramp Generator for Single-Slope Look Ahead Ramp (SSLAR) ADC", IEEE MWSCAS, 2009, pages 373 - 376, XP031528140
See also references of EP 2782258A4
SAKKARAPANI BALAGOPAL ET AL.: "An On-chip Ramp Generator for Single-Slope Look Ahead Ramp (SSLAR) ADC", IEEE MWSCAS, 2009, pages 373 - 376, XP031528140
See also references of EP 2782258A4
Attorney, Agent or Firm:
HASEGAWA Yoshiki et al. (JP)
Yoshiki Hasegawa (JP)
Yoshiki Hasegawa (JP)
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