LATCH CIRCUIT AND CLOCK CONTROL CIRCUIT

Title:

LATCH CIRCUIT AND CLOCK CONTROL CIRCUIT

Document Type and Number:

WIPO Patent Application WO/2011/074050

Kind Code:

A1

Abstract:

Provided is a latch circuit comprising a latch unit and a clock propagation suppressing unit. The latch unit holds and outputs inputted data of 0 or 1. The clock propagation suppressing unit compares input data inputted to the latch unit and output data outputted from the latch unit. When it is detected that the input data and the output data are 0 and match each other or it is detected that the input data and the output data are 1 and match each other, the clock propagation suppressing unit suppresses the propagation of a clock signal, which is inputted from outside, through the latch unit.

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Inventors:

KANARI KATSUNAO (JP)

Application Number:

PCT/JP2009/007039

Publication Date:

June 23, 2011

Filing Date:

December 18, 2009

Export Citation:

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Assignee:

FUJITSU LTD (JP)
KANARI KATSUNAO (JP)

International Classes:

H03K3/356

Foreign References:

JP2001308686A	2001-11-02
JPH04306013A	1992-10-28
JP2004056667A	2004-02-19
JPH10290143A	1998-10-27
JPH09214297A	1997-08-15
JPH11340795A	1999-12-10
JPH04298115A	1992-10-21
JPH10290143A	1998-10-27
JPH0486116A	1992-03-18
JPH11340795A	1999-12-10
JP2000077983A	2000-03-14
JP2006229745A	2006-08-31
JPH09214297A	1997-08-15

Other References: