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Title:
LATCH CIRCUIT AND FLIP-FLOP CIRCUIT HAVING SINGLE EVENT UPSET RESISTENCE
Document Type and Number:
WIPO Patent Application WO/2018/230235
Kind Code:
A1
Abstract:
Provided are a latch circuit and a flip-flop circuit that have superior single event upset (SEU) resistence. The latch circuit according to the present invention having single event upset (SEU) resistence is configured such that, with respect to the eight transistors configuring a conventional DICE latch circuit, each is replaced with four transistors by adding redundant transistors at the three locations of series, parallel, and series-parallel positions, in order to replace serial redundancy with parallel redundancy, and a first data input section and a second data input section are also made doubly redundant.

Inventors:
MARU AKIFUMI (JP)
KUBOYAMA SATOSHI (JP)
EBIHARA TSUKASA (JP)
MAKIHARA AKIKO (JP)
Application Number:
PCT/JP2018/018955
Publication Date:
December 20, 2018
Filing Date:
May 16, 2018
Export Citation:
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Assignee:
JAPAN AEROSPACE EXPLORATION (JP)
HIGH RELIABILITY ENG & COMPONENTS CORPORATION (JP)
International Classes:
H03K3/356
Foreign References:
JP2009118335A2009-05-28
US6696873B22004-02-24
US6327176B12001-12-04
US20040017237A12004-01-29
US6696874B22004-02-24
US6696873B22004-02-24
US6327176B12001-12-04
US20040017237A12004-01-29
US6696874B22004-02-24
US6696873B22004-02-24
US6327176B12001-12-04
US20040017237A12004-01-29
US6696874B22004-02-24
Other References:
T. CALINM. NICOLAIDISR. VELAZCO: "IEEE TRANSACTIONS ON NUCLEAR SCIENCE", vol. 43, December 1996, IEEE, article "Upset Hardened Memory Design for Submicron CMOS Technology", pages: 2874 - 2878
See also references of EP 3641132A4
Attorney, Agent or Firm:
TANAKA Shinichiro et al. (JP)
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