[0001] This Patent Application claims priority to U.S. Provisional Patent Application No. 61/492201, filed on June 1, 2011, entitled "Latching Circuits for MEMS Display Devices" and U.S. Non Provisional Application No. 13/483975, filed on May 30, 2012, entitled "Latching Circuits for MEMS Display Devices." The disclosure of the prior Applications are considered part of and are incorporated by reference in this Patent Application.

TECHNICAL FIELD

[0002] The disclosure relates to the field of latching circuits. In particular, this disclosure relates to pixel circuits and display devices that include the latching circuits.

DESCRIPTION OF THE RELATED TECHNOLOGY

[0003] Display devices use two-dimensional arrangements of light modulating elements to display images and video content. Selective modulation of light at each pixels of the two- dimensional array produces the images of each frame of content.

[0004] Some display devices actuate light modulators (such as shutters) by mechanical means in order to display the image or video content. A display device that actuates a shutter by electrical means can facilitate faster shutter movement, and thus provide for faster pixel refresh rates during display.

SUMMARY

[0005] The systems, methods and devices of the disclosure each have several innovative aspects, no single one of which is solely responsible for the desirable attributes disclosed herein. [0006] One innovative aspect of the subject matter described in this disclosure can be implemented in an apparatus having a plurality of MEMS devices arranged in an array and a control matrix comprising only n-type or only p-type transistors coupled to the plurality of MEMS devices to communicate data and drive voltages to the MEMS devices. For each MEMS device, the control matrix includes a latch configured to maintain a difference in voltage levels on a first output terminal and a second output terminal. The latch includes a first pre-charge transistor and a first output terminal discharge transistor coupled to the first output terminal, a second pre-charge transistor and a second output terminal discharge transistor coupled to the second output terminal and a pixel discharge transistor coupled to the first output terminal discharge transistor and the second output terminal discharge transistor. The latch is configured such that a state of the first output terminal discharge transistor is controlled based on a voltage level of the second output terminal applied to a gate of the first output terminal discharge transistor. In some implementations, the first pre-charge transistor can be a diode-connected transistor. In some implementations, the apparatus is a display apparatus and the MEMS device includes a shutter that is actuated based on the voltage levels on the first output terminal and the second output terminal. In some implementations, the apparatus also includes a first latching control line that is coupled to the first output terminal by the first pre-charge transistor and configured to apply a first driver voltage and to pre-charge the first output terminal from a first voltage level to a second voltage level that is different from the first voltage level based on application of the first driver voltage. The apparatus can be configured to discontinue the first driver voltage such that the first output terminal returns to the first voltage level or maintains the first output terminal at the second voltage level based on a voltage retained in a retention capacitor.

[0007] In some implementations, an end of the retention capacitor is connected to the first latching control line and the first driver clock voltage acts as a bias voltage of the retention capacitor. In some implementations, a second latching control line is coupled to the second output terminal by the second pre-charge transistor and configured to apply a second driver voltage and pre-charge the second output terminal from the first voltage level to the second voltage level based on application of the second driver voltage. In some such

implementations, the apparatus is configured to discontinue the second driver voltage at a later time than the first driver voltage is discontinued such that the voltage is retained in the retention capacitor. In some implementations, the apparatus is configured to initiate the first driver voltage and the second driver clock voltage at a same time. In some implementations, the pixel discharge transistor controls a discharge of the first output terminal and the second output terminal through the first output terminal discharge transistor and the second output terminal discharge transistor. In some implementations, each of the first pre-charge transistor, the first output terminal discharge transistor, the second pre-charge transistor and the second output terminal discharge transistor is configured as two transistors coupled with a common gate.

[0008] Another innovative aspect of the subject matter described in this disclosure can be implemented in an apparatus having a plurality of MEMS devices arranged in an array and a control matrix that includes only n-type or only p-type transistors coupled to the plurality of MEMS devices to communicate data and drive voltages to the MEMS devices. For each MEMS device, the control matrix includes a latch that is configured to maintain a difference in voltage levels on a first output terminal and a second output terminal and includes a first pre-charge transistor and a first output terminal discharge transistor coupled to the first output terminal and a second output terminal discharge transistor coupled to the first output terminal discharge transistor. The latch is further configured such that the output of the second output terminal discharge transistor selectively controls the first output terminal discharge transistor to selectively discharge voltage stored on the first output terminal, thereby controlling a voltage level of the first output terminal. In some implementations, the first pre-charge transistor can be a diode-connected transistor.

[0009] In some implementations, the apparatus is a display apparatus and the MEMS device includes a shutter that is actuated based on the voltage levels on the first output terminal and the second output terminal. In some implementations, the apparatus further includes a first latching control line coupled to the first output terminal by the first pre-charge transistor and configured to apply a first driver voltage and a second latching control line coupled to the second output terminal discharge transistor and configured to apply a second driver voltage to switch the second output terminal discharge transistor. In some such implementations, the apparatus is configured to discontinue the second driver voltage at a later time than the first driver voltage is discontinued such that the second output terminal discharge transistor controls the discharge of the first output terminal discharge transistor, thereby controlling a voltage level of the first output terminal. In some implementations, the apparatus is configured to maintain the voltage level of the first output terminal until a subsequent the first driver voltage is applied. In some implementations, the apparatus is configured to initiate the first driver voltage and the second driver clock voltage at a same time. In some implementations, each of the first pre-charge transistor, the first output terminal discharge transistor and the second output terminal discharge transistor is configured as two transistors coupled with a common gate.

[0010] Another innovative aspect of the subject matter described in this disclosure can be implemented in an apparatus having a plurality of MEMS devices arranged in an array and a control matrix that includes only n-type or only p-type transistors coupled to the plurality of MEMS devices to communicate data and drive voltages to the MEMS devices. For each MEMS device, the control matrix includes a latch that is configured to maintain a difference in voltage levels on a first output terminal and a second output. The latch includes a first pre- charge transistor and a first output terminal discharge transistor coupled to the first output terminal and a first latching control line coupled to the first output terminal by the first pre- charge transistor. The first output terminal discharge transistor is coupled to an electrode of the first latching control line. The apparatus can be configured to apply, to the first latching control line, a first driver voltage that changes from an intermediate voltage level that has a magnitude intermediate between a first voltage level and apply a second voltage level, to the second level voltage, from the second voltage level to the first voltage level, and from the first voltage level to the intermediate voltage level at a time that a voltage on the first output terminal changes from the first voltage level to the second voltage level. In some

implementations, the latch is configured such that applying the first driver voltage changes a voltage level of the first output terminal from the first voltage level to the second voltage level. In some implementations, the first pre-charge transistor can be diode-connected transistor. In some implementations, the apparatus is a display apparatus and the MEMS device includes a shutter that is actuated based on the voltage levels on the first output terminal and the second output terminal.

[0011] Details of one or more implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below.

Although the examples provided in this summary are primarily described in terms of MEMS- based displays, the concepts provided herein may apply to other types of displays, such as LCD, OLED, electrophoretic, and field emission displays, as well as to other non-display MEMS devices, such as MEMS microphones, sensors, and optical switches. Other features, aspects, and advantages will become apparent from the description, the drawings, and the claims. Note that the relative dimensions of the following figures may not be drawn to scale.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 shows an example latching circuit.

[0013] Figure 2 shows an example timing diagram for operation of the latching circuit of

Figure 1.

[0014] Figure 3 shows an example pixel circuit that can be used in a display.

[0015] Figure 4 shows a schematic of an example display.

[0016] Figure 5 shows an example latching circuit.

[0017] Figure 6 shows an example timing diagram for operation of the latching circuit of

Figure 5.

[0018] Figure 7 shows an example latching circuit.

[0019] Figure 8 shows another example latching circuit.

[0020] Figure 9 shows another example latching circuit.

[0021] Figure 10 shows another example latching circuit.

[0022] Figure 11 shows another example latching circuit.

[0023] Figure 12 shows an example timing diagram for operation of the latching circuit of

Figure 11.

[0024] Figure 13 shows an example pixel circuit.

[0025] Figure 14 shows another example latching circuit.

[0026] Figure 15 shows another example latching circuit.

[0027] Figure 16 shows an example timing diagram for operation of the latching circuit of

Figure 15. [0028] Figure 17 shows another example latching circuit.

[0029] Figure 18 shows another example latching circuit structure formed with p-type MOS transistors.

[0030] Figure 19 shows an example timing diagram for operation of the latching circuit of Figure 18.

DETAILED DESCRIPTION

[0031] Certain display apparatus utilize latching circuits to control the actuation of the light modulators, such as mechanical shutters, employed by the display apparatus to generate images. These latching circuits are typically fabricated as complementary metal-oxide- semiconductor (CMOS) circuit using CMOS fabrication techniques in the art and including both N-MOS and P-MOS type transistors.

[0032] The CMOS manufacturing process for fabricating the latching circuits can be complex. For example, when fabricating a latching circuit using polycrystalline silicon-based transistors, the process can require up to six, and even as many as ten or more photo processes.

[0033] Apparatus and methods herein provide latching circuits, pixel circuits, and displays based on latching circuits that are fabricated from transistors of a single conductivity type (i.e., only n-type transistors or only p-type transistors). As a result, complexity of the manufacturing process for fabricating the latching circuits can be reduced. Timing schemes are described which can facilitate the latching of information in a comparatively shorter interval than existing latches.

[0034] In some implementations, the state of the light modulators in the display is set by selectively discharging one of two output terminals that might attract a light modulator. The discharge of each terminal is controlled by an output terminal discharge transistor. In some implementations, the latching circuit includes a separate pixel-level discharge transistor that prevents discharge of the output terminal charge through either output terminal discharge transistor until such discharge is desired. This transistor also helps isolate a retention capacitor that stores a voltage indicating the desired state of the pixel. Doing so prevents charge leakage and improves reliability.

[0035] Particular implementations of the subject matter described in this disclosure can be implemented to realize one or more of the following potential advantages. Fabricating a latch based on transistors of a single conductivity type can reduce the fabrication process by two or more photo processing steps, which can reduce the complexity of the manufacturing process. The circuits disclosed herein also may yield increased switching speed. Isolation of a data- storing retention capacitor also can reduce charge leakage and increased switching reliability. This results in improved image quality and consistency.

[0036] Figure 1 shows an example latching circuit. The latching circuit is formed from transistors of both conductivity types. The latching circuit of Figure 1 is typically formed from a coupled arrangement of n-type MOS transistors (NMT93 and NMT94) and p-type MOS transistors (PMT 95 and PMT96). The coupled arrangement of transistors is connected between a power line (LVDD), which supplies a uniform voltage VDD, and a power line (LGND), which supplies a ground voltage GND.

[0037] The latching circuit of Figure 1 can be formed from polycrystalline silicon.

[0038] Figure 2 shows an example timing diagram for operation of the latching circuit of Figure 1. The timing diagram depicts a time-sequence of voltages that can be applied to the latching circuit of Figure 1 during operation, including a scanning voltage (cpG) and a driver clock voltage (cpAC). Figure 2 also shows the time variation of the voltages at nodes N91, N92, N93 and N94 in the latching circuit of Figure 1. Voltages VDD and GND are uniform.

[0039] The operation of the latching circuit of Figure 1, when a data voltage at a low level voltage VL (also referred to herein as a L level voltage) is applied on the data line (LD), is as follows.

[0040] As shown in Figure 2, at time tl , the scanning voltage (cpG) on the scanning line (LG) is changed from a L level voltage VL to a high level voltage VH (referred to herein as a H level voltage). The n-type MOS transistor NMT 91 is switched ON, and the L level voltage (VL) on the data line (LD) is captured in a retention capacitor (CD). As a result, node N91 is at an L level voltage VL. [0041] At time t2, the driver clock voltage (cpAC) on the latching control line (LAC) is changed from an L level voltage (VL) to an H level voltage (VH2). As a result, n-type MOS transistor NMT92 is switched ON and node N94 is at the L level voltage (VL).

[0042] This causes the p-type MOS transistor PMT 95 and the n-type MOS transistor NMT 94 to be switched ON, and p-type MOS transistor PMT 96 and n-type MOS transistor NMT 93 to be switched OFF. At this point, node N92, i.e., the second output terminal (OUT 2), is at ground voltage GND, and node N93, i.e., the first output terminal (OUT 1), is at voltage VDD. As a result, the first output terminal (OUT1) is at an H level voltage and the second output terminal (OUT 2) is at an L level voltage.

[0043] The operation of the latching circuit of Figure 1 when a data voltage at an H level voltage VDH is applied on the data line (LD) is as follows.

[0044] As shown in Figure 2, at time t3, the scanning voltage (cpG) on the scanning line (LG) is changed from an L level voltage VL to an H level voltage VH. The n-type MOS transistor NMT 91 is switched on and the data voltage (VDH) on the data line (LD) is stored in retention capacitor (CD). As a result, node N91 is at the H level voltage VH3.

[0045] At this time, the n-type MOS transistor NMT 93 and p-type MOS transistor PMT96 are switched ON, and p-type MOS transistor PMT95 and n-type MOS transistor NMT94 are switched OFF. Node N92, i.e., the second output terminal (OUT2), acquires voltage VDD. Node N93, i.e., the first output terminal (OUT1), acquires ground voltage GND. Therefore, the first output terminal (OUT1) acquires an L level voltage and the second output terminal (OUT2) acquires an H level voltage.

[0046] Figure 3 shows an example pixel circuit that can be used in a display. The pixel circuit can be formed using the latching circuit of Figure 1 and a movable shutter (S). The latching circuit is used to actuate each the movable shutter of a display. The latching circuits facilitate the display of images by the display by electrically actuating, i.e., controlling the position of, a movable shutter (S). The actuation of the movable shutter (S) is based on the voltage differences at the two output terminals of the latching circuits, i.e., the first output terminal (OUT 1) and the second output terminal (OUT 2), of the latching circuit. A movable shutter (S) may be referred to as a mechanical shutter. In an example, the display is a Micro Electro Mechanical Systems (MEMS) display. [0047] In an example implementation, the latching circuit is used to actuate the movable shutter (S) so that it moves rapidly along the direction of the electrostatic forces applied based on the voltages of the output terminals. When node N92 (the second output terminal, OUT2) is at ground level voltage GND, node N93 (the first output terminal, OUT1) is at voltage VDD. Therefore, the movable shutter (S) moves rapidly towards node N93 (the first output terminal, OUT1). When node N92 (the second output terminal, OUT2) is at voltage VDD, node N93 (the first output terminal, OUT1) is at voltage GND. The movable shutter (S) moves rapidly towards node N92 (the second output terminal, OUT2).

[0048] The luminescent state and non-luminescent state of the pixels of a display can be controlled by the opening and closing the movable shutter (S). For example, the display can be a backlight display. When the movable shutter (S) moves towards node N92 (the second output terminal, OUT2), the light rays of the backlight display may be transmitted (thereby causing the pixel to be in a luminescent state). When the movable shutter (S) moves towards node N93 (the second output terminal, OUT1), the light rays of the back lit display are blocked (causing the pixel to be in a non-luminescent state).

[0049] The actuation of the movable shutter (S) facilitates image display by controlling the output of light rays from select pixels (similar to the control of output light rays by a liquid crystal layer in a liquid crystal display unit). As shown in Figure 3, LSS is the control line of the movable shutter (S), and cpS indicates the control signal applied to the movable shutter (S). The control signal (cpS) of the movable shutter (S) can be a specified uniform voltage. The control signal (cpS) also may be pulse voltage, such as in a reverse drive of a liquid crystal display unit.

[0050] Figure 4 shows a schematic of an example display. Multiple pixels (PX) are positioned in a two-dimensional array, with each pixel component (PX) of the array including a movable shutter and a pixel circuit configured to actuate the movable shutter. The pixel circuits of the display can be formed from any of the latching circuits described herein.

[0051] In Figure 4, the rows are sets of the scanning lines (LG) and are connected to a vertical drive circuit (XDR). The columns are sets of the data lines (LD) and are connected to the horizontal drive circuits (YDR). [0052] The power lines (LVDD and LGND), the latching control lines (LAC) and shutter control lines (LSS) are common to all pixels, and are connected to the horizontal drive circuit.

[0053] An image is displayed during the display period after the data voltage on the data line (LD) is written to a given pixel in a given row within the writing period, and the movable shutter is moved towards one of the output terminals of the latching circuit during the movable shutter setting period (i.e., from time point t2 in Figure 2 until the movable shutter is moved completely in a given direction).

[0054] Example of latching circuits that are formed from either only n-type MOS transistors or p-type MOS transistors are described below in connection with Figures 5-19. The latching circuits may be used to form pixel circuits, which can be arranged in an array to provide a display.

[0055] Figure 5 shows an example latching circuit. More particularly, Figure 5 shows an example of a latching circuit that is formed from a single type of transistor. In this example, the transistors are n-type MOS transistors (referred to herein using notation NMT*). For simplicity, the n-type MOS transistors are referred to herein simply as transistors. In an example, the transistors (NMT*) are formed using a polycrystalline silicon semiconductor layer.

[0056] As shown in Figure 5, the latching circuit includes a retention capacitor (CD), a data line (LD), a scanning line (LG), a bias line (LB) to supply a bias voltage (Bias), a first latching control line LAC1 to supply a first driver clock voltage (cpACl), and a second latching control line LAC2 to supply a second driver clock voltage (cpAC2). In an example, the bias voltage can be a fixed, uniform voltage.

[0057] Figure 6 shows an example timing diagram for operation of the latching circuit of Figure 5. For example, Figure 6 shows the time variation of the scanning voltage (cpG), the driver clock voltages (c ACl and cpAC2), and the voltages at nodes Nl, N2, N3 and N4 of the latching circuit of Figure 5.

[0058] A H level voltage or an L level voltage can be applied as the data voltage on the data line (LD). The L level and the H level voltages can correspond to data of either "0" or "1", respectively. [0059] The operation of the example latching circuit of Figure 5 when a data voltage at a L level voltage VL is applied on the data line (LD) is as follows.

[0060] At time tl, the scanning voltage (cpG) is changed from an L level voltage VL to an H level voltage VHl . The scanning line (LG) is coupled to the gate of an input transistor (NMTl). Therefore, the H level voltage VHl switches the input transistor (NMTl) ON and passes on the data voltage VL on the data line (LD) to node Nl . Voltage VHl can be expressed as: VHl > VDH + Vth, where Vth is the threshold voltage of the n-type MOS transistors (NMT*) and VDH is the H level voltage on the data line (LD). For purposes of simplification, all of the n-type MOS transistors are considered to have the same threshold voltage Vth.

[0061] At time t2, the first driver clock voltage (cpACl) is supplied on the first latching control line (LACl) and the second driver clock voltage (cpAC2) is supplied on the second latching control line (LAC2). In the example of Figure 6, the first driver clock voltage (cpACl) and the second driver clock voltage (cpAC2) are supplied simultaneously. Also, in the example of Figure 6, both the first driver clock voltage (cpACl) and the second driver clock voltage (cpAC2) are H level voltages VH2. Each of transistors NMT4 and NMT6 can be a diode-connected transistor coupling node N3 and N4 to the latching control lines LACl and LAC2, respectively. As a result, both nodes N3 and N4 acquire a voltage of VH3 through transistors NMT4 and NMT6. That is, transistors NMT4 and NMT6 serve as pre- charge transistors for the respective nodes N3 and N4. Voltage VH3 can be expressed as: VH3 = VH2 - Vth, where VH2 is the level of the first driver clock voltage (cpACl) and the second driver clock voltage (cpAC2).

[0062] Transistor NMT2 is switched OFF at time t2. Since node N4 is at an H level voltage VH3, transistor NMT3 is switched ON. Node N2 acquires the H level voltage VH4 after transistor NMT3 passes on the voltage from node N3. Voltage VH4 can be expressed as: VH4 = VH3 - Vth.

[0063] At time t3, the first driver clock voltage (cpACl) is changed to the L level voltage VL. Current cannot flow from node N3 to the first latching control line (LACl), since it is against the direction of the diode-connected transistor (NMT4). Also, transistor NMT2 is switched OFF. As a result, the voltages of nodes N2 and N3 do not change. [0064] At time t4, the second driver clock voltage (cpAC2) is changed to an L level voltage VL. Node N2, which is connected to the gate of transistor NMT5, acquires an H level voltage VH4 (VH4 > Vth). As a result, transistor NMT5 is switched ON and Node N4 acquires the L level voltage VL.

[0065] At this time, since the voltage of node N4 acquires the L level voltage VL, transistor NMT3 is switched OFF. The first output terminal (OUT1) of the latching circuit has the H level voltage VH3 of node N3 and the second output terminal (OUT2) has the L level voltage VL of node N4.

[0066] Transistors NMT3 and NMT5 serve as output terminal discharge transistors for the first output terminal (OUT1) and the second output terminal (OUT2), respectively.

Transistor NMT2 serves as a pixel discharge transistor and can be used to control the discharge of both output terminals through the discharge transistors NMT3 and NMT5.

[0067] At time t5, the data voltage on the data line (LD) is changed from the L level voltage VL to the H level voltage VDH. However, the scanning voltage (cpG) at time t5 is an L level voltage and so transistor NMTl is switched OFF. Since the data voltage is not imported from the data line (LD), no further voltage variations occur in nodes Nl, N2, N3 and N4.

[0068] The operation of the example latching circuit of Figure 5 when a data voltage at a H level voltage VDH is applied on the data line (LD) is described below.

[0069] At time t21, scanning voltage (cpG) on the scanning line (LG) is changed to an H level voltage VH1. Input transistor NMTl is switched ON and the voltage of node Nl acquires the data voltage VDH (VDH > Vth). As a result, transistor NMT2 is switched ON and the voltage of node N2 changes to the L level voltage VL.

[0070] Since node (N2) is coupled to the gate of transistor NMT5, transistor NMT5 is switched OFF. Node N4 either remains at the L level voltage or acquires a voltage VL - AVI . Voltage AVI is voltage variation that is imported to node N4 from the coupling capacitance of transistor NMT5 when it changes from the H level voltage VH4 to the L level voltage VL.

[0071] Since transistor NMT3 is switched OFF, node N4 remains at the L level voltage VL (or VL-AVl), and node N3 is maintained at the H level voltage VH3. [0072] The voltage difference between the first output terminal (OUT1) (node N3) and the second output terminal (OUT2) (node N4) is essentially VH3 - VL at time (t21) (i.e., the voltage offset AVI has little to no affect on the actuation of the shutter based on the voltage difference between the output terminals of the latching circuit of Figure 5.

[0073] At time t22, the first driver clock voltage (cpACl) and the second driver clock voltage (cpAC2) are both changed to the H level voltage VH2, the voltage of nodes N3 and N4 acquire voltage VH3 (similar to the voltage at time t2). Since the voltage of node Nl is an H level voltage and transistor NMT2 is switched ON, the voltage of node N2 changes to the H level voltage VH4.

[0074] At time t23, the first driver clock voltage (cpACl) acquires the L level voltage VL. The transistor (NMT2) is switched ON. Since node (N4) is at an H level voltage VH3, transistor (NMT3) is switched ON. Nodes N2 and N3 acquire the L level voltage VL.

[0075] At time t24, the second driver clock voltage (cpAC2) acquires the L level voltage VL. Since the voltage of node (N2) is the L level voltage VL, transistor (NMT5) is switched OFF. Current cannot flow from node (N4) to the second latching control line (LAC2), since it is against the direction of the diode-connected transistor (NMT6). As a result, the voltage of node (N4) does not change from the H level voltage VH3.

[0076] At this point, the first output terminal (OUT1) is at the L level voltage VL of node (N3), and the second output terminal (OUT2) is at the H level voltage VH3 of node (N4).

[0077] At time t25, the voltage on the data line (LD) is changed from the H level voltage VDH to the L level voltage VL. However, the scanning voltage (cpG) is at the L level voltage VL, so input transistor (NMT1) does not switch ON. Therefore, the data voltage is not imported from the data line (LD), and no change occurs in the voltages of nodes (Nl, N2, N3 and N4).

[0078] As described above, the example latching circuit of Figure 5 can be operated as a latch if it is driven as described in connection with Figure 6. That is, the latching circuit of Figure 5 can be used to provide the latching function using transistors of only a single conductivity type (here, n-type MOS transistors). Also, using the timing scheme shown in Figure 6, it is possible to latch information in a comparatively shorter period of time than a latching circuit that is formed using transistors of both conductivity types. [0079] Figure 7 shows an example latching circuit. More particularly, it is a latching circuit that is formed from the latching circuit of Figure 5, and also includes a movable shutter control line (LSS) configured to connect to a shutter (S). The pixel circuit of Figure 7 can be used to actuate the movable shutter (S). An array of pixel circuits of Figure 7 can be used to form a display. The display can display images by electrically actuating the movable shutters (S) associated with each pixel, using the voltage difference between the outputs of the corresponding latching circuit.

[0080] A display that includes a latching circuit described herein can be used to display color images using a field sequential approach. The field sequential display approach is based on a viewer's perception of light emitted by three subpixels. In this example, each pixel circuit described herein can be used to form a subpixel. Each subpixel corresponds to a primary color (Red (R), Green (G), and Blue (B)). In an example, the subpixels can display secondary colors. Each of these subpixels serves as a source of the light of a different color and intensity. Entire fields of a certain primary color, but with intensity varying over the image plane, can be displayed to a viewer sequentially. If the different primary color components of an image are displayed in rapid succession, the viewer's brain merges the primary color components into a single image, thereby forming a single unitary color image having the intended color composition. In an example, a frame of 1/60 Hz can be divided into sub-frames that displays the R, G and B colors (or secondary colors). The intensity of each pixel would be based on the length time a sub-pixel is in a luminescent state.

[0081] The example latching circuit of Figure 5 differs from a CMOS circuit that uses transistors of both conductivity types in that the example of Figure 5 dynamically retains the H level and the L level voltages on the output terminals. The dynamically retained charge can leak in a current of the MOS transistor, even in the OFF state, e.g., if it is held for a long period of time. That may result in unstable actuation of the movable shutter (S) due to voltage variations. Since the pixel circuit of Figure 7 can be configured to periodically reset the movable shutter display, the voltages and retention periods can be controlled.

[0082] An example use of the pixel circuit of Figure 7 in a display is as follows. The movable shutter (S) is moved towards node (N3) or node (N4) during the movable shutter resetting period (TB in Figure 6), after the data voltage is supplied to the data line (LD) for any pixel in any row within the writing period (TA in Figure 6). An image is displayed during the display period (TC in Figure 6). In an example, the resetting of the movable shutter (S) may take longer that shown in Figure 6. For example, the resetting period can be longer in duration than period TB. That is, the switching time for a display period may differ from the time interval between t4 and t5 in Figure 6.

[0083] Figure 8 shows another example latching circuit. It is based on the circuit of Figure 5.

[0084] The latching circuit of Figure 8 is formed from substituting each of the five (5) n- type MOS transistors of Figure 5, namely NMT2, NMT3, NMT4, NMT5 and NMT6, with two (2) transistors that are coupled using a common gate connection. For example, transistor (NMT2) of Figure 5 is substituted with transistor (NMT21) and transistor (NMT22), which are connected with a common gate (and therefore receive the same gate voltage). Transistors NMT3, NMT4, NMT5 and NMT6 of Figure 5 each can be similarly substituted with double transistors coupled with a common gate connection, as shown in Figure 8.

[0085] With the double-gate transistor structure, the latching circuit of Figure 8 can handle higher voltages and can have a higher effective resistance to source-to-drain leakage.

[0086] The example of Figure 8 does not show a double transistor substitution for transistor NMT1. The single transistor NMT1 used in the example of Figure 8 can be is sufficient for passing an H level voltage (VDH) to node (Nl). However, in another example

implementation, input transistor NMT1 may be substituted with a double transistor.

[0087] The latching circuit in the example of Figure 8 shows that all of the transistors NMT2, NMT3, NMT4, NMT5, and NMT6 of Figure 5 can be substituted with double transistors. However, in another example, only one of the transistors NMT2, NMT3, NMT4, NMT5, and NMT6 is substituted with a double transistor. In another example, two or more of the transistors NMT2, NMT3, NMT4, NMT5, and NMT6 can be substituted with double transistors.

[0088] Figure 9 shows another example latching circuit.

[0089] In this example, the bias line (LB) that supplied the bias voltage (Bias) in Figures 5 and 8 is eliminated. The retention capacitor (CD) is connected to the first latching control line instead (as shown Figure 9). [0090] Since the voltage on node (Nl) is now based on the changes in the first driver clock voltage (cpACl), e.g., from an L level voltage VL to an H level voltage VH2, it increases from voltage VL to voltage VDH2 or from voltage VDH to voltage VDH3 according to the following formulae:

VDH2 = VL + (VH2 - VL) x CD/ (CD + CS) (1)

VDH3 = VDH + (VH2 - VL) x CD/ (CD + CS) (2)

[0091] Here, CS represents an increase in capacitance over the retention capacitor (CD) at node (Nl). As described above in connection with Figure 5, transistor (NMT2) functions mainly when the first driver clock voltage (cpACl) acquires an H level voltage and again when the first driver clock voltage (cpACl) is reduced to an L level voltage. That is, the voltage of the first driver clock voltage (cpACl) may go lower than the H level voltage VDH of node (Nl) at about time t3 and time t23 (shown in Figure 6) or later.

[0092] The voltage variation at node (Nl) due to the first driver clock voltage (cpACl) changing from the L level voltage VL to the H level voltage VH2 has little or no effect on the operations of the latching circuit. That is, the latching circuit of the example of Figure 9 exhibits similar latching behavior as any other latching circuit described herein. Eliminating the bias line (LB) can simplify the wiring layout for the circuit, and thereby can reduce the complexity of the fabrication process.

[0093] Figure 10 shows another example latching circuit. It is based on the example of Figure 9.

[0094] In this example, each of the five (5) n-type MOS transistors of Figure 9, namely transistors NMT2, NMT3, NMT4, NMT5 and NMT6, is substituted with two (2) transistors that are coupled using a common gate connection. For example, transistor (NMT2) is substituted with transistor (NMT21) and transistor (NMT22) which share a common gate (and therefore receive the same gate voltage). Transistors NMT3, NMT4, NMT5 and NMT6 of Figure 10 each can be similarly substituted with double transistors connected with a common gate, as shown in Figure 9.

[0095] With the double-gate transistor structure, the latching circuit of Figure 10 can handle higher voltages and has a higher effective resistance to source-to-drain leakage. [0096] The example of Figure 10 does not show a double transistor substitution for transistor NMT1. The single transistor NMT1 used in the example of Figure 8 can be sufficient for passing an H level voltage (VDH) to node (Nl). However, in another example implementation, input transistor NMT1 may be substituted with a double transistor.

[0097] The latching circuit in the example of Figure 10 shows that all of the transistors NMT2, NMT3, NMT4, NMT5 and NMT6 of Figure 5 can be substituted with double transistors. However, in another example, only one of the transistors NMT2, NMT3, NMT4, NMT5 and NMT6 is substituted with a double transistor. In another example, two or more of the transistors NMT2, NMT3, NMT4, NMT5 and NMT6 are substituted with double transistors.

[0098] Figure 11 shows another example latching circuit. Previous examples were based on a differential latching circuit with two (2) reverse outputs (the first output (OUTl) and the second output (OUT2)). The example of Figure 1 1 is based on a different configuration of output terminals.

[0099] Figure 12 shows an example timing diagram for operation of the latching circuit of Figure 11. The example timing diagram of Figure 12 shows the time variation of the scanning voltage (cpG), the first driver clock voltage (cpACl 1), the second driver clock voltage (cpAC 12), and the voltages at nodes N 11 , N 12 and N 13 of Figure 1 1.

[0100] The operation of the example latching circuit of Figure 11 when a data voltage at a L level voltage VL is applied on the data line (LD) is as follows.

[0101] At time tl, the scanning voltage (cpG) on the scanning line (LG) is changed from a L level voltage VL to a H level voltage VH1, input transistor NMT11 is switched ON and the voltage of node (Ni l) acquires the data voltage VL on the data line (LD).

[0102] If node (Ni l) previously was at an H level VDH, the voltage in node (N12) is reduced from VL to VL2 (a shown in Figure 12) due to the gate capacitance of transistor (NMT12). The voltage difference AV2 from VL to VL2 of node (N12) can be expressed using the following formula:

AV2 = (VDH-VL) x Cg / (Cg + CS11) [0103] Here, Cg is gate capacitance of transistor (NMT12), and CS11 is the capacitance of node (Ni l) over gate capacitance Cg.

[0104] There is a similar variation at node (N13). However, the voltage drop in node (N13) can be less. Since node (N13) has a load capability connected to the first output terminal (OUT1), a parasitic capacitance of the diode-connected transistor can be eliminated.

[0105] At time t2, the first driver clock voltage (cpACl 1) on the first latching control line (LAC11) and the second driver clock voltage (cpAC12) on the second latching control line (LAC 12) is changed from a L level voltage VL to a H level voltage VH2.

[0106] As shown in the example of Figure 12, the second driver clock voltage (cpAC12) is increased to an H level voltage before the first driver clock voltage (c ACl 1) starts to drop from an H level voltage at time (tl6). In addition, while Figure 12 shows that the first driver clock voltage (c ACl 1) and the second driver clock voltage (cpAC12) are changed from the L level voltage VL to the H level voltage VH2 substantially simultaneously, it is not required. Any timing structure in which the second driver clock voltage (c AC 12) reaches a H level voltage after the first driver clock voltage (cpACl 1) reaches a H level voltage is applicable. With this timing scheme, a drain avalanche that can occur by the reverse current from node (N12) to the first latching control line (LAC11) is avoided.

[0107] At time t2, the voltage of node (Nl 1) is raised to the H level voltage VDH2 based on the charge on retention capacitor (CD). Here, VDH2 can be represented similarly to formula (1) above.

[0108] Node (N13) acquires a voltage VH3 (VH3 = VH2 - Vth), where the H level voltage VH2 of the first driver clock voltage (c ACl 1) is reduced by the value of the threshold voltage Vth of transistor (NMT14).

[0109] Node (N12) acquires a voltage VH3, where the H level voltage VH2 of the first driver clock voltage (cpACl 1) is reduced by only the threshold value Vth of transistor (NMT14), since the transistor (NMT13) is switched ON.

[0110] At time t3, the first driver clock voltage (cpACl 1) changes from an H level voltage VH2 to an L level voltage VL. The voltage of node (Nl 1) acquires an L level voltage VL and transistor (NMT12) is switched OFF. [0111] Subsequently, the voltage of node (N13) is maintained at an H level voltage VH3. Since the transistor (NMTl 3) is switched ON, node (N12) acquires an L level voltage VL.

[0112] At time t4, the second driver clock voltage (cpAC 12) is changed from an H level voltage VH2 to an L level voltage VL. Node (N12) is maintained at voltage VL since transistor (NMTl) is switched OFF. From time t4 onwards, the first output terminal (OUTl) remains at the H level voltage VH3.

[0113] The operation of the example latching circuit of Figure 11 when a data voltage at a H level VDH is applied on the data line (LD) is described below.

[0114] At time t21, scanning voltage (cpG) on the scanning line (LG) is changed from an L level voltage VL to an H level voltage VH1. Input transistor (NMTl 1) is switched ON and the voltage of node (Ni l) acquires the data voltage VDH.

[0115] The voltage of node (N12) becomes VH42, which is voltage VDH reduced by the threshold voltage Vth of transistor (NMTl 1), based on the infusion of electric charge from node (N13) since transistor (NM12) is switched ON. The voltage of Node (N13) is also reduced by an amount based on this emission. However, this is not shown in Figure 12 due to the high capacitance of node (N13).

[0116] At time t22, the first driver clock voltage (cpACl 1) and the second driver clock voltage (cpAC12) are simultaneously changed to a H level voltage VH2 from a L level voltage VL. As previously mentioned, the first driver clock voltage (cpACl 1) and the second driver clock voltage (cpAC12) need not be raised simultaneously. However, for applicable timing schemes, the second driver clock voltage (cpAC12) reaches an H level voltage after the first driver clock voltage (cpACl 1) is brought to an H level voltage. This can eliminate a drain avalanche that can occur due to a reverse current from node (N12) to the first latching control line (LAC 11).

[0117] At this time, the voltage of node (Nl 1) is changed to an H level VDH3 based on the charge on retention capacitor (CD). Voltage VDH3 can be determined using formula (2) above. [0118] Node (N13) acquires the voltage VH3 (VH3 = CH2 - Vth), which is the H level voltage VH2 of the first driver clock voltage (c ACl 1) reduced by the threshold voltage Vth of transistor (NMT14).

[0119] Node (N12) also acquires the H level voltage VH3, which is the H level voltage VH2 of the first driver clock voltage (c ACl 1) reduced by the threshold voltage Vth of transistor (NMT13) (since transistor (NMT13) is switched ON).

[0120] At time t23, the first driver clock voltage (cpACl 1) is changed from an H level voltage VH2 to an L level voltage VL. Transistor (NMT13) is switched ON. The voltage applied to node (Ni l), and at the gate electrode of transistor (NMT12), changes from VDH3 to VDH, with transistor (NMT12) remaining switched ON. Therefore, node (N13) is connected with the first latching control line (LAC11) through transistor (NMT12) and transistor (NMT13) and acquires an L level voltage VL. Since transistor (NMT13) is switched ON, node (N12) also acquires voltage VL.

[0121] At time t24, the second driver clock voltage (cpAC12) is increased from an H level voltage VH2 to an L level voltage VL. Transistor (NMT13) is switched OFF and nodes (N12 and N13) are maintained at voltage VL.

[0122] From time t24 onwards, the first output terminal (OUT1) remains at the L level voltage VL.

[0123] The latching capability is likewise possible by interchanging the positions of transistor (NMT12) and transistor (NMT13).

[0124] The latching circuit of Figure 11 can be used to form a pixel circuit of a display to actuate a movable shutter by introducing a second output terminal (OUT2) that is directly controlled by a third driver clock voltage (cpAC3) supplied by the third latching lines (LAC 13) (as shown in Figure 11).

[0125] At time tl4, the third driver clock voltage (cpACB) on the third latching control line (LAC 13) is changed from an H level voltage VH4 to an L level voltage VL. At time tl8, the third driver clock voltage (cpAC13) is changed from an L level voltage VL to an H level voltage VH4. Similarly, at time t34, the third driver clock voltage (cpAC13) is changed from an H level voltage VH4 to an L level voltage VL, and, at time t38, changed from an L level voltage VL to an H level voltage VH4.

[0126] The movable shutter (S) is moved towards the first output terminal (OUTl) when the first output terminal (OUTl) acquires the H level voltage VH3 between times tl4 and time tl8. At time tl8, the position of the movable shutter (S) remains unchanged even though the second output terminal (OUT2) acquires to an H level voltage VH4.

[0127] The movable shutter (S) does not move between time t34 and time t38 while the first output terminal (OUTl) is at the L level voltage of VL. At time t34, the movable shutter (S) moves towards the second output terminal (OUT2) when the second output terminal (OUT2) acquires an H level voltage VH4.

[0128] Figure 13 shows an example pixel circuit. The pixel circuit of Figure 13 is based on the latching circuit of Figure 11 and can be used to actuate a movable shutter (S).

[0129] In the example of Figure 11, and as described below in connection with Figures 14, 15 and 16, the bias line may be eliminated, and the retention capacitor (CD) can be connected to the first latching control line (LAC1) instead.

[0130] Figure 14 shows another example latching circuit.

[0131] In this example, each of the three (3) n-type MOS transistors NMT12, NMT13 and NMT14, are substituted with two (2) transistors that are coupled using a common gate connection. For example, transistor (NMT12) of Figure 11 can be substituted with transistor (NMT121) and transistor (NMT122), which are connected with a common gate (and therefore receive the same gate voltage). Either transistor NMT13 or transistor NMT14, or both transistor NMT13 and transistor NMT14, can be similarly substituted with double transistors connected with a common gate, as shown in Figure 14.

[0132] With the double-gate transistor structure, the latching circuit of Figure 14 can handle higher voltages and has a higher effective resistance to source-to-drain leakage.

[0133] The example of Figure 14 does not include a double transistor substitution for transistor NMT11. The single transistor NMT11 used in the example of Figure 14 can be sufficient for passing an H level voltage (VDH) to node (Ni l). In another example, input transistor NMT11 may be substituted with a double transistor. [0134] Figure 15 shows another example latching circuit.

[0135] In this example, transistor (NMT13) and the second latching control line (cpACI2) are eliminated from the latching circuit. The first electrode of transistor (NMT12) is connected to the first latching control line (LACl 1).

[0136] Figure 16 shows an example timing diagram for operation of the latching circuit of Figure 15. The example timing diagram of Figure 16 shows the time variation of the scanning voltage (cpG), the first driver clock voltage (cpACl 1), third driver clock voltage (cpAC13), and the voltages at nodes (Nl 1 and N13).

[0137] In this timing scheme, the latching control line (LACl) supplies a voltage that is maintained at an the intermediate level VH10, except during the interval of time between time tl4 and time tl 8 and the interval of time between time t34 and time t38. During these time intervals, the voltage of the latching control line (LACl) is varied between an H level voltage VH2 and an L level voltage VL.

[0138] That is, as shown in Figure 16, the first driver clock voltage (cpACl 1) changes from an intermediate level voltage VH10 to the H level voltage VH2, from the H level voltage VH2 to the L level voltage VL, and from the L level voltage VL to the intermediate level voltage VH10.

[0139] In this example, the voltage at node (N13) changes from the H level voltage VDH (the data voltage) to H level voltage VDH2 (which is higher in magnitude than VDH-Vth).

[0140] As a result, the latching conditions do not change when a data voltage is applied on the data line (LD), since transistor (NMTI2) is switched OFF even when the voltage of node (Nl 1) is the H level voltage VDH.

[0141] Operation of the latching circuit shown in Figure 15 is described below based on Figure 16.

[0142] First, a data voltage at an L level voltage VL is applied on the data line (LD).

[0143] At time tl, the scanning voltage (cpG) on the scanning line (LG) is changed from the L level voltage VL to the H level voltage VH1. The input transistor (NMT11) is switched ON and the voltage of node (Ni l) acquires the data voltage VL. [0144] At time t2, the first driver clock voltage (cpACl 1) is changed from intermediate level voltage VH10 to the H level voltage VH2. Thus, the voltage of node (Nl 1) also increases, based on the retention capacitor (CD), and is set to the H level voltage VDH2. Voltage VDH2 is computed as previously described.

[0145] Node (N13) acquires the H level voltage VH3, which is the H level voltage VH2 of the first driver clock voltage (cpACl 1) reduced by the threshold voltage of transistor

(NMTI4).

[0146] At time t3, the first driver clock voltage (cpACl 1) is changed from the H level voltage VH2 to the L level voltage VL. The voltage of node (NHl 1) also acquires the L level voltage VL and transistor (NMTl 2) is switched OFF. Consequently, node (N13) maintains the H level voltage VH3.

[0147] At time t4, the first driver clock voltage (cpACl 1) is changed from the L level voltage VL to the intermediate level voltage VH10.

[0148] Similar to the examples of Figures 11 to 14, the output at the first output terminal (OUT1) is an H level voltage VH3 for a data voltage at the L level voltage VL supplied on the data line (LD).

[0149] The operation of the example latching circuit of Figure 15 when a data voltage at a H level voltage VDH is applied on the data line (LD) is as follows.

[0150] At time t21, scanning voltage (cpG) on the scanning line (LG) is changed from the L level voltage VL to the H level voltage VHl . Input transistor (NMTl 1) is switched ON and the voltage of node (Nl 1) is set to H level data voltage VDH.

[0151] Intermediate level voltage VH10 is higher than (VDH-Vth), therefore transistor (NMTl 2) remains switched OFF.

[0152] At time t22, the first driver clock voltage (cpACl 1) changes from the intermediate level voltage VH10 to the H level voltage VH2. The voltage of node (Ni l) increases based on the retention capacitor (CD) and is set to the H level voltage VDH3. Accordingly, transistor (NMTl 2) is switched ON. H level voltage VDH3 is computed as previously described. [0153] Node (N13) acquires H level voltage VH3, which can be computed as the H level voltage VH2 of the first driver clock voltage (c ACl 1) reduced by the threshold voltage of transistor (NMT 14).

[0154] At time t23, the first driver clock voltage (c ACl 1) changes from the H level voltage VH2 to the L level voltage VL. The voltage of node (Nl 1) is decreased from voltage H level voltage VH3 to H level voltage VDH. Since the first driver clock voltage (cpACl 1) has the L level voltage VL, transistor (NMT12) remains ON. Consequently, node (N13) is set to the L level voltage VL.

[0155] At time t24, the first driver clock voltage (cpACl 1) on the first latching control line (LAC11) changes from the L level voltage VL to intermediate level voltage VH10, and transistor (NMT 12) is switched ON.

[0156] Intermediate level voltage VH10 is greater than (VL + Vth). Consequently, at time t24, the voltage of node (N13) increases through transistor (NMT 14) and reaches (VH10- Vth). If voltage VH4 of the second output terminal (OUT2) at that time is changed to an H level voltage, the voltage can be set in such a way that voltage (VH10- Vth) of the first output terminal (OUT1) is an L level voltage. For example, if the latching circuit of this example is used in a display to actuate a movable shutter, the intermediate level voltage VH10 can be set so that the threshold voltage for actuation of the movable shutter (S) is higher than (VH10- Vth).

[0157] From time t24 onwards, the first output terminal (OUT1) has voltage level (VH10- Vth).

[0158] Figure 17 shows another example latching circuit.

[0159] The latching circuit of Figure 17 is formed from substituting each of the two (2) n- type MOS transistors of Figure 15, namely NMT12 and NMT14, with two (2) transistors that are coupled using a common gate connection. For example, transistor (NMT 12) of Figure 15 is substituted with transistor (NMT 121) and transistor (NMT 122), which are connected with a common gate (and therefore receive the same gate voltage). Transistor NMT 14 of Figure 15 can be similarly substituted with double transistors connected with a common gate, as shown in Figure 17. [0160] With the double-gate transistor structure, the latching circuit of Figure 17 can handle higher voltages and has a higher effective resistance to source-to-drain leakage.

[0161] Although a single input transistor (NMT11) is shown in Figure 17, it can be substituted with a double gate transistor structure..

[0162] While the example latching circuits of Figures 5 through 17 are shown based on use of n-type MOS transistors, solely p-type MOS transistors also can be used to form a latching circuit.

[0163] Figure 18 shows an example latching circuit formed with p-type MOS transistors. Figure 19 shows an example timing diagram for operation of the latching circuit of Figure 18. The example timing diagram of Figure 19 shows the time variation of the scanning voltage (cpG), each driver clock voltage (cpACl and cpAC2), and the voltages of each node (Nl, N2, N3 and N4) of Figure 18.

[0164] The latching circuit in this implementation is constructed with p-type MOS transistor. Therefore, transistor (PMT2) cannot be switched OFF even if the voltage of node (Nl) is lower than an H level voltage from the first driver clock voltage (cpACl).

Consequently, an H level voltage (VDH) on the data line (LD) should be more than the H level voltage (VH2) of the first driver clock voltage (φ AC1). For example, VDH can be set equal to VH2.

[0165] A L level voltage on the data line (LD) should be lower than the threshold voltage Vth of p-type MOS transistor of this implementation. Accordingly, an L level voltage on the data line (LD), the Bias voltage shown in Figure 19, and VL (i.e., the L level voltage of the first driver clock voltage (φ AC1)) may not necessarily be equal. In connection with the examples of Figures 18 and 19, an L level voltage on the data line (LD) is represented by notation VDL. The H level voltage (VH1) of scanning voltage (cpG) on the scanning line (LG) should be higher than the H level voltage (VH2) of the first driver clock voltage (cpACl). For example, VH1 can be equal to VH2.

[0166] In this example implementation, the L level Voltage VL3 of scanning voltage (cpG) on the scanning line (LG) can be set to less that the L level voltage VDL on data line (LD) reduced by the threshold voltage Vth. Accordingly, the L level on the data line (LD), the bias voltage shown in Figure 19, and VL (the L level voltage of the first driver clock voltage (cpACl)) need not be equal. The L level voltage on the data line (LD) can be greater than VL. In this example implementation, the voltages can have the following relationship: VL≤ VL3 < VDL - Vth.

[0167] The operation of the example latching circuit of Figure 18 when a data voltage at a H level voltage VDH is applied on the data line (LD) is as follows.

[0168] At time tl, scanning voltage (cpG) on the scanning line (LG) is changed from the H level voltage VH1 to the L level voltage VL3. Input transistor (PMT1) is switched ON and node (Nl) is set to the data voltage VDH.

[0169] At time t2, the first driver clock voltage (cpACl) on the first latching control line (LAC1) and the second driver clock voltage (cpAC2) on the second latching control line (LAC2) are set to the L level voltage VL. Nodes (N3 and N4) acquire the L level voltage VLl through transistors (PMT4 and PMT6), respectively. Each of transistors (PMT4 and PMT6) serves as a pre-charge transistor for the corresponding output terminal. Also, each of transistors (PMT4 and PMT6) can be a diode-connected transistor. Here, VLl = VL + Vth.

[0170] At this time, transistor (PMT2) is switched OFF. Transistor (PMT3) is switched ON since node (N4) acquires the L level voltage VLl . Accordingly, node (N2) acquires the L level voltage VL2. Here, VL2 = VLl + Vth.

[0171] At time t3, the first driver clock voltage (cpACl) is set to the H level voltage VH2. Transistor (PMT3) remains switched ON and transistor (PMT2) remains switched OFF.

Since transistor (PMT4) is a diode-connected transistor, current does not flow from the first latching control line (LAC1) to node (N3). Accordingly, the L level voltage VLl is maintained on node (N3).

[0172] At time t4, the second driver clock voltage (cpAC2) is set to the H level voltage VH2. As the voltage of node (N2) is the L level VL2, transistor (PMT5) is switched ON. As transistor (PMT6) is a diode-connected transistor, current does not flow from the second latching control line (LAC2) to node (N4). Accordingly, the H level voltage VH2 is maintained on node (N4). Therefore, transistor (PMT3) is switched OFF. Consequently, node (N3) is set at the L level voltage VLl (the first output terminal (OUTl)) and node (N4) is set at the H level voltage VH2 (the second output terminal (OUT2)). [0173] The operation of the example latching circuit of Figure 18 when a data voltage at a L level voltage VDL is applied on the data line (LD) is as follows.

[0174] At time t21, scanning voltage (cpG) on the scanning line (LG) is changed to the L level voltage VL3. Input transistor (PMT1) is switched ON and node (Nl) is set to voltage VDL. Here, VDL < Vth, transistor (PMT2) is switched ON and voltage of node (N2) is changed to the H level voltage VH2.

[0175] As a result, transistor (PMT5) is switched OFF. The voltage of node (N4) remains H level voltage VH2, or becomes VH2 + AV3. Voltage AV3 is the voltage variance that is imported to node (N4) from the coupling capacitance of transistor (PMT5) at the time it changes to the H level voltage VH2 from the L level voltage VL2.

[0176] Since node (N4) is at the H level voltage VH2 (or VH2 + AV3), the transistor (PMT3) is switched OFF and node (N3) is maintained at the L level voltage VLl .

[0177] At time t22, the first driver clock voltage (cpACl) and the second driver clock voltage (cpAC2) are set to the L level voltage VL at substantially the same time. Similarly as at time t2, the voltage of nodes (N3 and N4) are set to the L level voltage VLl; the voltage of node (N2) is set to the L level voltage VL2.

[0178] At time t23, the first driver clock voltage (cpACl) is set to the H level voltage VH2. At that time, since the voltage of node (Nl) is not changed to the L level voltage VDL, transistor (PMT2) remains switched ON. Also, since the voltage of node (N4) is not changed to the L level voltage VLl, transistor (PMT3) also remains switched ON. Accordingly, nodes (N2 and N3) are set to the H level voltage VH2.

[0179] At time t24, the second driver clock voltage (cpAC2) is set to the H level voltage VH2. At that time, the voltage of node (N2) remains at the H level voltage VH2. Therefore, transistor (PMT5) remains switched OFF. Since transistor (PMT6) is s diode-connected transistor, current does not flow from the second latching control line (LAC2) to node (N4). Accordingly, node (N4) remains at the L level voltage VLl .

[0180] Consequently, the first output terminal (OUT1) is set at the H level voltage VH2 (of node (N3)) and the second output terminal (OUT2) is set at the L level voltage VLl (of node (N4)). [0181] In an example, a pixel circuit can be formed based on the latching circuit of Figure 18 and a movable shutter control line (LSS) configured to connect to a shutter (S). Such a pixel circuit can be used to actuate a movable shutter (S). An arrangement (e.g., two- dimensional array) of these pixel circuits can be used to form a display. The display can display images by electrically actuating the movable shutters (S) associated with each pixel, using the voltage difference between the outputs of the latching circuit of Figure 18.

[0182] Definition of Terms

NMT* n type MOS transistor

PMT* p type MOS transistor

CD retention capacitor

LD the data line

LG the scanning line

LB the bias line

LAC* the latching control lines

LDVV, LGND power lines

LSS the movable shutter control line

S the movable shutter

N* Node

XDR Vertical drive circuit

YDR Horizontal drive circuit

[0183] The disclosure described latching circuits of various pixel circuits for actuating a movable shutter of a display. However, the latching circuits described herein are applicable to any similar operation that can be applied in displays other than a pixel circuit for actuating a movable shutter. In addition, various changes can be made to the systems, apparatus and methods described herein without departing from the scope of this disclosure.