Title:
LATENCY TOLERANT PROCESSING EQUIPMENT
Document Type and Number:
WIPO Patent Application WO2003044688
Kind Code:
A3
Abstract:
A processing architecture for performing a plurality of tasks comprises a conveyor of pipe stages, having a certain width comprising different fields including commands and operands, and a clock signal; wherein each pipe stage performs a certain part of an operation for each task of the plurality in a respective time slot. The processing architecture is also implemented in random access memory and dynamic random access memory devices. The present invention provides processing of data such that latency of memory and communication channels does not reduce the performance of the processor.
Inventors:
ABROSIMOV IGOR ANATOLIEVICH (RU)
DEAS ALEXANDER ROGER
DEAS ALEXANDER ROGER
Application Number:
PCT/IB2002/004814
Publication Date:
July 22, 2004
Filing Date:
November 18, 2002
Export Citation:
Assignee:
ABROSIMOV IGOR ANATOLIEVICH (RU)
International Classes:
G06F15/78; (IPC1-7): G11C7/10; G06F9/38
Other References:
LAUDON J ET AL: "INTERLEAVING: A MULTITHREADING TECHNIQUE TARGETING MULTIPROCESSORS AND WORKSTATIONS", ACM SIGPLAN NOTICES, ASSOCIATION FOR COMPUTING MACHINERY, NEW YORK, US, vol. 29, no. 11, 1 November 1994 (1994-11-01), pages 308 - 318, XP000491743, ISSN: 0362-1340
J.L. HENNESSY AND D.A. PATTERSON: "Computer Architecture A Quantitative Approach", MORGAN KAUFMANN, SAN MATEO - CALIFORNIA, XP002274189
DUBEY P K ET AL: "OPTIMAL PIPELINING", JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, ACADEMIC PRESS, DULUTH, MN, US, vol. 8, no. 1, 1990, pages 10 - 19, XP000103320, ISSN: 0743-7315
SURESH P ET AL: "PERL-a registerless architecture", HIGH PERFORMANCE COMPUTING, 1998. HIPC '98. 5TH INTERNATIONAL CONFERENCE ON MADRAS, INDIA 17-20 DEC. 1998, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 17 December 1998 (1998-12-17), pages 33 - 40, XP010317631, ISBN: 0-8186-9194-8
SCHMITT-LANDSIEDEL D ET AL: "PIPELINE ARCHITECTURE FOR FAST CMOS BUFFER RAM'S", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE INC. NEW YORK, US, vol. 25, no. 3, 1 June 1990 (1990-06-01), pages 741 - 746, XP000140206, ISSN: 0018-9200
JEONG G J ET AL: "DESIGN OF A SCALABLE PIPELINED RAM SYSTEM", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE INC. NEW YORK, US, vol. 33, no. 6, June 1998 (1998-06-01), pages 910 - 914, XP000833670, ISSN: 0018-9200
J.L. HENNESSY AND D.A. PATTERSON: "Computer Architecture A Quantitative Approach", MORGAN KAUFMANN, SAN MATEO - CALIFORNIA, XP002274189
DUBEY P K ET AL: "OPTIMAL PIPELINING", JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, ACADEMIC PRESS, DULUTH, MN, US, vol. 8, no. 1, 1990, pages 10 - 19, XP000103320, ISSN: 0743-7315
SURESH P ET AL: "PERL-a registerless architecture", HIGH PERFORMANCE COMPUTING, 1998. HIPC '98. 5TH INTERNATIONAL CONFERENCE ON MADRAS, INDIA 17-20 DEC. 1998, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 17 December 1998 (1998-12-17), pages 33 - 40, XP010317631, ISBN: 0-8186-9194-8
SCHMITT-LANDSIEDEL D ET AL: "PIPELINE ARCHITECTURE FOR FAST CMOS BUFFER RAM'S", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE INC. NEW YORK, US, vol. 25, no. 3, 1 June 1990 (1990-06-01), pages 741 - 746, XP000140206, ISSN: 0018-9200
JEONG G J ET AL: "DESIGN OF A SCALABLE PIPELINED RAM SYSTEM", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE INC. NEW YORK, US, vol. 33, no. 6, June 1998 (1998-06-01), pages 910 - 914, XP000833670, ISSN: 0018-9200
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