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Title:
LATERAL POWER TRANSISTOR COMPRISING FILLED VERTICAL NANO- OR MICRO-HOLES AND MANUFACTURE THEREOF
Document Type and Number:
WIPO Patent Application WO/2018/109452
Kind Code:
A1
Abstract:
A lateral power transistor formed in a portion of a semiconductor wafer, wherein through-holes of micro- or nanoscale size extend through the wafer, to provide the location of doped regions that extend from and around the through-holes throughout the thickness of the wafer and form terminal regions (12, 14) of the transistor, and lateral conduction paths (16) between said regions. Devices according to the invention are not restricted in volume by the usual depth limitation of conventional lateral and vertical power devices related to diffusion depth and breakdown voltage respectively. The invention is useful for BJT or JFET constructions and for one or more power transistor on a single monolithic construction.

Inventors:
WOOD JOHN (GB)
Application Number:
PCT/GB2017/053713
Publication Date:
June 21, 2018
Filing Date:
December 12, 2017
Export Citation:
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Assignee:
WOOD JOHN (GB)
International Classes:
H01L29/66; H01L29/06; H01L29/08; H01L29/10; H01L29/735; H01L29/808
Domestic Patent References:
WO2014122472A12014-08-14
Foreign References:
GB2546475A2017-07-26
EP3029735A12016-06-08
US20130075741A12013-03-28
US20050093097A12005-05-05
EP1039548A22000-09-27
US20020063259A12002-05-30
US20170287721A12017-10-05
US3044909A1962-07-17
US4754310A1988-06-28
Other References:
DIDAC VEGA: "Macroporous Silicon FET Transistors for Power Applications", SPANISH CONFERENCE ON ELECTRON DEVICES (CDE), 2013
RODRIGUEZ ET AL.: "Novel Electronic Devices in Macroporous Silicon: Design of FET Transistors for Power Applications", IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 58, no. 9, 2011, XP011381335, DOI: doi:10.1109/TED.2011.2159508
G.-F. DALLA BETTA ET AL.: "Development of modified 3D detectors at FBK", IEEE NUCL. SCI. CONF. R. (NSS/MIC, 2010, pages 382, XP031945139, DOI: doi:10.1109/NSSMIC.2010.5873785
Z. HUANG ET AL.: "Metal-assisted chemical etching of silicon: a review", ADV. MATER., vol. 23, 2011, pages 285 - 308, XP002735507, DOI: doi:10.1002/adma.201001784
G. GAUTIER: "Deep trench etching combining aluminum thermomigration and electrochemical silicon dissolution", APPL. PHYS. LETT., vol. 88, 2006, pages 212501, XP012081831, DOI: doi:10.1063/1.2206120
KIYOTA ET AL.: "Rapid Vapor-Phase Direct Doping; Ultra-Shallow Junction Formation Method for High-Speed Bipolar and Highly-Integrated DRAM LSIs", EXTENDED ABSTRACTS OF THE 1991 INTERNATIONAL CONFERENCE ON SOLID STATE DEVICES AND MATERIALS, vol. 199L, 1991, pages 47 - 49, XP000279414
Attorney, Agent or Firm:
HANSON, William (GB)
Download PDF:
Claims:
CLAIMS

1. A lateral power transistor formed in a portion of a semiconductor wafer, wherein through-holes of micro- or nanoscale size extend through the wafer, to provide the location of doped regions that extend from and around the through-holes throughout the thickness of the wafer and form terminal regions of the transistor, and lateral conduction paths between said regions.

2. A transistor according to claim 1, wherein at least one bounding doped region is provided to form a high voltage lateral drift region.

3. A transistor according to claim 1 or 2, wherein the semiconductor wafer is of silicon.

4. A transistor according to claim 1, 2 or 3, being a single-sided-single-base-device, a double-sided-single-base-device, a single-sided-double-base-device, or a double-sided- double-base-device.

5. A transistor according to any preceding claim which is a bipolar junction transistor, or a junction field effect transistor.

6. A transistor according to any preceding claim, wherein the terminal regions comprise concentric rings.

7. A transistor according to any preceding claim, having an edge termination in the form of an etched grove or a coating.

8. A transistor according to any preceding claim, wherein the holes are filled with electrically conducting material.

9. A transistor according to any preceding claim, wherein additional through-holes are provided in an array aligned with a drift region of the transistor to provide a doped region that balances the charge in a surrounding doped region of opposite conductive type.

10. An assembly comprising a set of lateral power transistors each according to any preceding claim, formed in a single semiconductor wafer, the wafer having bounding doped regions allowing a high voltage between the transistors.

11. An assembly according to claim 10, wherein the transistors in the set are doped differently to give different minority carrier lifetimes.

12. An assembly according to claim 11, wherein at least one, but not all, of the transistors has a shallow-doped collector-emitter region.

13. An assembly according to claim 11, wherein at least one, but not all, of the transistors is doped with gold or platinum.

14. A method of forming a lateral power transistor, comprising taking a semiconductor wafer, forming a plurality of through-holes of nano-scale or micro-scale size through the wafer and doping the wafer using the holes to create doped regions that extend from and around the through-holes throughout the thickness of the wafer and form terminal regions of the transistor, and lateral conduction paths between said regions.

15. A method according to claim 14, wherein forming the holes comprises etching, such as wet chemical etching, in particular metal assisted chemical etching, or deep reactive-ion etching.

16. A method according to claim 14, wherein forming the holes comprises laser photoablation.

17. A method according to claim 14, 15 or 16, wherein the holes are filled with conductive material, using a through silicon via process.

18. A method according to claim 14, 15 or 16, wherein the holes may be plated with conductive material using an atomic layer deposition process.

Description:
LATERAL POWER TRANSISTOR COMPRISING FILLED VERTICAL NANO- OR MICRO-HOLES AND

MANUFACTURE THEREOF

Background to the Invention

[01] This invention relates to a method of making a transistor and to a transistor so made.

[02] My international application WO 2014/122472 describes a base region of a first conductivity type, wherein said base region constitutes a drift region of said structure; first and second collector/emitter (CE) regions, each of a second conductivity type adjacent opposite ends of the base region; wherein the base region is lightly doped relative to said collector/emitter regions. The structure further comprises a base connection to the base region, the base connection being within or adjacent to said first collector/ emitter region. This document is incorporated herein by reference.

[03] My co-pending US application US-A-2017/ 287721 describes a method of etching an N-type silicon substrate or a substrate having a silicon surface, the method comprising: placing the substrate in a container, providing a volume of an acid solution in the container, wherein the acid solution serves as an insulator; drilling, using one or more needles supplied with a voltage, one or more holes on the surface of the substrate to locally invert the N-type substrate to a P-type substrate, wherein the voltage applied on the surface of the substrate anodically etches the surface of the substrate to create the one or more holes by surface inversion. This document is also incorporated herein by reference.

[04] High voltage, high power, transistors generally use vertical conduction paths and special "thin wafer" processing to improve the specific on-resistance of the switch. A typical example is shown in Figure 1.

[05] Lateral power devices, of which many structures are well known, are generally considered to have inferior specific on-resistance because of the reduced conductive volume available to the lateral path which is ordinarily confined close to the wafer surface. See Figure 2.

[06] Previously there have been proposals to use through-silicon holes as the basis for forming doped transistor structures. E.g. US-A-3044909 describes a bar of silicon with included grain boundaries which allow for through-silicon etching, then doping to form the base of a PNP or NPN transistor by having the diffisions link up between the doped holes. See Figures 3 and 4. [07] Didac Vega, "Macroporous Silicon FET Transistors for Power Applications" Spanish Conference on Electron Devices (CDE), 2013 and Rodriguez et al, "Novel Electronic Devices in Macroporous Silicon: Design of FET Transistors for Power Applications", IEEE Transactions on Electron Devices (Volume: 58 , Issue: 9 ) 2011, show ideas for lateral through-wafer conduction paths. See Figure 5.

[08] These prior art ideas are deficient when it comes to building a high voltage, high current transistor because:

a. there are no methods given of forming multiple paralleled devices to make large area structures

b. the structures shown have a single bar of silicon with just two end-plates for connection to the power terminals.

[09] The horizontal devices described by Didac Vega and Rodriguez, supra, do not create a valid high voltage structure, as each pore becomes a gate and these gates are distributed evenly through the drift region causing voltage breakdown to the gate at the drain side. Current flows around the pores for JFET operation instead of the pores just acting as dopant sources. Also all of the horizontal FETs are effectively in series which results in an unworkably high on-resistance and the use of macroporous silicon severely limits the possible patterns of through-hole structures which can be formed without etch degeneration.

[10] In addition, none of the known structures show a method of implementing a charge compensation (superjunction) structure.

Summary of the Invention

[11] It is an aim of the invention to provide a new structure with lateral conduction paths of much higher conductive volume than even a typical vertical device.

[12] The invention provides a lateral power transistor formed in a portion of a semiconductor wafer, wherein through-holes of micro- or nanoscale size extend through the wafer, to provide the location of doped regions that extend from and around the through- holes throughout the thickness of the wafer and form terminal regions of the transistor, and lateral conduction paths between said regions.

[13] A through-hole of micro- or nanoscale size, also called a micro- or nanohole herein, means a hole having a diameter or (if other than circular) a largest cross-sectional dimension, of from 1 nm to 100 μιη. [14] At least one bounding doped region may be provided to form a high voltage lateral drift region.

[15] The semiconductor may be of silicon.

[16] The transistor may be a single-sided-single-base-device, a double-sided-single-base- device, a single-sided-double-base-device, or a double-sided-double-base-device.

[17] The transistor may be a bipolar junction transistor, or it may be a junction field effect transistor.

[18] The terminal regions may comprise concentric rings.

[19] The transistor may have an edge termination in the form of an etched grove or a coating.

[20] The holes may be filled with electrically conducting material.

[21] Additional through-holes may be provided in an array aligned with a drift region of the transistor to provide a doped region that balances the charge in a surrounding doped region of opposite conductive type, to provide a superjunction mechanism where the net doping of the drift region is substantially higher than the normal maximum doping for a given breakdown voltage.

[22] The invention also provides an assembly comprising a set of lateral power transistors each as set out above and bounding doped regions allowing a high voltage between the transistors.

[23] In embodiments of the invention, the transistors in the set are doped differently to give different minority carrier lifetimes. In one such embodiment, at least one, but not all, of the transistors has a shallow-doped collector-emitter region. In another such embodiment, at least one, but not all, of the transistors is doped with gold or platinum.

[24] The invention also provides a method of forming a lateral power transistor, comprising taking a semiconductor wafer, forming a plurality of through-holes of nano- scale or micro-scale size through the wafer and doping the wafer using the holes to create doped regions that extend from and around the through-holes throughout the thickness of the wafer and form terminal regions of the transistor, and lateral conduction paths between said regions.

[25] Forming the holes may comprise etching, such as wet chemical etching, in particular metal assisted chemical etching. Alternatively the holes may be formed by deep reactive-ion etching, or by laser photoablation. [26] The holes may be filled with conductive material, using a through silicon via process. Alternatively the holes may be plated with conductive material using an atomic layer deposition process.

[27] Advantageously, any unidirectional or bidirectional devices formed according to the invention do not need double-sided processing or double-sided base connections. A further advantage comes from the fact that these new devices are fabricated on ordinary full- thickness silicon wafer processing equipment - no "thin wafer" handling is needed.

Brief Description of the Drawings

[28] Embodiments of the invention will now be described in more detail, by way of example only, with reference to the accompanying drawings, in which:

[29] Figure 1 shows a known vertical power transistor;

[30] Figure 2 shows a known lateral power transistor;

[31] Figure 3 is shows a known through-etched transistor;

[32] Figure 4 shows a further known through-etched transistor;

[33] Figure 5 is a schematic cut-away view of a known lateral FET;

[34] Figure 6 schematically shows power transistors according to the principle of the present invention;

[35] Figure 7 shows a Single-Sided-Double-Base-Device (SSDBD) transistor;

[36] Figure 8 is a cross-section of the SSDBD transistor;

[37] Figure 9 shows a Single-Sided-Single-Base-Device (SSSBD);

[38] Figure 10 shows a dual driver chip attached to the SSSBD;

[39] Figure 11 shows multiple independent transistors and drivers on the same die;

[40] Figure 12 shows a circuit diagram and a timing diagram for a dual-lifetime transistor arrangement;

[41] Figure 13 shows an etching process;

[42] Figure 14 shows examples of applications for transistors of the invention, and the structure of a JFET;

[43] Figure 15 shows a simulation result for a device according to the invention;

[44] Figure 16 shows a machine for the etching process;

[45] Figure 17 shows etching patterns;

[46] Figures 18, 19 and 20 show circuits incorporating devices according to the invention;

[47] Figure 21 schematically shows a switch according to the invention, and the symbol, a test circuit, and an example of an implementation circuit for the switch; [48] Figure 22 shows a full bridge base driver using devices of the invention;

[49] Figure 23 shows interleaved transformers;

[50] Figure 24 shows a transformer drive circuit including devices according to the invention;

[51] Figure 25 shows the determination of the adiabatic operating point for the circuit of Figure 24;

[52] Figures 26 and 27 show tapped, stacked bridge circuits of the invention;

[53] Figure 28 shows a circuit and a communications protocol for interfacing a transistor of the invention with a controller device;

[54] Figure 29 shows a multi-chip implementation of the components of Figure 28;

[55] Figure 30 shows possible structures and circuits for a superjunction device according to the invention;

[56] Figure 31 is a graph of superjunction on-resistance;

[57] Figure 32 shows a JFET cascode structure and an equivalent circuit;

[58] Figure 33 shows adiabatic circuits including devices according to the invention;

[59] Figure 34 shows wafers with devices on both sides;

[60] Figure 35 shows capacitor structures according to the inventions and applications for such devices;

[61] Figure 36 shows single-transistor resonant converter circuits including devices according to the invention;

[62] Figure 37 show simulated operating characteristics of a transistor according to the invention;

[63] Figure 38 shows steps in the formation of a transistor according to the invention;

[64] Figure 39 shows further adiabatic circuits including devices according to the invention;

[65] Figure 40 shows a power factor controller circuit including devices according to the invention;

[66] Figure 41 shows a ring oscuillator circuit including devices according to the invention;

[67] Figure 42 shows equipment for etching devices according to the invention;

[68] Figure 43 shows transformer-coupled multimode driver circuits including devices according to the invention;

[69] Figure 44 shows further details of one of the circuits of Figure 43; [70] Figure 45 shows a single- or double-sided-double-base-device according to the invention;

[71] Figure 46 shows the circuit, structure and output voltage of a an active full bridge including devices according to the invention;

[72] Figure 47 shows details of the circuit of Figure 46;

[73] Figure 48 shows structure and packaging for the circuit of Figure 46;

[74] Figure 49 shows a buck-boost converter circuit including devices according to the invention;

[75] Figure 50 shows the operation of power-factor-controller boost systems including devices according to the invention;

[76] Figure 51 shows the structure of a smart-power system of an integrated driver IC including devices according to the invention;

[77] Figure 52 shows a circuit usable with the circuit of Figure 51;

[78] Figures 53 and 54 show methods of making transistor structures according to the invention to use with the adiabatic power converters;

[79] Figure 55 schematically shows a universal power converter including devices according to the invention;

[80] Figure 56 shows details of the circuit of Figure 55;

[81] Figure 57 shows a desired operating waveform for a transformer driven by the circuit of Figure 55; and

[82] Figure 58 shows undesired operating waveforms for a transformer driven by the circuit of Figure 55.

Detailed Description of Preferred Embodiments

[83] NPN type power structures will be described herein, but PNP structures are also possible by reversing the doping systems. Where reference is made to diffusion, ion implantation and other doping methods are also options. Silicon is mentioned as the most obvious semiconductor to use other materials including silicon carbide are also practical.

[84] Figure 6 is a simplified view of power transistors according to the invention. Doped regions 2, 4, 6 are formed with a diffusion depth sufficient to form continuously doped columns at a depth in the order of 325 μηι. The doping is accomplished by means of through-holes 8, which are formed in these regions by metal-assisted chemical etching (MacEtching) to form micro- or nano-tubes. The regions 2 form drains, the regions 4 form gates and the regions 6 form sources. The arrows show conduction paths which can be 50 μη long for an applied voltage of 600 V. The drawing shows only part of a fabricated die, and the total conductive cross-sectional area can be 5 cm 2 .

[85] Such devices achieve a fivefold to tenfold reduction in conduction losses as compared with the known devices. Thus a die can be made one fifth of the size of that of the known device with a commensurate cost saving.

[86] Multiple devices can be fabricated on the same die. For example a full bridge of four power transistors can be isolated using through-wafer junction-isolation. Neither wafer- thinning nor thin-wafer processing equipment are required. The voltage rating of the device is set lithographically, independent of the wafer thickness. Also, single-sided connection is possible for flip-die mounting.

[87] Figure 7a is a top view of a Single-Sided-Double-Base-Device (SSDBD) transistor created according to the invention. This shows a P-type silicon wafer 10. Concentric rings of doped silicon extend through, or at least partly through, the thickness of the wafer. These comprise pairs of N+ rings 12, for forming collector-emitters with P+ rings 14, forming bases, between the rings of each P-type pair. The rings have the MacEtched holes. Alternatively, deep reactive-ion etching (DRIE) can be used to form differently shaped holes shown on the left hand side of Figure 7a. The high resistivity P-type wafer can create voltage-sustaining, current-conducting, drift regions between these rings.

[88] Figure 7b shows a schematic or test circuit for the transistor fabricated as shown in Figure 7a.

[89] Shapes other than concentric rings can be used to form the transistors, such as meanders, spirals etc. In particular, Figure 7c shows stripes that can increase the parallel current capacity of the complete switch when connected together.

[90] Masking with thermal S1O2 grown inside the vertical holes and selective removal permits multiple independent doping operations on different groups of the vertical electrode. Another option is to use liquid doping (similar to spin-on-dopant) with pre- masking for multiple dopings, relying on capillary action for the dopant to run into the micro / nano holes and with a subsequent single furnace step to simultaneously perform all the different drive-ins.

[91] Figure 8 shows the vertical cross-section structure of the same SSDBD transistor. The concentric pairs 12 of N+ rings of material which extend part-way or entirely through the wafer thickness are alternately labelled CE1, CE2. Inserted inside these CE regions are the P+ regions 14 which extend part-way or entirely through the wafer thickness forming BASE1, BASE2.

[92] There exists a conductivity-modulated path from CE1 12 through the drift region 16to CE2 12 controlled by BASE1 and BASE2 14. The device is structurally different but functionally equivalent to the that shown in Figure 1A of WO 2014/122472, and can be controlled in the same way - optimally using the "high-side" BASE (or C-BASE) to turn the device on and emitter-switched turn off.

[93] A key fabrication step for the device of the invention is the production of small diameter (or small cross section for non-round) holes with large depth and high aspect ratio as can be produced using known DRIE etching (e.g. the Bosch process), laser drilling and also other techniques known to the practitioners of TVS (Through-Silicon-Via) methods amongst others. Note that although circular holes are shown, any shape can be produced using DRIE etching and the shape can be optimised to position the dopants where required for optimum performance, as mentioned above with respect to Figure 7a. Plain, undoped holes can change the flow of currents and electric fields around the BASE region.

[94] A typical Bosch process DRIE etch machine such as the PlasmaPro ® 100 Estrelas Deep Silicon Etch System (Oxford Instruments) can attain etch rates up to 25μηι/ min and an aspect ratio up to 70:1.

[95] The DRIE or otherwise etched holes can act as diffusion surfaces, whereby for example a phosphorus or boron dopant can be diffused (or implanted) from the holes outwards into the lateral direction of the silicon, possibly using low temperature plasma immersion implant or furnace dopant processing. An alternative method of doping is to use selective epitaxy to create a doped silicon lining e.g. using the Centura ® Epi reactor (Applied Materials). Subsequent furnace drive-in can be used to diffuse the dopants if desired.

[96] A lateral device must still have the equivalent of high voltage 'edge termination' of the drift region 16 to support the applied voltage without premature breakdown and one solution is shown in Figure 8. This involves structuring the surface of both sides with a field- shaping V-groove 18 which is effectively a lateral version of the technique shown previously WO 2014/122472 for vertical devices. A known method is to use KOH alkali isotropic etch to form the V.

[97] Asymmetrical devices could benefit from a single ramp shape profile rather than the V-shape needed for bidirectional blocking voltage sustaining. Other options are an ion- implanted termination 20, a semi-insulating polycrystalline silicon (SIPOS) coating 22 to impose a voltage gradient along the outside of the drift region 16 or finally good results have been achieved using AI2O3 atomic layer deposition (ALD) coatings to terminate the edges of P-type wafers used for high voltage photodectors (G.-F. Dalla Betta et al., "Development of modified 3D detectors at FBK", IEEE Nucl. Sci. Conf. R. (NSS/MIC) (2010) 382 and could work for the wafer surfaces here. For N-type wafers, thermal S1O2 or SiN should suffice.

[98] A silicon dioxide etch stop 24 can be formed on the bottom of the wafer.

[99] Figure 9a shows a Single-Sided-Single-Base-Device (SSSBD) using optional asymmetric dopings to support for example Punchthrough (also applicable to the SSDBD) which is now in the lateral direction. The structure is similar to the device of Figure 7a. Doping the holes of alternate rings 26 with a deep P type diffusion 28 can create a field-stop.

[100] Shallow CE doping can create a "transparent emitter" to create an 12 type (IGBT- replacement transistor) which exhibits rapid turn-off (low E 0 ff).

[101] A JFET or BJT type BASE is created according to the doping of the N+ and P+ region profiles and whether or not the N+ doping manages to pinch-off the P region or whether the N doping envelops the extra P doping - this can also be applied to the SSDBD. See the schematic circuits of Figure 9b.

[102] An alternative minority lifetime control is possible by using for example gold or platinum doping in a separate step or combined with the CE, BASE doping phases to produce regions with decreased minority carrier lifetime.

[103] To make low resistance contacts, the holes (or pores) will generally be filled or just plated with metal, polysilicon or similar facilitating contacts on the wafer surface where wiring (possibly multilevel planar metal wiring) connections will be made to parallel multiple rings for higher current ratings and to connect to the outside world. TSV (through- silicon-via) techniques can be used.

[104] ALD is another option for coating the holes with e.g. tungsten before possible electroplating.

[105] Connections to the top, bottom or both surfaces are possible depending on whether or not the holes pass completely through the wafer. It is not necessary to connect to the bottom electrodes - leaving the option of keeping the bottom surface clear for heat transfer mounting. [106] For the CE terminals, first a polysilicon liner then a conductor fill would result in the well known polysilicon-emitter concept to give higher Beta to the device.

[107] TSV type nano hole arrays or porous silicon could be plated using an ALD process combined for rapid bulk quantity deposition for vertical vias eg. WF6 (Tungsten

HexaFlouride) / B2¾ (DiBorane) ALD chemistry or WF6/S1H4 or WF6/S12H6 disilane chemistry.

[108] Faster options are possible with combination ALD and chemical vapour deposition (CVD) such as ALTUSR PNL™ (PulsedNucleation Layer) Tungsten system.

[109] Kelvin connections are possible using top and bottom if desired e.g. the bottom would provide the CE1, CE2 power terminals, whilst the top would provide CE1/BASE1 CE2/BASE2 signal lines and be free of high current.

[110] Figure 10 shows a co-packaged driver IC 30 for the SSDBD (single sided double base device), which driver can be formed on a silicon-on-insulator (SOI) substrate to allow the CEl+BASEl and CE2+BASE2 circuitry to coexist on the same silicon, where otherwise the high voltage potential difference between these two ends of the power path would cause problems for a bulk silicon driver circuit. The capacitors 32 shown indicate an isolated (high common-mode reject) signalling link between the two domains.

[Ill] The driver chip is shown flipped and bump-attached to the power transistor die.

[112] Figure 11 shows junction isolation doped strips 34 to fully isolate multiple independent transistors 36, which can now be located in the same silicon without interference or leakage through the substrate as is a common concern for power integrated circuits. Driver circuity including CMOS circuits can also be fabricated in the voltage islands created by what are effectively unbroken vertical doped walls. By these methods, half- bridge or full-bridge switching arrangements or indeed any smart-power high voltage integrated circuit applications can be realised on a single die. By using power switches in series, very high voltage composite switches can be fabricated on a single die which will still retain the high switching speed of the low voltage elements from which it is made.

[113] Multiple voltage devices on the same die can be created by use of different ring pitch (drift region width) something not possible for vertical devices. Series-connected lower voltage devices also eliminate the problem of ultra-lightly doped silicon being needed for 3kV and above.

[114] Again, the capacitors 38 shown indicate an isolated (high common-mode reject) signalling link between two domains for overall control and feedback signaling. [115] Figures 12a and 12b respectively show a circuit diagram and a timing diagram for a dual-lifetime transistor arrangement according to the invention. This is fabricated as shown in Figures 9d and 9e.

Dual-Lifetime Transistor

[116] One unique feature of the concentric-ring transistor construction is that each ring is a fully contained transistor which in principle could have different doping systems within and at the ends of the drift region compared to its neighbours by using selective masking/ doping. This scheme could be applied advantageously to make some fraction of the rings operate at high effective lifetime (slow turn-off but low on-resistance) and another, possibly smaller, fraction of the rings operate at low effective lifetime (faster turn-off but higher on-resistance) to make a dual-lifetime transistor. This is done by modifying the lifetime-control doping mentioned previously between transistor rings. Such a composite device would have a high-lifetime-BASE electrode and a low-lifetime-BASE electrode, respectively controlling transistors 40, 42 which are still connected in parallel with each other on the power switching path. With a suitable driver circuit it is possible to achieve simultaneously very good conduction loss and switching loss performance as measured by the well known R on , E on , E 0 ff metrics.

[117] For turn-on, the high-lifetime transistor 40 would be used - routing all the base current into those high-lifetime rings. High lifetime gives high-beta and therefore a lower Ron for a given base drive.

[118] Prior to complete turn off, a suitable driver chip (possibly on-die) can re-route this base current into the rings of the low-lifetime transistor 42. This allows extra time for the space charge to drain away from the high-lifetime rings but the low-lifetime transistor keeps the full current flowing - albeit at a temporarily higher R on loss. Ultimately when the low- lifetime path is switched off there will be no tail current from the high-lifetime transistor rings which are clear of charge and E 0 ff will be that of the speed-optimised low-lifetime devices.

[119] An advanced driver chip can hide the 2-stage turn-off scheme as shown by delaying the initial turn on by the known turn-off time and thus maintain an output pulse width modulation (PWM) ratio identical to the input PWM ratio (albeit with some small latency - generally not an issue in practice). See Figure 18a. [120] Figure 12a shows one embodiment allowing a driver IC to select different BASE outputs on demand to implement the two-step dual-lifetime scheme, and Figure 12b shows the expected turn on / off waveforms for the composite transistors.

Example Process

[121] Figure 13 shows an example of an etching process for the transistors of the invention. As a low cost alternative to dry DRIE or plasma etch equipment, as mentioned above, MacEtch , also known as MACE, is able to fabricate high aspect ratio structures on silicon. MacEtch is a wet-etch method described by Z. Huang et al, "Metal-assisted chemical etching of silicon: a review" Adv. Mater. 2011, 23, 285-308. Holes of even sub-micron size can be etched right through a silicon wafer by forming a pattern of noble metal (Au, Ag, Pt, or Rh) on the silicon surface then placing into a tank of H2O2 + HF + H2O. Either a masked pattern or placement of gold nano / microspheres forms the pattern and the latter tunnels into the silicon to form the holes.

[122] For economy, throughput can be high by processing many wafers in parallel in one or multiple etching tanks.

[123] Anhydrous, or dry HF etching together with some non-condensing water vapor and oxygen gas might also achieve a non-wet chemical etch.

[124] The figure shows a technique where even though all of the deep holes are formed at the same time, they can be individually doped with the required polarity using an oxide masking technique followed by furnace or plasma doping. After formation of the nano-holes (a), thermal oxide is grown on the surface and down the insides of the holes (b). The oxide is patterned and selectively etched to remove it from the inside of some of the holes 44, then P-type doping is applied (c). Oxide is then regrown over the entire surface (d). The oxide is patterned and selectively etched to remove it from inside of the other holes 46, then N-type doping is applied, possibly using doped polysilicon for a polysilicon-emitter effect (e). The finished article, minus the final wiring with oxide removed, and copper via fill 48, is shown at (f). The well know spin-on photoresist, expose, develop, HF etch cycles are not shown and occur between stages.

[125] Full control of dopant position and strength is gained by using as many repetitions of this process as needed. Polysilicon emitters can be formed during this process for the highest possible beta. Retrograde doping profiles and heterojunction emitters are possible by changing the materials deposited. Discretely identifiable holes are shown but there is no reason that nano-holes, making effectively a porous silicon in the desired areas, would not work just as well.

[126] Normally, porous silicon on macro scale uses N wafers and electrochemical process, but this has limitations on the types of array patterns which are possible using the traditional masking.

[127] G. Gautier, "Deep trench etching combining aluminum thermomigration and electrochemical silicon dissolution", Appl. Phys. Lett. 88, 212501 (2006) describes another possible solution to use aluminium through-wafer thermomigration followed by preferential etching to create holes, although the typical resolution is >20 μηι in diameter.

[128] An interesting further possibility is to use smaller, possibly nano-sized holes to dope the drift region with profiles impossible to achieve ordinarily. Figure 13 shows nano-holes which have a dot-density used to modulate the doping. Given sufficient thermal diffusion time the doping profiles could be smooth gradients. With a gradient of SiGe doping in the drift applied by this method, electron drift could be enhanced through bandgap engineering.

[129] US-A-4754310 describes superjunction concepts in which N- and P-type strips are doped side by side and work to deplete each other to produce a net "instrinsic" silicon effect but with much better than normal majority carrier conduction due to their increased doping. This allows much faster operation of the dual-carrier (electron and hole) devices since a higher minimum level of majority carrier conductivity is possible when the devices are not in their depleted state.

Example Application

[130] Figure 14a depicts a schematic for the high voltage components of an active bridge rectifier manufacturable with the techniques of the invention.

[131] Different polarities of T2 switches have been used: the top two 50 are manufactured on an N-type wafer so that a single I-MODE driver chip can support those two integrated devices from a single VDD supply to rectifiy the positive excursion of the AC input.

[132] To rectify the negative polarity, a pair of T2 devices 52 is built on a P-type wafer. The bases can be controlled as mentioned in US- A-2017/ 287721 to effect soft-start or overvoltage protection of the downstream DC equipment. This only requires two of the four active rectifiers to be controllable. Therefore the NPN transistors at 50 can optionally be replaced by links for a diode-only mode. [133] Figure 14d shows JFET devices of both high power and low power that are easy to fabricate according to the invention and are useful for bias supplies - in the role of extracting a few μΑ of startup current through lDss@V gs = 0V (the current is gateable 'off after boot-up digitally as shown).

[134] These JFETs are also useful as high-common-mode-difference level translators for digital signals between low-side and high-side I-MODE drivers as shown. The JFETs can be driven with forward-biased gates to operate as bipolar-mode JFETS (BMJFETs) with the same drive circuits as used for other PN junctions.

TCAD Simulation

[135] A technology computer-aided design (TCAD) simulation result of a nominally 700V SSDBD according to the invention is seen in Figure 15. The hole sizes are 8 μιη diameter for the BASE and 8 μιη x 16 μηι slot for the CE terminals and doped accordingly.

Centrifugal Method of MacEtching

[136] One version of MacEtch proposed in the literature incorporates a magnetic layer, e.g. of iron, so that the magnetic field can assist in the etching process. The force available is quite low with ordinary permanent magnets.

[137] In Figure 16 a machine construction is shown for providing centrifugal assistance of high directed force to the metal-assisted-chemical-etch process. Catalyst-metal of Au, Ag, Pvh, Pt, W or similar possibly isolated patterns of discrete shapes are deposited on the surface of the wafers 54. The wafers are placed in a typically plastic drum 56 with closed ends together with the etchant. Low speed initial rotation will allow the shapes to 'bed in' then high speed rotation will give many 'G' of effective increase in centrifugal forces directed as pushing the catalyst through the wafers as the etching process proceeds. The currently known method of magnetic force MacEtch is weaker by comparison, so it is more prone to exhibit trajectory drift as the metal passes through the wafer. Centrifugal force is sufficient to warp the wafer 54 temporarily and this would also help keep the etched holes normal to the wafer surface.

Improved MacEtch Hole Formation Method

[138] Usually 1:1 patterns of noble metal, as shown in Figure 17a, are used for etching isolated structures with the MacEtch process, so gold is patterned exactly as the holes are to appear in the etched material. Problems arise because the etching process requires exchange of etchant and reactants from underneath the gold to the bulk liquid, or else etching stops and/ or bubbles form causing the mask to move around laterally. The usual solution is to make the gold "nano-porous" or so thin that atoms can diffuse though it. This helps, but limits the etching rate and the very thin (e.g. 10 nm) gold films are fragile and tend to break up over long duration etching.

[139] To address these problems a two-step approach is used. First, as shown in Figure 17b or c, a "Waffle Griddle" pattern can be used instead of a full circle to do the etching. It has ample edge length to allow diffusion to/ from under the metal catalyst but acts in the manner of a cookie-cutter and will produce long tall 'nano-' or 'microwires' within the desired hole as the metal descends through the silicon. These wires will be etched away with a final 'trilogy etchant' - typically 126 parts nitric acid (70%), 60 parts H2O, 5 parts ammonium fluoride (40%), which has a silicon etch rate of 150 nm/ min. Four minutes in this solution will completely dissolve wires up to 1 μιη in diameter and will attack less than 100 nm of protective oxide which would be used on the silicon surfaces. An increase of diameter of 1.2 μιη of the holes is expected.

[140] Improvements expected of using this MacEtch method are that isolated patterns are prevented from wandering, increased edge length is provided to allow for chemical diffusing of etching and by products, for faster speed, and the etch process is now fairly independent of the shape of hole to be created.

Further Switching Circuits for Power Integrated Circuits

[141] Figure 18 shows circuits and structures suitable for integrating, and incorporating the ultra lateral concept of the invention.

[142] Figure 18a shows how a combination of B2 device and 12 devices (WO 2014/122472) provides a half-bridge output on a single piece of silicon, yet only a single driver IC is needed. No level shifting is required and the same base current is effectively switched to whichever base bhl, bll or bl2 is needed where bll and bl2 are different lifetime-controlled sub-transistors within the lowside switch.

[143] Multiple half-bridges can be placed on the same silicon wafer, e.g. two or three half- bridges to make a monolithic two-phase or three-phase power stage. ESBT i.e. emitter- switched bipolar mode, explained in US-A-2017/287721 is possible but is not shown here.

[144] Figure 18b shows the same circuit as Figure 18a, but working as an active half-bridge rectifier. In this mode, the current directions are opposite those of Figure 18a, which invokes opposite conduction modes in the transistors (Common Emitter becomes Emitter-Follower and vice-versa ), but otherwise the circuit sequencing operation is similar. [145] Alternative labeling AC1, AC2 is used in Figure 18b for configuration as a fast AC switch which connects between AC1 and AC2 nodes when activated. The base current would be multiplexed at high speed between the two inverse-series connected transistors to turn them both on individually or at the same time. Many options are possible for the choice of series device for a 1200 V AC switch, e.g. two 12 devices of 1200 V rating each using punchthrough (each only supports unidirectional blocking) or two 600 V-rated T2 switches where each can support +/- 600 V for 1200 V total rating. A high switching speed of the former is assured when lifetime or transparent emitter control is used and conduction loss is still good for a dual device because two 1200V punchthrough devices have the same combined drift region thickness as a single 1200V non-punchthrough AC device but a super- proportional benefit of beta and R on due to the half-thickness of the each active switch.

[146] Figure 18d is a transformer-coupled driver which affords the possibility of recovering base charge energy, since the paths through the transformers are fully bidirectional. The drive circuit has limited ability to move far from 50:50 duty cycle as is typical for simple transformer systems. The circuit is shown with a double base device from WO 2014/122472.

[147] Figure 18e therefore shows transformers operating at multiples of the power switching frequency to deliver a bipolar drive voltage able to turn on and off the bipolar junctions at will for an arbitrary PWM ratio.

[148] Figure 18e incorporates the circuit of Figure 18d into a single ended parallel resonant (SEPR) converter topology, driving an inductive cooking hob where the bidirectional transistor can be used to completely replace the bridge rectifier needed by a typical DC bus IGBT solution. Losses are reduced from 100W to around 10W. Alternatively, the adiabatic process illustrated in Figure 24 can exploit a half-bridge pair of transistors with the L p being the hob winding and the L s being the eddy current loss path in the saucepan. The same power conversion topology used for inductive hob drive can be deployed also for a microwave oven magnetron drive, a rice cooker, etc.

[149] Figure 19 shows I-MODE driver circuit configurations from US-A-2017/287721 which can be used with the ultra lateral switches of the present invention for different unipolar and bidirectional switching.

[150] Figure 20 shows different transistor types that are useful for multiplexing different voltage sources to make stepwise arbitrary power waveforms suitable for controlling a load. The top and bottom transistors are unidirectional while the middle taps require bidirectional switches.

Fast Single-Sided-Single-Base-AC-Switch (SSSBAC)

[151] Figure 21 shows a fast Single-Sided-Single-Base-AC-Switch (SSSBAC) - also known as a "T3" type. It is possible to fabricate such a switch without needing lifetime control or transparent electrodes using the scheme of Figure 21. This can be seen as a simplification of Figure 18b, but here, instead of two separate transistors each with terminated N+ structures at the ends of the drift region, the two transistors share a common base connection and have a drift regions which permit diffusions of electrons back and forwards. In effect they have a centre-tapped drift region.

[152] The operation is similar to Figure 1C of WO 2014/122472. The SSSBAC has the ability to pull charge from the base for rapid turn-off and allows the base drive to be adiabatic (charge recovering).

[153] Figure 21a is a 3D view of a section through a ring structure. Electrons can be injected through a forward-biased PN junction of BASE / EBASE which will turn on both transistors since there is not a continuous N+ region in the center of the drift region which would block electrons.

[154] P-medium doping around all the holes made in the center gives a field-stop effect to support punchthrough blocking mode of whichever transistor half is reversed biased (this approximately halves the needed drift thickness versus non-punchthrough). Due to the PN junctions at the ends of the drift region, the BASE driver circuitry will generally be self- biased at one diode drop above the most negative of CE1 or CE2. For this reason it helps to use a floating base driver using transformer coupling. The I-MODE self-bootstrap driver concept of US-A-2017/287721 can be used through transformer coupling and very high (multiples e.g. lOx or lOOx of power switching frequency) base current generation circuitry.

[155] In Figure 21d, the AC current path is interrupted with a capacitor which provides a low impedance source to extract a fraction of the load current through the PWM action of switch SWA after first being rectified by the polarity swapper circuit (intelligently controlled by the detected polarity - not shown). TR1 is typically a 1:1 turns ratio coupled-inductor (i.e. transformer) which only needs to be in the nanohenry range of primary inductance. The normal function of the missing switch SWB is taken with Dl which is a Schottky barrier rectifier to capture the flyback energy as a voltage driving a current into the SSSBAC transistor. Waveforms similar to those shown in Figure 18e can be expected and diodes D2 and D3 prevent any losses during the SWA on-time. Fully proportional base current control is set as a forced-beta given by the SWA PWM ratio. This circuit can also be used to drive any other BJT or 12, or other transistor type in a fully floating configuration with the main downside being the extra loss of the Schottky voltage drop, which itself could be overcome with active rectification on the secondary side of the coupled inductor. Both Dl and D2 could be fabricated on the power transistor die, meaning that only a passive external coupled inductor is needed to control the power devices in a totally isolated manner.

[156] For fast turn-on and turn-off of the power transistor, FET PFET1 in combination with SWA can be turned on briefly then periodically whereby D2 will set a negative bias on the BASE of the transistor. Reverse voltages of around 5V are sufficient. Signal noFF going low is used to turn on PFET1.

[157] A ping circuit to monitor a remote switch or other isolated input can be realized by adding one more winding to inductor TR1. This is a useful control input from either a mechanical switch or electrical output of e.g. a PLC controller. The state of the switch on the isolated side can be determined on the primary side be the extent of the primary voltage swing.

Example Process Flow

[158] An example of a process flow to build basic transistors according to the invention is as follows:

[159] Firstly, gold is patterned for making through-silicon holes using soft UV nano imprinting. This is designated mask #1.

[160] All through-silicon holes are etched at the same time in wet etchant.

[161] In the doping procedure, any doping which should be applied to all the holes is carried out at this stage. E.g. the field-stop P-region could be applied to all holes.

[162] For CE1 and CE2 formation, oxide is grown everywhere. The oxide is removed for the N+ holes to create mask #2. Phosphorus doping is then carried out.

[163] For the base, the oxide is grown again, and removed for the P+ holes to create mask

#3. Boron doping is then carried out.

[164] Next, the top and bottom surfaces which represent the edges of the drift region, are passivated, using ALD of AI2O3 e.g. with a spacial ALD machine, such as that at http:/ / www.solaytec.com/. The passivation pattern is mask #4.

[165] Both sides of the device are then covered with a dielectric, for example SU-8 using a spin-on technique. This covers the passivation layer and has a thickness of e.g. 2 μηι. [166] The dielectric is patterned so that openings exist at the locations of the through- silicon holes, to create mask #5 on the front of the device and mask #6 on the back.

[167] A second layer of SU-8 is patterned for the trenches to provide mask #7 on the front of the device and mask #8 on the back. These link up to the openings of previous masks, enabling access to the contacts.

[168] Metallization similar to a TSV process is then carried out. For a first level TSV this simply involves plating into the trenches. A TiN ALD (Spacial ALD) conformal deposition, 50 nm thick, and with a 25 Ω resistance, coats the inside of the through-silicon holes and the top and bottom wafer surfaces, and is a diffusion barrier for copper into silicon.

[169] Next, copper electroless plating and/ or electroplating is used to plate the through- silicon holes and thicken up the TiN patterns to form the first level copper interconnect in the trenches. The copper is annealed at 350 °C for one hour in a nitrogen atmosphere (a higher could affect the SU8).

[170] The device is then flipped so it can be surface mount device (SMD) soldered. The two-layer metal will be on the bottom. The top surface can be prepared for clip-on heatsinking.

Adiabatic Operations of Minority Carrier Transistors

[171] The transistors described previously are all either minority carrier devices or majority carrier devices with conductivity modulation caused by minority carrier injection. This phenomenon dramatically reduces the conductivity losses of the switches but comes at a price of "saturation" and "desaturation" time. These refer to the processes of charging and then extracting charge from the forward biased PN junctions of the transistor respectively. Often this puts minority carrier based devices at a competitive disadvantage to unipolar devices such as MOSFETs which do not have this issue and can switch faster in "Hard- Switching" applications.

[172] To combat this effect, a technique called adiabatic switching is described in the following sections, and the specific measures needed to apply it to minority carrier devices where it can reduce switching losses to below those achievable even with silicon carbide or gallium nitride. When operating adiabatically, all charging and discharging is done in a non- dissipative way using magnetic energy stored in inductive components to exchange energy with the charge storage nodes.

[173] Figure 24 gives a building block for building an adiabatic system using a transformer- coupled set of switches to form a bridge, also known as a synchronous modulator/ demodulator. As mentioned with respect to figures 18d and 18e, there exists a bidirectional, i.e. reversible, energy path between the switch capacitances and the magnetic components.

[174] Figure 23 shows multiples of the previous transformers/ bridges operated in phase- offset interleaving and how this can maintain a continuous power path between both sides of a power converter yet still allow time for the adiabatic voltage reversals needed - which are hidden in the sequence.

[175] Operation in adiabatic mode occurs as shown in the simplified transformer +/- drive polarity circuit of Figure 24. By controlling the switching times it is possible to exploit the largely trapezoid ramp of voltage caused by magnetisation current to charge all the different capacitances. There exists an optimum point of operation, shown in Figure 25, where the transistors switch on perfectly in time with the inductive-current induced ramp.

[176] A unique identifying feature of a properly adiabatic system is that virtually all of the observable power voltage swings in the system occur when the transistors are off. Ideally, transistors switch on only to remagnetise the inductive components where energy is being stored for the next voltage transition.

[177] The switching environment for the transistors is entirely benign. There is no risk of second breakdown in the transistors, no chance of dynamic breakdown or snapback effects. The usual figures of E on and E 0 ff energy loss do not apply. The transistors are always switched on and off with zero voltage across them.

[178] The output capacitance of power transistors, the transformer stray capacitances any other charge store attached form one effective Ό capacitance value. Since the switching losses and CV 2 /losses are largely eliminated the transistors can be scaled up in size to reduce conduction losses to the lowest practical level.

[179] The above discussion has shown adiabatic operation of the power transformers, but the same technique can be applied to the base drive transformer of Figure 22 where all of the base charge (and some of the drift charge) of driving the power bridge transistors is recoverable, is stored in the magnetizing current of suitably chosen transformer design and recirculated to discharge the base (and some of the drift charge) charge. Very high levels of circulating current can be used and the transistors can be switched on and off in under 500nS. Very efficient operation up to 200 KHz is possible for a 1000 V transistor system, with higher speeds for lower voltage systems. [180] One drawback of adiabatic operation is the fairly fixed operating frequency and the limited ability to modulate the output voltage by the usual variable PWM method. Instead, to produce a variable output voltage (effectively a programmable transformer turns ratio), a (coarse) dynamic tap selection with a fine tune PWM "blend" is implemented as shown in Figures 26 and 27. Such circuits or multiples thereof can perform common tasks, such as AC sine wave generation, as in a 3-phase motor inverter, or in reverse can perform AC to DC conversion with unity power factor if needed.

[181] A single multi-tap generator can be tapped at different points by many independent in-out or output generators (since all power paths are bidirectional), without having to duplicate the multitap transformer. E.g. three separate tap select multiplexed and interpolator pairs would drive an induction motor.

[182] Another tap and interpolator could work as a MPP (maximum power point) tracker wherein a solar array voltage is tapped and interpolated to the best point(s) on the transformer stack to account for the instantaneous solar voltage being regulated. A further example is use of the tap and interpolate system to charge and discharge a storage capacitor adiabatically to provide either AC ripple cancellation or unity power factor correction depending on whether the DC bus is a source or a sink of energy.

[183] For electric vehicle applications, the taps could be tied to the taps of a high voltage battery string, whereby the transformers would automatically spread the energy load or charge evenly between the batteries, no matter which tap the final load or the charging current is attached to - as per fig.120 option.

[184] Figure 26a shows an application of 400 V using a stack of 66 V-rated power bridges but the concept is applicable for higher voltages. E.g. using 1000 V transistor bridges would support 6000 V operation. The stack is a series string on the DC bridge, but note that the transformer windings are not in series: each is driven by its own bridge and each shares a common magnetic core. On the other side of the isolation barrier is a similar stack of bridges and now multiple voltages are available by tapping at the different positions in the stack.

[185] Figure 26b shows a non-isolated autotransformer version. It can be advantageous to produce a non-isolated DC to AC converter, since this reduces the copper losses (the primary is removed, freeing winding area on the core for the inductor string), promotes an 'autotransformer' mode of power transfer and can simplify the control electronics. To convert to non-isolated mode, both the primary winding and primary drive/control electronics are dispensed with and the input DC power source is connected to the top and bottom of what was the secondary series-DC synchronous modulator tap string. No other changes are needed.

[186] Operation is now quite different because much of the output current from the selected tap flows directly from the DC input source. Interleaving of transformers is still beneficial to prevent discontinuities in the input and subsequent inductor voltage-bounce or capacitor voltage dips.

[187] To generate any voltage from 0 to 400 V, the circuit of Figure 27 can be used. Here, one of a set of coarse taps of 50V resolution is selected, using switches according to the invention, then fine tuning is performed using PWM interpolation (blending) between tap voltages. In this example, low voltage MOSFETs are suggested for the fine tuning PWM.

[188] Note that the previous adiabatic circuits work for bidirectional AC to AC power conversion where the switches are AC types. Also the DC circuits operate as bidirectional power converters useful for vehicle applications such as motor drive and regenerative braking.

Communication and Power Linkage using Coupled Inductors

[189] In many applications, beyond simple on/ off control of these transistors there is the need to coordinate activity of one or a number of transistors with one or more controller devices. This entails communicating digital data to/from transistors which may be riding on very high and fast slewing common-mode voltages. Figure 28 shows a mechanism and communications protocol which can achieve this using only a single coupled-inductor shared with the I-MODE boost inductor function which is explained in US-A-2017/287721. The normal I-MODE self-bootstrap, forced-beta base drive concept is previously described as being divided into a two portions of inductor operation: charge and discharge. In the charge portion, with SWA on, magnetic flux builds up in the inductor in response to an imposed voltage. During the discharge portion, with SWB on, normally the current is redirected into the base of a power transistor. Where isolated secondary windings are present on the core, the discharge could also be seen as a 'Flyback' event.

[190] Figure 21d shows a simplistic floating AC transistor switch with an isolated on/ off control interface, all linked together with a common magnetic circuit (core), possibly suitable for a solid-state-relay application.

[191] This concept of coupled inductors can be extended to a fully functional isolated digital data and power network to support high frequency half bridge or full bridge switching with control and measurement data. The extra features are shown in Figure 28 for the example of a full bridge, quad power transistor setup. There are five separate control ICs, each electrically isolated from one another. One device is a typically a master controller in Domain 0 and will either implement the overall control algorithm or interface to a controller that does so. Simply by using turns on a common air or other magnetic circuit to make the coupled inductors, each of the ICs is simultaneously in power and communication with all the others.

[192] A data communications protocol is built on top of the power transfer mechanism. A round-robin or bit-addressable protocol sequences the particular transistor as the target for communication. The addressed transistor can route the flyback energy from the core to the base of its controlled power transistor if it needs to turn that transistor on. If the flyback energy is not directed to any transistor, the voltage can shoot high, as was documented for the I-MODE, driver and here each device in each domain uses either active or passive rectification on each isolated domain of the system, and is able to charge up a local VDD from this event. Thus, all the isolated CMOS I-MODE dies can run their logic and analog control functions. This event can also be used a synchronizing event once per packet, whereby all the attached devices synchronize their state machines.

[193] The PWM ratio used by the inductive boost circuit to transform VCAP voltage to VBASE voltage can be dynamically changed from buck to boost, to recover the base charge and put it back into VCAP during turn off. This could be important at very high frequencies, to reduce switching power consumption, especially with very large super-junction BJT structures.

[194] Domain 0 is the interface domain, which interfaces with an external device to control the power transistors and provides a conventional digital data interface, e.g. a serial peripheral interface (SPI) for status, setup and measurements. It too generates a VDD via the coupled-inductors, so that any CMOS control IC connected in this domain will be powered.

[195] Domain 1 and Domain 3 are power-sequencing domains. ICs in this type of domain are responsible for high-current (through current) control of one or more transistors in the main power path (SWA) and will extract the base drive current using the I-MODE boost system and can, using SWB, directly drive (without any intervening winding) one or more bases of one or more transistors. In the quiescent mode, when no power transistors are turned on, there would be a microampere leakage (parasitic or JFET current-source for example) which would allow occasional (perhaps several kHz) 'pings' of the local winding using SWA and the VCAP leakage-developed voltage. Flyback pings (Vboost time) will be rectified by ICs in all other domains to furnish them with micropower level VDD supplies to operate the CMOS when the loads are off.

[196] Domains 2 and 4 are slave-domains and do not possess the SWA switch, instead relying on power from the coupled inductor to feed to the base of the controlled transistor using active rectification of the flyback energy. These slave ICs can be physically much smaller and lower cost than power sequencing ICs since they lack the very large SWA MOSFET and only have to carry base current, which is some fraction (forced beta) less than the collector current.

[197] Two distinct data communication protocols are present. The first is in the pre-active mode signaling regime, when the power stage is not active, and the second is active-mode data communication regime. The biggest difference between the protocols is whether the power transistors are switched on or not.

[198] In the pre-active signaling protocol, domain 0, the interface-domain, is able to issue signals to all domains simultaneously by pulsing its winding to VDD for a short time using PFET1. This signal is received in all other domains. The length of this pulse determines the event. This event may clash with the quiescent power generation of the power-sequencing domains mentioned above, so in quiescent mode domain 1 must use specially designed weakened drive transistors SWA_WEAK which can be forcibly overridden by the signaling domain.

[199] For synchronization, a short length V DD pulse from domain 0 (longer than a 'ping' pulse) signals the node to enter the pre-active data protocol and synchronizes the state machines in each domain.

[200] The ON command is a long length pulse to enter the active protocol and turn the power transistors on.

[201] When the synchronization pulse is received by domains they enter into a pre-active mode, in which the power-sequencing domain controller (domain 1) will now issue multiple rapid pings in a row. The purpose of each of these is to transfer one bit of data from one domain to all the other domains. A simple round-robin scheme or bit-addressable scheme could be implemented to set the currently addressed domain as the source of the data bit. In pre-active mode, no IC will route the flyback (discharge) pulse onto any transistor base, so flyback will rise to VDD level unless it is 'squashed' to some lower level.

[202] The mechanism for data transfer is by "flyback pulse squashing". This is done by any 'addressed' domain's driver IC driving SWX (instead of routing the pulse to the transistor's base via SWB) and by doing so this can transmit a "1" bit of information (and the absence of this even can be interpreted as sending a "0" bit). SWX being on keeps the flux in the core constant (zero volts over the winding) and the magnetization current is circulated at low loss.

[203] Any domain will be able to detect the "squashed" flyback pulse using its receive comparator. A receiver gets the data bit value using a differential comparator to find 0 V instead of finding either VDD (Vboost) or typically 0.7V (the VBE voltage), as would be typical if all SWX switches were off.

[204] It is important that there can be some guaranteed full flyback events - some that are not squashed - to preserve the floating VDD generation mechanism sufficient to power all of the CMOS ICs attached. One implementation is to hard-code by design that every Nth (e.g 4th) pulse will never be squashed. This reduces the date rate somewhat and also the reduction of base drive current must be accommodated, in a similar manner to that suggested previously for the data.

[205] The pre- active protocol is very useful for setting up the domains ready for on/ off activity, for example to configure them for implementation of the active protocol (which can therefore be soft) and setting current limits, temperature limits, setting which devices are to be switched on when the active protocol begins, etc. A programmable logic similar to field- programmable gate array (FPGA) fabric could be incorporated onto the CMOS chip and devices uploaded over the pre-active protocol.

[206] For the active protocol, to actually turn on some of the power transistors, domain 0 issues a long-length- VDD pulse which is immediately and easily detected in all domains. Domain 1 will respond by starting the active mode, wherein SWA and SWB switch in sequence to boostrap current to drive one or more transistors.

[207] Which switches are activated, and in which round-robin timeslot, depend on the data bits previously sent during the pre-active protocol. Again, since the inductor flux is shared by the multiple windings in each domain, a round-robin time-share base current driving scheme could activate BASE1, the next pulse going to BASE2 and so on in each of the domains where transistors are to be turned on. In other words, multiple transistors can be powered by the single magnetic core. Each transistor receives proportionally less average base current but still it is possible to adjust the PWM ratios so that each transistor gets a sufficiently low forced-beta level. Generally, in a four-transistor bridge only two of the power transistors are turned on at a time. With a 50 ns, 25 ns and 25ns intervals for charge, discharge 1 and discharge 2 respectively, two power transistors would be operated at a forced beta of approximately 4.

[208] Even during active mode, the data communications are possible, if the addressed domain 'squashes' the flyback pulse, thereby sending a detectable "1" - using the same mechanism as was described for pre-active mode. The downside is that by squashing a flyback pulse the current supplied to the transistor's base current is obviously reduced. This can be corrected by domain 1, which can extend subsequent base drive pulses given to make up the shortfall.

[209] Turn-off, i.e. changing from the active mode to the quiescent mode, is controlled by domain 0, which can very quickly turn off one or more or all of the power transistors without delay or contention, using the 'flyback squashing' mechanism. If SWX in any Domain 0 is active it can squash the base current flyback events for all transistors connected to the single magnetic core, since the magnetic core is shorted-out during that time. The effect on the transistors is immediate but the state machines may take longer to respond, as when the power sequencing domains detect that the reserved VDD flyback pulse has been squashed, they may revert back to quiescent mode.

[210] Indeed any domain could force other domains to turn off for example because of a fault (e.g. overtemperature, short circuit, stuck-on) by exerting its SWX which would also set domain 1 to quiescent mode.

[211] Multiple active mode selection is possible without an intervening turn-off event. Some applications such as the dual-lifetime transistor require more than mere on/ off sequencing of the transistors and therefore require extra control bits.

Multiphase Implementations

[212] For each of the circuits involving the inductors and cores, multiphase versions exist, wherein multiple independent inductive/electronic paths work in parallel but are sequenced to be phase-offset from each other. Such circuits would be able to pass multiple bits in parallel if configured with the full complement of logic. Ripple current is reduced, the size of the inductors is reduced and the effect of 'flyback squashing' might be reduced if only one out of N phases is squashed to transmit a single-bit path of data.

Networking and Interconnection

[213] In Figure 29a, all of the components of Figure 28 are located together in a single module. It is also possible to create a monolithic silicon device with all the same pieces created in or on the substrate. [214] A coaxial square-section ferrite tube construction 60 runs around the periphery of the stacked die.

[215] Effectively, this scheme forms a network of intelligent addressable isolated power transistors, bootstrapping to gain all the necessary floating supplies at low cost. Because charge/ discharge pulses are issued at rates of 10 MHz or above, and each can transfer one bit of data, a high data-rate datastream is achieved which could carry information such as voltage, temperature and current digitizations between the isolated domains for control or protection purposes. The signal levels are high current (on the order of amps) and highly immune to interference.

[216] The device in each domain is able to participate in the charge time once the domains become fully synchronous. Phase locked loops could be deployed to lock the phase of the signals. Should, for example, two devices simultaneously route say 0.1 V of VCAP voltage to their respective windings (they will lock together by transformer action) the current will be fed from two sources. Effectively, the two windings are in series in terms of magnetizing the core.

Signal-Only Linkages and Isolated Inductors

[217] The arrangements describes above fully combine power and voltage distribution and signaling, whereas it is entirely possible to use signal-only coupled inductors, not intended to transmit base and/ or VDD power or to have some sections, using some domains, using non-coupled inductors

Magnetics Design

[218] Figure 29b shows on-chip magnetics using nano-pores and TSV technology.

[219] The nano-hole facility affords the possibility to make extremely high performance integrated inductors and transformers. A silicon wafer is etched, with MacEtch or a similar method, to produce through-wafer nano-slots 62 in a toroidal arrangement. These slots can be ALD or electroplated or wet chemical plated with a magnetic material which is deposited on the surface first and is then plated outwards to fill the nano-slots. Figure 29b shows a much coarser pitch for the nano-slots than that which would actually be used.

[220] The silicon still retains its integrity, but in the preferred radial magnetization mode there are periodic discontinuities in the magnetic material affording a distributed airgap. Due to the very fine distributed structure and predominantly one-dimensional aspect of the magnetic material, eddy currents are suppressed. This allows the use of high flux density magnetic materials, including pure metals such as iron, nickel or cobalt, without the risk of high eddy losses. Ferrite and other non-conductive materials are also possible. Assuming the magnetic material is of relatively high permeability, the effective permeability is set by the total airgap length between the magnetic pieces and can be well controlled.

[221] To make the conductive (typically copper) windings of the transformer, a modification of the TSV (through silicon via) technique is used, similar to that mentioned above, and possibly co-created with the contacts for the power transistors. This will produce vertical copper pillars 64, 66 which pass through the silicon substrate and can function as the vertical part of one or more spiral windings. The final step, to create inductors or transformers, is to form linkages 68 from the inside copper pillars 64 to the outside copper pillars 66 in a pattern which creates one or more spiral windings.

[222] The leakage inductance can be very low and the isolation voltage between windings is set by the oxide (or other dielectric) thickness between the windings, or alternatively by the depleted silicon if using doped holes.

[223] Ultimately, a nano/microporous silicon structure could be wet-oxidized to turn it into 100% S1O2. This could accommodate (effectively) infinitely fine wires and ideally low skin and proximity effects. #

Artificial Litz Wiring on the Inductors:

[224] For low inductances, a small number of turns is needed, which would imply a large cross-sectional area for the copper conductors (large holes or slots), but this brings with it the problem of magnetic skin and proximity effects which increase the AC resistance of the windings.

[225] For magnet wire transformers this is solved using a braided or 'Litz' construction, shown in Figure 29c. This allows thinner wires (approximately equal in diameter to the skin effect depth) for magnetic wire to have the same effect, i.e. that of forcing multiple thinner paralleled conductors (filaments) to share the current equally. It is not sufficient to simply fragment the cross section, but it is also necessary to make each of the paralleled filaments have the same "electromagnetic experience" passing around the magnetic circuit. The drawing shows that each filament experiences equal passage on the inside and outside winding layer positions.

[226] The nano/micro plated hole system can extend full cross-section copper conduction (not limited by skin or proximity effects) to frequencies of many GHz because of the very small cross-sectional diameters, possibly combined with the ability to interleave these wires using sub-micron multilevel metallization. Superjimction MOSFET / JFET / BJT System Using the Through-Wafer Nanohole Concept

[227] Superjunctions are described in US-A-4754310. The concept of through-wafer lateral devices is depicted in relation to a superjunction (SJ) MOSFET concept in Figure 30, shown from above the wafer surface, looking down at the through-silicon structures. The same concept can be applied to the drift region of a JFET device or BJT device and this will be demonstrated.

[228] A through-wafer gate 'tube' is created using MacEtch or other technique and then this is thermally oxidized (or ALD deposition of another gate dielectric could be used) before typically a polysilicon fill or even a metal coating method to provide the gate electrode.

[229] By using the ideas presented earlier for creating doped regions and profiles through the thickness of the wafer using nano / micro holes, the doping patterns shown could result.

[230] An N-type wafer with a P doped region underneath the MOS channel forms the MOSFET control gate, typically of an enhancement mode device (though depletion mode is possible with the correct implants). The other end of the channel enters into the drift region of the structure. Then, as shown under Option A, charge-compensating columns of Pmed (P medium doped) are formed with the peppered nano-hole, or nano-pore through-wafer MacEtch process explained above with regard to the bipolar devices.

[231] The N drift region could optionally be doped in a special way. Option B uses the native N wafer doping and only dopes the Pmed columns for the super-junction effect.

[232] Doping using selective conformal epitaxy of doped silicon would achieve the doping needed and could be used to close up the nano-holes.

[233] In Option B, the purpose of the Pmed (P medium doping) regions is only to deplete the N drift region columns to give the blocking voltage rating, but at the same time to benefit from the higher wafer N doping during the conduction region of operation. The Pmed columns do not participate in majority-carrier conduction so the fact that the cylindrical or other shaped holes might not have low surface recombination velocity should not affect operation. The only concern is that the P regions properly deplete and do not cause localized high voltage gradients. The choice of surface passivation of the holes is important - again a combination of ALD alumina and or silicon dioxide should be suitable.

[234] It should be apparent that the construction has no constraints upon the drift region length which is now a lateral dimension, unlike a normal superjunction MOSFET where the pitch of the columnar structure is restricted by the etching tools as the trenches become deeper. Here, the drift regions are at 90 degrees to a standard superjunction MOSFET and the wafer thickness is decoupled from the drift region length. Wafer thickness solely sets the effective "width" of the MOS device, e.g. a 500 μιη thick wafer, using 50 μηι lateral drift length, would have 10 times lower specific on-resistance than a standard SJ vertical MOSFET and be much easier to manufacture without special thin-wafer processing. Using nano-sized holes, e.g. 100 nm diameter, the column pitch could be reduced to below 1 μιη and with drift length of 80 μιη from the graph of Figure 31, it should be possible to build MOSFETs with ratings of many thousands of volts with this method, with less than single-digit specific on- resistances in mQ*cm 2 .

[235] Another advantage of the superjunction concept is that a device of any voltage rating can be fabricated by adjustment of the drift length, since the charge compensation mechanism scales linearly without needing to alter the drift doping at all.

Graded Doping Concentration Superjunctions

[236] Graded doping concentration superjunctions are known to have better breakdown voltage with respect to process tolerances and this useful feature can be implemented by simply changing the size of the charge compensation holes, which will vary the surface area and hence the amount of dopant incorporated.

[237] Field-plates can be used for charge compensation and here this would be done by insulating the column's holes first before filling with conductive material, e.g. polysilicon, then connecting the polysilicon to the source terminal or other potential, as an alternative to doping.

Semi Superjunctions

[238] Some of the benefit of the superjunction structures comes not from the charge compensation but from the presence of the columns through the drift layer, whose conductivity can be well below that of a fully highly doped compensation structure and still be useful. Especially for minority carrier devices, these columns help to remove charge during turn-off, making a much cleaner turn-off waveform, free of ringing and at higher edge rates. With these structures, devices of 3000 V or higher still have good switching performance.

Monolayer Doping Technique to Dope the Nano-Holes

[239] The tubes are well matched as they are all created at the same time by the same process. Therefore, there should be excellent matching of numbers of dopant species of the donor and acceptor types, resulting in good charge balance. [240] A monolayer of boron as deposited, typically using a monolayer doping process, for example 1.7*10 14 boron atoms per cm 2 surface area. If this is diffused over a micron thickness, this equates to a column being doped at 1.7*10 18 per cm 3 which is more than necessary for most charge compensation applications. Lower concentrations are possible, using different precursor mixtures, one part of which adheres to make a monolayer of inactive material, taking up a site which might otherwise attach to a doping-material molecule. A RTA (rapid thermal anneal) could achieve an initial drive-in, after which etching could be performed to remove a dopant-rich thin layer on the inside of the nano- holes, then finally a longer lasting thermal drive-in would complete the process to make a more uniform layer throughout the columns.

Vapor Phase Doping - Polysilicon Doping Option

[241] Vapor phase doping is a known method of conformally doping a silicon wafer. See e.g. Kiyota et al, "Rapid Vapor-Phase Direct Doping; Ultra-Shallow Junction Formation Method for High-Speed Bipolar and Highly-Integrated DRAM LSIs", Extended Abstracts of the 1991 International Conference on Solid State Devices and Materials, Yokohama, 199L, pp. 47- 49.

[242] Another possibility is use of low-pressure chemical vapor deposition (LPCVD) conformal deposition of in-situ or other doped polysilicon to dope the holes prior to thermal drive-in.

Post-Etching Tuning

[243] Breakdown voltage is optimized when compensation is perfect. Post-manufacturing tuning is possible if the compensation doped holes are treated with an etching step, e.g. a XeF2 gaseous etch able to remove a thin layer of doped silicon with each pulse. This could be an iterative process, by measuring breakdown voltage on a sample point on a wafer and repeating a pulse of XeF2 etchant if necessary. For this scheme, the compensation columns should have an initial overdose.

Passivation on the Doped Holes

[244] Having holes within the drift region of a minority carrier device risks reducing overall carrier lifetime. Therefore S1O2 or AI2O3, etc, for low surface recombination velocity, can be deposited, possibly by ALD, to maintain a good lifetime in the transistor. Conversely, to reduce the lifetime, a different coating can be considered to speed up turn-off.

Dual-Mode Bipolar/FET Switchover and Active Low-Recovery-Loss Rectifier [245] As an alternative or augmentation of the superjunction version, minority carriers can be injected in the manner of a BM-JFET (bipolar mode JFET).

[246] When the base/ gate voltage of a normally-off JFET is around 0.4 V, the channel is operating in JFET mode with only majority carriers providing the conduction. From this off (0 V) gate condition it is easy to enter and exit the majority carrier (ohmic) region at around 0.4 V, the minority carrier injection regime (conductivity modulation) occurring from about 0.4 V to about 0.7 V. When minority carriers are injected, the device acts as a bipolar transistor. In the forward direction it is known that majority-carrier devices turn off very quickly because there is no stored space charge to be removed from the junctions. In the reverse direction, when acting as a synchronous rectifier, it is also known that JFET devices suffer no reverse recovery time and automatically turn on from the negative VDS. For active diode/ self-synchronous rectifier operation, the gate controller can have a further means to detect when a reverse voltage is imposed over the switch to turn on with about 0.4 V at the gate. It also has a means to act, with a control signal to turn the device off, by dropping from a gate voltage of about 0.7 V to about 0.4 V, into majority-carrier mode before finally turning off with 0 V or a negative gate signal. In Figure 28, domain 2 includes means to detect the reverse voltage logic for detecting when to turn off.

[247] An optimised control sequence could switch the device from bipolar mode back to JFET mode prior to final switchoff, to eliminate tail currents.

Superjunction JFETand BJT Cascodes

[248] A JFET differs from a MOSFET implementation only at the source side, where instead of inversion of a thin channel of semiconductor, a pre-assigned channel is depleted by an adjacent junction to turn it on or off. A JFET can be normally-on or normally-off, depending on the doping characteristics.

[249] By adding a low-voltage source-series, typically MOS, switch, a cascode circuit is created, in which a normally-on JFET characteristic is acceptable since the overall cascode is normally-off. The cascode circuit gives very fast switching characteristics.

[250] Figure 30e includes a JFET. Figure 30f shows the JFET system reconfigured slightly to be driven in BJT mode, in which the base must exceed one diode-drop in order to turn on the device. BJT mode has the advantage of a given conductivity modulation which can take the on-resistance below that of the normal superjunction drift region. The JFET device can also have its gate driven into forward bias, whereby it injects minority carriers into both the base and drift regions, substantially lowering conductivity when turned on. A convenient feature of the bipolar-mode JFET is that it can very quickly be returned to its JFET, majority- carrier mode before turn-off, giving a tail-less turn-off suitable for hard switching applications.

[251] For all the devices mentioned, complete through-wafer junction or trench isolation is possible between the devices. "Mixing and matching" is possible by co-integrating opposite polarity MOSFETs and any other bipolar or other devices.

Fractional Current Boost Converter for VDD Supply

[252] With a JFET (or MOSFET) cascode system using normally-on power FETs, it is easy to extract a VDD voltage supply while the switch is off, since the source will naturally rise to a voltage Vpmchoff when SW ca scode is off. A diode and a low-dropout (LDO) regulator are all that is needed to provide VDD from the source voltage.

[253] To provide VDD continuously while the switch is on, modifications to the previously described I-MODE driver circuit for the BJT type are beneficial. Figure 30g is a diagram of a multi-element JFET device in which a fraction of the elements, and therefore a fraction of the total drain current, are routed through an SWboost MOS switch and an inductor which can now both have a low current rating. The main power current path is switched by SW ca scode without any added inductor and SWboost is switching some fraction of the drain current and forming a boost converter to provide VDD. For a BJT type of bipolar-mode-JFET, the circuit of figure 30h is more appropriate.

JFET Normally-Off, JFET Normally-On, Normally-Off Cascode and Inductorless Self- Power

[254] Using the concepts of the present invention it becomes possible to make a very high performance cascode circuit using a JFET of normally-on type, with a cascode connection to a low-voltage rating, normally-off JFET, BJT or MOSFET on the same die with a small space overhead, as shown in Figure 32. This enables inductorless power extraction. Previously, JFETs were mentioned or considered for providing small amounts of startup power to bootstrap the controller. Inductor components were previously considered necessary for BJT-type BM-JFET bootstrap base power sources (in which there is a need for significant base power). However, Figure 32 shows an arrangement in which the inductor components could be replaced. Since we are now considering a high-impedance field effect gate system, large continuous base currents are not required, so a low voltage switch can be used, which can for a short time increase the effective VDS of the overall power switch, by including the VDD voltage (decoupled with a capacitor) in series with the load. This switches the low side cascode switch off and switches on the optional PFET or diode. Because the normally-on JFET device will remain on, possibly until V ca scode reaches approximately 5 V (assuming 5 V pinchoff voltage for the power JFET), it is possible to conduct for a time the full load current into VDD, which might be about 1.8 V, to replenish VDD. All that the intelligent controller must do is to time the replenishment to maintain a given VDD regulation.

Superjunction or Normal PIN Diodes or Schottky Diodes

[255] Methods of manufacture of PIN diodes of normal or superjunction type can be easily derived from the drawings since all of the structures have a PIN diode type structure which is supporting the voltage. PIN and Shottky diodes are useful to allow for handover from possibly slow reverse-conducting switches in a bridge - especially in hard switching applications.

Adiabatic Gate/Base Driver Using Flying Inductor and Circulation While Not in Use, and Emitter Switching

[256] One drawback of silicon power MOSFET technology versus gallium nitride (GaN) is the higher gate charge of the former, which manifests in higher power consumption when driving the gates at MHz frequencies.

[257] This drawback can be counteracted by using adiabatic techniques to recover the gate/base charge. The mechanism involves making sure all charge/ discharge voltages are sustained over an inductance so that the energy is stored/ released and not dissipated.

[258] Figure 33a shows a basic version. Figure 33b additionally includes a path to allow for boosted voltages beyond normal VDD to drive the MOSFET gate at up to 15 V. The inductor is a low value, possibly integrated device and Figure 33c shows a series of partial versions of the circuit, in which a high current generated directly in time in the inductor or through an optional precharge period just before steering tends to drive the gate. There should be enough inductive energy so that it is nearly exhausted when driving the gate capacitance from 0 to typically 8 V in about 50 ns.

[259] Using any extra energy stored in the same inductor later to pull down the gate voltage, conserves the energy and can return it back to VDD in the manner shown.

[260] The higher-voltage rated PFET sequenced at the correct time lets the inductor-driver gate voltage exceed the normal VDD (typically 1.8 V) and even up to 15 V. This suits standard

MOSFETs and IGBJT devices without requiring a separate 15 V power supply.

[261] The precharge phases can set an arbitrary current level simply by controlling the precharge time. Any excess energy left in the inductor is generally returned to VDD. [262] Two or more copies of the circuit can be interleaved with one serving as the "turn- on" path and another as the "turn-off" path for the gate capacitance. This might be needed when generating very short on-times (or short off-times) where otherwise there would not be enough time to fit in the precharge periods.

Diodes Instead of Lifetime Control to Implement 12 Devices

[263] Diodes on the opposite side of the wafer can act like a PNP transistor with its base grounded, to assist in turning off the transistor from the base.

[264] For 12 devices (like IGBJTs) turn-off time is controlled by mechanisms which can alter the recombination rate of the injected carriers.

[265] Figure 34a shows the usual method of thin 'transparent emitter' lifetime control which is easy to implement on a vertical device, but not easy to implement in the ultra- lateral concept of the present invention. Instead, we refer to Figure 34b, which shows the ultra-lateral concept, viewed from above, since the junctions are not merely on opposite sides of the wafer as is the case for vertical devices. This uses a 'JFET' style opening in its bottom junction, which has the effect of giving a fairly fixed current sink to help turn off the junction. Figure 128c shows a PNP device which improves turn-off speed (with consequent reduction in the beta of the overall device). Where the Nmed doping is lower than the N+ then the PNP emitter junction is set up to have a lower turn-on voltage than the latter, giving an effective turn-off path to bypass the main P-/N+ junction.

Capacitor Structures Using MacEtch

[266] Figure 35a shows a capacitor structure using MacEtch according to the invention. A known similar structure, on glass, not using MacEtch, is described at http: / / www.nature.com/ nnano / journal/ v4/n5/ fig_tab / nnano.2009.37_F4.html. For example, holes of diameter 500 nm and depth of 500 μιη, provide an area of 0.8 nm 2 . With 50 nm of oxide thickness, 8.9 x 10 12 F/m x 3.9 S1O2 eR, each one gives a capacitance of 0.56 pF. At a pitch of 1 μηι, an area of 1 mm x 1 mm provides a generous capacitance of 560 nF.

Pulse Power Absorption

[267] With reference to Figure 35b, for several applications and in particular a DC circuit breaker application, the power transistor must handle very large transient overload conditions, potentially leading to very high localized heating in the junctions and device failure. Using the nano / microhole scheme and the fact that the transistor can be stretched indefinitely in the z-dimension, it is possible to extensively permeate the silicon structure with very high heat capacity material or a phase-change material to absorb the heat. The very fine distribution of the heat-absorbing material (including the use of high molecular weight polymers which are known to have exceptionally high thermal heat capacity) is not compromised by the usual effects of poor thermal conductivity, since the heat only has a very short path to cross into the heat absorbers spread through the typically silicon structure. It would also be possible to infuse the semiconductor structure with a "meltable" phase-change material to exploit the specific heat of fusion to absorb intermittent high overload events.

[268] In a diode format or back-to-back diode format such a semiconductor would make a good replacement for a metal-oxide-varistor (MOV) clamp.

Preplanned On Off

[269] Different devices and/ or modes are employed for the most effective on/ off operation.

[270] Figure 35c shows a circuit that adds to Figure 12 and digitizes one whole input PWM pulse (1 bit analog-to-digital converter style) with the transition times stored into a register buffer. Transition times digitized at above the 10 ns shown and say 1 ns (ring oscillator) precision are recreated at the same point one cycle (or other delay time) later.

[271] Knowing the commanded PWM input, the microcontroller can decide the best sequencing of transistors, slow (low voltage drop) and fast, as appropriate to generate the pulse. It can also decide whether and when to choose the BM-JFET or pure JFET mode for the appropriate transistor types.

Superjunction High Capacitance / Charge around 0 V and Countermeasure

[272] A final issue with the superjunction concept, especially relative to gallium nitride devices, is the very high drain-to-source capacitance Cos around 0 V, up to 20 V where full depletion is accomplished for a typical highly doped, low resistance columnar structure. In non-adiabatic, non-resonant systems, especially in half-bridge configuration, in both drive directions, the device turning on must charge the CDS of the device that is off, while there could be say 600 V across the switch turning on. This creates a very high E on loss. One possible countermeasure is shown in Figure 35d, in which an inductive boost path and a PIN diode (both formable on-die) can drive about the first 20 V of the swing from the low- side before the high-side driver completes the swing. This scheme is possible when the activity of all the components is correctly synchronized, and can reduce the E on losses by a factor of 30 - bringing those losses comparable to those of a GaN device.

CMOS Compatible Process Flow [273] The processing to make the power transistors should be compatible with CMOS wafer fabrication for implementing monolithic smart-power devices. Nano/micro through- silicon holes could be formed before CMOS processing starts and doped after the very high thermal budget CMOS processes such as well formation. CMOS processing would continue until just before the backend metallization, the filling and contacting of the nano/micro holes being completed before final metallization.

[274] Several CMOS processes feature photodiodes which could be used to receive isolated control pulses if the device package has a transparent region to receive the light pulses.

[275] Microcontrollers, ADCs and the like are readily available on the CMOS process. High Power Full Voltage, Full Switching Adiabatic

[276] The traditional approach to reducing CV 2 f power loss in a power switching circuit is to reduce the output capacitances of the power switches through use of GaN or other expensive semiconductors and operate at faster edge rates to reduce shoot-through losses in the half-bridges. This does not negate the dynamic power loss of the load capacitance, and the fast edge rates themselves can induce high losses through ringing.

[277] Figure 39 shows a circuit similar in intent to those of Figure 33, but now applied to higher voltage, higher power loads. The method seeks to largely eliminate the CV 2 f power wasted in charging capacitive loads at high speed. In the general case, the circuit has four transistors used to drive one output node. A reduced number of devices might be possible for loads with asymmetrical capacitance, such as a load incorporating freewheeling diodes.

[278] LI is a low resistance inductance and the rise and fall portions of the output swing are routed from the small transistors mpl, mnl to the load via this inductance. These devices can be small (and therefore low output capacitance - which is important because the CV 2 f energy of these is not fully recovered) since they only conduct briefly in a switching cycle so their conduction losses are low.

[279] Transistors mp2 and mn2 are generally much larger devices and are designed mostly to minimize conduction losses when the output is not switching. Large sizes are not a problem because their output capacitance energy (including superjunction capacitance) is largely eliminated as a source of loss by the adiabatic switching scheme as are the load capacitance energy / power losses.

[280] The transistors are shown as P type and N type MOSFETs, to highlight the similarity with Figure 33, but fully N type switches are possible, as are BJT or JFET type switches.

[281] Operation can be seen by way of the waveforms and switching sequence given. [282] In steps 1 - 4, the output is slewed using the inductor LI driven by mpl. Energy is not dissipated by the voltage difference between 500 V and the Q (output) voltage while all the loading capacitance is ramped; instead it is stored in LI, then later supplied to the load when LI is discharged. Mp2 takes over the holding of the DC output path at low DC loss.

[283] Steps 5 - 8 are similar to 1 - 4 but for the opposite polarity swing.

[284] This circuit is able to cope with very high levels of superjunction capacitance, output load capacitance, distributed capacitance, and reverse recovery capacitances with minimal Eon/Eoff. It is also free of cross-conduction in the bridge.

[285] If created using a multi-transistor substrate with on-die drivers then only one extra inductor is needed (a small external or on-die wirebond inductor).

[286] Figure 40 shows the implementation of a single-chip, asymptotically zero switching loss, power factor controller (PFC) using a dual inductor and control scheme, with a protective bridge-rectifying protective PFC on a chip. A boost-type adiabatic PFC is fed from an active bridge rectifier and the semi-regulated DC bus is fed to an adiabatic forward converter. Control circuits are not shown, but are easily determined from the previous step by step processes shown in Figure 39, together with the well known PFC boost topology and forward converter topologies.

[287] The circuits described here are two-stage switching method using one extra inductor but there is no reason why this concept cannot be extended to three stages with two extra inductors or n stages with n+1 inductors, each one adiabatically driving the next one. As an example, three stages with switches sized respectively at lx, 4x, 16x, would reduce dynamic consumption by 16x and only need two small inductors.

High Voltage Measurement Circuit

[288] Figure 41 shows the use of a ring oscillator, modulated by the voltage-dependent depletion capacitance. This provides a low power method of measuring very high voltages without needing high value resistors which are difficult to fabricate on chip.

[289] The ring oscillator's frequency is set by the capacitive loading which in turn is voltage dependent, because of the depletion thickness variation with voltage. The frequency, and indirectly, the voltage, is measured using a digital counter enabled for a set period of time.

[290] A matching 'capacitor' structure, with a fixed known voltage applied to it, serves as a reference frequency measurement against which the unknown voltage result is calibrated. M-I-S (Metal-Insulator-Semiconductor) Anodic Etching and/or MacEtching Using a Moving Platform

[291] We refer to Figure 42. In the following, where reference is made to metal, generally any conductor would suffice.

[292] When for example a microneedle array is used, making the needles negative makes them act like metal gates in a MOS structure. The wafer to be etched is N-type and a liquid serves as an insulator.

[293] With a voltage of say 10 volts, when the needle comes within about 500 nm of the silicon surface, the silicon will locally invert from N-type to P-type and holes will appear at the surface of the silicon. Because of the applied circuit voltage, the surface of the silicon will be anodically etched - similar to the way microporous silicon can be formed, but in this case holes are created by surface inversion.

[294] The microneedle array is positioned on a nanometer-accurate XYZ positioning table. A small oscillating X/Y movement of perhaps +/-100 nm can serve as mechanical agitation of the etching solution, although it will make the etched features this much larger. Z- oscillating motion can be used to form a piston-type pumping effect, to further improve circulation of etchant and effluent and maintain high etch rate.

[295] High frequency, possibly bipolar, electrical pulses rather than DC may reduce conduction losses in the HF and only allow for short pulses where the inversion layer is being etched compared to long times when it is recovering.

[296] The etch rate is set by the current, which in turn depends on the surface area being etched.

[297] This system could also be applied to a MacEtch version, which mechanically would work similar to the M-I-S etch, but now the microneedles would be plated with noble metal, the etching solution would be HF + H2O2 and no electrical supply would be required.

Isolated Base Driver Circuits Including IC for xSDBD

[298] We consider developments of the circuits of Figures 18d, 18e and 18f .

[299] All of the structures shown can be translated into 'ultra-lateral' versions according to the present invention, but will be drawn in the conventional way, assuming a double sided wafer.

[300] Dual base devices such as DSDBDs (double sided double base devices) and SSDBDs (single sided double base devices), collectively called XSDBDs, can be constructed as depletion mode JFETs, as described in WO 2014/122472 and US-A-2017/287721. [301] The sequence shown in Figure 43a-f provides an optimal base drive system for the configuration shown for a P wafer device. The polarity is +1000 V, but the circuit is not 'handed' and will work identically with -1000 V over the switching device if the CE1/BASE1 / CE2/BASE2 naming convention is reversed.

[302] The 'signal' transformer functions as a fundamental component for passing current from one end to the other end of the transistor while the third primary port pri is used, injecting base current and modulating between JFET and bipolar operating modes of the XSDBD. Very high currents may be present in the secondaries of the transformer, but generally only briefly during the switch-on and switch-off edges.

[303] The following sequence assumes a drive into the primary winding pri of the circuit, although as shown there is the option of a two-winding, not-fully-isolated system, with the drive waveform being imposed on one of the two windings seel or sec2 (seel is shown).

[304] Figure 43a shows the off condition, in which the main power transistor forms a JFET channel in which CE1 is the gate and BASE1, acting as the channel, might not be fully depleted but SW1 cuts off the conduction path.

[305] At the opposite end, SW2 connects the BASE2 which is the 'drain' end of the JFET to 0 V, which prevents the bottom PN junction from becoming forward biased.

[306] Figure 43b shows the majority carrier mode (JFET). At this point SW1 turns on and there is now a DC power path through the P region of the device, because the JFET path is not pinched off when BASE1 (the JFET source) connects to CE1. This power path involves the DC path of the transformer windings seel and sec2, but since the magnetization effect of these two windings is opposite, the transformer sees no increase in flux from this current and hence the effective inductance of this path is low.

[307] This, plus the lack of minority carrier conduction, allows a very fast ramp of current, ultimately limited by resistance of the wafer.

[308] Figure 43c shows the bipolar conduction mode. This mode dramatically reduces the resistance of the semiconductor path, by injection of minority carriers. It is possible to modulate the voltage between CE and BASE on both ends of the device from the primary port (or any other port), even in the presence of high common-mode current in the secondaries. This is because any delta imposed does not change the current through the P- wafer, since a voltage is added to both BASE1 and BASE2 .

[309] Current into the primary port only starts to rise when approaching and passing typically 0.5 V, whereupon the PN junctions can become forward biased. As shown in Figure 43c, a mismatch in currents between seel and sec2 occurs, as some of the hole current gets redirected to become a hole injection current into the CE2 terminal, producing emitted electrons in classic bipolar transistor action and stored charge in the silicon. These different currents pass out of CE2.

[310] Only this portion of current has to be provided by the primary drive circuit, which can therefore modulate conductivity of the overall transistor from the isolated primary port, elegantly moving between primarily majority, mixed-mode, and minority carrier mode.

[311] Figure 43d shows the saturation mode, which is an extension of the previous condition. If the drive current is increased and VBE approaches 0.75 V (at room temperature silicon), eventually the conductivity of the silicon is reduced so that both PN junctions become forward biased and saturation voltage can drop to 0.2 V or below at many hundreds of amps / cm 2 .

[312] Figure 43e shows desaturation. Returning to majority-carrier/ JFET mode is achieved by the reverse of the above process, i.e. lowering the primary drive voltage and therefore the current. Gradually the stored charge (hole/ electron) leaves the silicon. It is not essential to fully extinguish the minority-carrier injection, but at low voltage such as 0.5 V primary voltage the hole/ electron plasma density can be reduced to the point at which turn-off will be rapid, since most of the stored charge will have been removed. This occurs when the voltages VCEI and VCE2 are 2 V or greater.

[313] Figure 43f shows negative base turn-off bias. It is well known that BJT type devices turn off more quickly and are at a lower risk of second breakdown by using a negative base voltage. This can be provided through the transformer and will be detailed further below.

[314] Figure 43g shows that if the XSDBD device only needs to operate in unidirectional mode, then the concepts of a punchthrough drift region and a superjunction can be applied as shown.

[315] Figure 43h shows an AC switching superjunction. Even an AC switch can exploit superjunction and punchthrough to improve switching performance with the structure shown.

[316] Figure 43i is a simplified diagram of an example of a primary driver. A 15 V supply and a buck regulator produces a 1 V DC supply. A power driver can produce a low impedance output of 0 to 1 V at high slew rate, designated vbe. Either vbe or - (15 V- vbe) is applied to the primary using one of the drive_vbe or drive_neg_14V control signals respectively. The drive_neg_14V is pulsed low to cause the transformer to generate the negative pulse of Figure 43i, and this pulse should be on for long enough to cancel the volt*time product of the positive voltages used to drive the base power in order that the transformer does not saturate. A duty cycle of 95% is possible because of the ratio of typically 0.7 V to -14 V.

[317] Figure 43] is a simplified diagram of the secondary side of this example. The actual driver circuitry uses a MOSFET for swl and sw2, and this can be controlled using an auxiliary tap on the signal transformer. The positioning of the switch is slightly different to the previous sequence drawings but is effectively the same.

[318] Figure 44 shows further details of this arrangement. TR1 is the signal transformer, the primary drive of which is shown in Figure 43j.

[319] Figure 44a depicts one half of the secondary driver circuit - the other half, for the other end of the transistor, is not shown. MN1 is used to switch the BASE terminal in and out of circuit. When the transformer is activated in the forward direction, with perhaps vbe drive of 0.7 V, then MN1 should be switched on so the current can flow. The seven-turn auxiliary winding produces a positive voltage seven times larger than vbe drive and this is sufficient for MP1 to switch and store this voltage onto the gate of MN1, which is a low threshold type.

[320] When the negative -14 V is generated at the transformer, the main winding is tapped by zener diodes ZN3 and ZN2 to produce a negative -6 V to turn off the gate.

[321] When the driver is inactive (powered off) there is circuitry to automatically engage the switches using resistor Rl (as will be detailed later), and when the opposite CE terminal becomes negative, and the GATE pin becomes negative up to a clamp voltage of (locally) approx -57 V, MN1 acts as a source follower for this mode and is therefore very fast to slew.

[322] Although it is possible to build the circuit from discrete components, better results and internal protective circuits (see the detail of Figure 44a) are possible using a custom IC including low voltage threshold MOSFETs and it is possible to incorporate resistors, capacitors, diodes and zeners.

[323] Figure 44b shows how a four terminal packaged IC device can incorporate the circuitry needed.

[324] Figure 44c depicts a complete secondary-side system capable of control of the XSDBD. One custom IC is used for each end of the transistor.

[325] Resistor Rl assures that in the absence of power for the driver, the configuration of Figure 43a is the default, turning on sw2 and turning off swl by biasing the gate terminals of the ICs correctly. Capacitor CSPEED gives a speed-up factor for the unbiased operation. Part or all of CSPEED can be created from the parasitic interwinding capacitance of the secondary side windings.

Emitter Switched Device

[326] A common circuit to improve voltage rating and speed is a cascode, and a dual bipolar cascode is realisable as shown in Figure 44d. When the low voltage device turns off, an automatic negative reverse bias for the larger high voltage device develops, so that a -14 V or other negative supply is not required.

[327] Cascode bipolar devices, sometimes called ESBT (emitter switched bipolar transistor) or ESBC (emitter switched bipolar cascode) are highly immune to second breakdown, which allows for lower cost main power transistors, using coarser cell geometry which would otherwise be susceptible to second breakdown when not in cascode. These additional low voltage transistors can easily be made on the same substrate as the SSDBD.

SSDBD Mounting

[328] Figure 44e shows the mounting of a SSDBD where the power terminals CE1, CE2 are on the bottom of the die and the BASE connections are on the top.

XSDBD with Internal Auxiliary JFETs On-Die

[329] Figure 45 shows an XSDBD with internal auxiliary JFETs on-die. Compared to the previous drawings there is now an additional (auxiliary) JFET on each end (additional to the main power JFET path) but this is a low voltage N-channel JFET with a P-channel gate. Its purpose is to isolate the main larger P+ base connection of the power transistor whenever there is a negative polarity at the opposite end of the power transistor. By doing this it supports a very high pinchoff voltage for the main JFET and prevents unwanted turn-on when there no drive signal is present on the base driver transformer. These auxiliary JFETs can have a normally-on characteristic if desired, but this is not essential to the operation. SPICE Model

[330] Figure 45f is a schematic representation of a textual subcircuit that can potentially represent an XSDBD in the SPICE circuit simulator. There are many textual parameters which go into the .MODEL statements of the subcircuit elements which need to be 'tweaked' to get an accurate DC and temporally accurate model. These can be tuned automatically to fit data traces previously captured from a TCAD simulator or from measurements of an actual device. One such optimizer is called ASCO (http:/ / asco.sourceforge.net/). The result from multiple fitting runs will be a model with parameters which closely match the actual semiconductor device.

Active Full-Bridge Rectifier with Protective Functions using All NPN Structures

[331] Some of the concepts described with respect to Figure 28 are extended in Figures 46 and 47.

[332] A low cost solution is shown, using a single inductor and a master/ slave design for the multiple active rectifiers and ICs needed for a half or full bridge system. In the master there is only one SWA NMOS switch in the path of the full current, thereby reducing the I 2 R losses by a factor of four versus simply connecting together two-terminal active diodes.

[333] The SWB base current pulses are routed in turn to transistors Q2, Q4, Q5 or to transistors Ql, Q3, Q5, depending on the polarity of the mains AC to be rectified, and this occurs up to MHz time-share rates.

[334] A full bridge is shown, but the same idea works with half-bridge by omitting Q2, Q4 and IC3.

[335] This use of a single magnetic component in the boost circuit is possible because all of the transistors in the bridge rectifier have the same nominal current through them, and if the transistors are taken from the same manufacturing batch, they will match well - at high current densities and fully saturated the beta is constant with very different dopings.

[336] The full bridge scheme also would work for a full bridge high frequency bridge as used for a VFD (variable frequency motor drive inverter), not just a low speed bridge rectifier.

[337] The slave ICs only need to have switches SWB in them, and route the current pulses to the local transistor base after detecting and rectifying the VDD flyback event, which powers all the devices to between 3.3 V and 1.8 V, depending on the CMOS processes. These slave ICs can therefore be smaller and cheaper, because they only handle 2 A on average, instead of a full typical 20 A bridge current. Although there is an advantage to having the complete SWA, SWB switches in the slave (as described in connection with Figure 28, domain 1), with regards to magnetization current consistency in the core.

[338] Only a very basic synchronizing system is needed between the master and slave but data communication is still possible for more advanced devices.

[339] For a typical design, the voltage of vself_power to the boost converter might be 0.21 V, which equates to e.g. 4.2 W @ 20 A rectification current, and this must power BASE1, BASE2 and BASE3. At a typical 0.7 V at 2 A base current, each of three devices at B=10. The total voltage drop of the full bridge is 0.21 V + (75 mV *3) = 0.44 V for the full bridge or 0.22V/ diode, compared to a typical diode drop of 0.8 V to 1 V within a low cost commercial bridge rectifier.

[340] The Isamp node allows for monitoring of current in the bridge for control and protection purposes and is sampled immediately when the VDD pulse is issued. Additional samplers can be added to the BASE nodes and the combination of BASE (Vbe) voltage and current are indicative of die temperature on the power transistor and again could be used to cause a safety fault trip.

[341] Having a working VDD means the ICs can drive an LED status drive in order to indicate overcurrent, overvoltages, and/ or overtemperature, with various flashing patterns.

[342] Figure 47a includes more detail of the master I-MODE driver chip. The voltage dividers from the live and neutral shown in Figure 46 drive nodes vsensel and vsense2. These voltages are used directly on gates for VCBO rating FETs which will automatically clamp the BASE terminal of the transistors to the emitter with a low resistance switch when there is more than around 100 V across the transistor. This works even in the absence of VDD, preventing premature breakdown voltage of the transistor due to its gain into an otherwise open base connection. The vsensel, vsense2 inputs with the comparators can determine which polarity is to be rectified and the base pulses steered to the appropriate transistors. Finally, the sense voltage both gives the ability to prevent an overvoltage condition, by disabling the interrupter transistor if the AC peak voltage is too high, and can work as part of a progressive capacitor ramping (soft-start, inrush limiting) as in Figures 46c and 46d.

[343] Figure 47b is the timing diagram for the master/ slave scheme in which all of the devices use a shared magnetic path. Timing is achieved using on-chip oscillators, e.g. RC or ring oscillator based, and with the master and slave ICs being preferentially from the same batch, there would be good matching between the dies. A three slot timing sequence is used. tslotO begins with the master charging the inductor for approximately 66% of the tslot time. Then the inductor is released to provide a positive pulse seen in master and slave circuits and rectified to provide a local VDD at the appropriate voltage. A Schottky diode is shown inside the devices as the rectifier, but for CMOS process a P channel MOSFET could be used as an active rectifier to the same end.

[344] Identifying this VDD pulse, the slave resets its state machine to a known state (tslotO). Then, if its pol input is the correct polarity, it activates its switch SWB for a fixed amount of time (matched to the times generated in the master as mentioned earlier), injecting base current into its controlled transistor and thereby bringing the VCE of the controlled transistor down to around 75 mV or even less.

[345] The pulsed nature averages out over all 3 tslots to approximately 10% duty cycle or a forced beta of 10. When the slave turns off its SWB switch the voltage naturally jumps to VDD level, so the master, on the same magnetic circuit, can detect and move to tslotl.

[346] Note that the VDD pulse does not need to happen every three tslots, but can be very intermittent, only occuring at a rate to replenish the low-current VDD supplies. The state machines count off the rising edge of the dot winding signal and therefore only need occasional re-synchronization against the VDD pulses, which can be issued as part of a voltage regulation loop for VDD.

[347] In tslotl, the master again drives switch SWA with a fixed on-time and then a fixed off-time uses SWB1 or SWB2 (depending on the mains polarity) to turn on transistor Ql or Q2.

[348] For powering up, even without extra base current being injected from the I-MODE driver (i.e. the driver can be powered down), the substrate diodes as depicted in Figure 47a between Vss and BASEx mean that the transistors will automatically turn on in a diode mode at an overall 1.5 V (a combination of the substrate diode drop and transistor V e voltage). This ensures startup, since vself_power is in the conduction path and will soon get the nominal VDD voltage where the internal 'Schottky' causes a power up.

Alternative Construction of the Bridge

[349] To fit into a standard bridge-rectifier package, Figure 48 shows how, using devices mounted on both sides of a printed-circuit type substrate, a compact and low parasitic resistance and inductance (R and L) system can be made. The inductor is formed around the central mounting hole.

[350] Wafer-level 'balling' is a technique of attaching solder balls to a complete silicon wafer so that the singulated dies are directly solderable to a substrate. One machine which can perform this is from Packaging Technologies GmbH.

[351] A commercial device such as the NanoStar ® from Texas Instruments Inc. has a resistance per solder pad of approximately 1 ητΩ and an inductance of 21 pH for a 170 μιη diameter ball at a 500 μιη pitch.

Buck-Boost using Multitap Inductor

[352] A high volume application for a true bidirectional switch is in AC voltage regulation. Figure 49 is a working high-level simulation of the power conversion portion of the concept. A single inductor core is used, probably ferrite and probably gapped, because it works in magnetic-energy transfer (inductor) not transformer-action mode. On this core is wound a primary LI. Two secondaries L2 and L3 are shown for a centre-tapped scheme, whereas an alternative of a single winding and full-bridge switches is possible.

[353] To boost an mcoming AC voltage, use is made of S_BOOST while to reduce an AC voltage, use is made of S_BUCK.

[354] Operation is in two phases. In the first phase S_INPUT is activated for a portion of the switching cycle set by the parameter duty. During this time, current builds up in LI, the rate and the direction being determined by the instantaneous voltage at AC_IN and the Ip primary inductance.

[355] In the second phase, either S_BUCK or S_BOOST is activated for the remainder of the cycle, depending on whether the output is to be lower or higher than the input as desired. During this second phase, the magnetization current appears in the secondary winding at a ratio relative to the previous LI current, dependent on the turns ratio between L1:L2 or L1:L3, which need not be identical.

[356] The high frequency current waveforms are attenuated by capacitor CI.

[357] With a much higher switching frequency than mains frequency, the effective output voltage will be

Vout = Vin +/- duty/(l-duty) * Vi„ *turns_ratio.

Where turns_ratio is the number of turns on the primary divided by that on the secondary.

[358] The equation shows that it is possible to go from 0 to infinity at the output, but in practice a range of +/-50% is most easily achievable. One limit is on the voltage rating of SJNPUT:

V_S_INPUT_max = +/- Vin_peak * 1 /(1-duty).

[359] A control circuit (not shown) will implement a feedback loop to adjust the duty using feedback from a measure of the AC_OUT in the usual way.

[360] Compared to a simplistic buck regulator or a more complex buck/boost, the configuration here has several benefits. Firstly, only two switches need to be activated (out of the three present) to obtain either buck or boost. Secondly, peak current is reduced in the input-side power switch relative to a standard buck regulator, which must switch the full output current at sometime very low duty cycles. In this circuit, the current is reduced and the on- time extended because of the turns ratio between LI and L2/L3. This reduces switching and conduction losses accordingly. Thirdly, the output-side switches can be low voltage rated - depends on the maximum add/ subtract voltage required of the voltage regulator.

[361] As shown, this is a single phase unit, but it could beneficially be broken into multiple phase-offset units whose outputs are in parallel and whose inputs are connected together if the ripple currents are seen as problematic.

[362] A slight drawback is that the winding currents are fully switched and not continuous

- as with the flyback converter.

Totem-Pole PFCs using Adiabatic Techniques

[363] The techniques previously outlined for adiabatic PWM are applicable to the role of a Power-Factor-Controller boost system for a single or three phase AC to DC role. The well known configuration is in Figure 50a.

[364] The sub-diagrams of Figures 50b and c show the switch sequencing in a classic totem-pole PFC using diodes augmented here with transistor switches to eliminate the forward voltage drop. The "lowF" means that these switches only need to switch at a rate of 60 Hz. Phases A and B are the high frequency switch control signals. Only the switches on the left hand side of those sub-diagrams have to be high speed.

[365] The sub-diagrams of Figures 50d and e show an alternative control method, in which all four switches are capable of high speed operation.

[366] An adiabatic version using an extra inductor and pair of switches is shown in Figure 50f . This reproduces the operation of Figures 50b and c, but now the switching losses can be largely eliminated as has been explained in previous sections.

[367] Figure 50g simplifies Figure 50f for the case of a non-bidirectional power flow and each switch is shown as a BJT device. The adiabatic switch is only needed in the lowside but otherwise the operation is not different.

[368] Figure 51 shows a smart-power system of an integrated driver IC with a power transistor incorporating multiphase base drive wirebond inductors. The devices can incorporate protection (thermal, short circuit) functions and with the four-pin or higher packages can offer extra function such as isolated control input or current monitoring output.

[369] Following on from the above, Figure 52a shows circuits for emulating the capacitive input of a MOSFET/IGBT while initially powering and controlling the bipolar type transistor on the other side of the isolation barrier. At the low voltage gate side of the barrier, a control IC (previously shown in Figure 49) with integrated, typically CMOS, control electronics can drive a tiny transformer with bipolar magnetization pulses. A "turns ratio" exists between the primary and secondary so that the typically 10 V gate pulse is received at the other side of the transformer as a 3 V (typical) pulse. The presence or absence of pulses or their relative timing can convey on/ off or other information across the isolation barrier to the smart driver IC.

[370] On the high-voltage side of the barrier is an I-MODE control chip which is powered up by the pulse(s) generated from the primary side as rectified on the secondary side. The secondary-side power is augmented by the inductive boost system when the transistor is on, and by a JFET current source when the transistor is off.

[371] Figure 52b shows an alternative self-powered method to the JFET shown earlier. Here, a BJT and a feedback regulator are used. The beta of the power BJT device means a proportionally higher value of pull-up resistor - in this case 10 ΜΩ for a given self-power current. The NFET threshold working with the voltage divider sets the regulation voltage. The circuit's main function is to power up the driver IC when the power transistor is otherwise off.

[372] Figures 53 and 54 show methods of making transistor structures to use with the adiabatic power converters.

[373] Figure 53 shows the manufacture of a vertical transistor structure (rather than the 3D transistors described above) with a transparent emitter on the bottom side (similar to that used in a punchthrough IGBT). Instead of thinning the whole wafer as is usual, multiple cylindrical holes are formed, which when doped give the same effect as a thin wafer electrically but maintaining most of the mechanical strength of the original wafer.

[374] Figure 54 shows procedures for making a vertical power transistor (rather than the 3D transistors described before) and creating a wafer with ready made N+ "tubs" in which to form the transistors.

[375] First, X,Y grooves, 200 μιη deep, are cut on the top side of a 500 pm starting wafe,r using the dicing saw. Next, phosphorus diffusion is carried out atl250 °C for five days. Phosphorus diffuses from the bottom and top wafer surfaces and also from the surfaces exposed by the groove depth. The diffusion depth is much deeper than any possible saw damage. After grinding the front side down to the level shown, the final wafer is flat and 240 μιη thick, ready for forming transistors within. [376] The transistors will withstand high forward or reverse voltages and only a surface passivation is needed.

Universal Power Converter

[377] Figure 55 is a block diagram of a universal power converter featuring power factor control and isolation between two ports. Either a DC bus or a three-phase I/O port (seen on the right of the diagram) is at the left-side of the isolation transformer where two-way power can enter or leave the unit. On the right hand side of the isolation barrier, a three phase power I/O port is shown in more detail. The converter can buck or boost between the ports by changing the DC bus voltage which exists on both sides of the transformer, nominally 1200 V in this drawing. The I/O ports can be connected to three-phase AC power lines.

[378] Multiple taps on the transformer and power multiplexing provisions routes a portion of the transformer voltage span onto adiabatic PWM units. By selection of the correct multiplexing position and an appropriate PWM ratio then any voltage between 0 V and 1200 V in this example can be created at any port - essentially the transformer effective "turns- ratio" can be controlled from 0.0 to 1.0 looking from one direction or from 1/0.0 to 1/1.0 from the other direction, giving infinite possibilities of buck or boost.

[379] By centre-tapping at the 600 V point a neutral line can be created for either port. 1200 V, 0 V becomes +/-600 V with respect to neutral in this case.

[380] As shown, a capacitor is added to one of the Mux/ PWM ports and by controlling the rate of change of the effective turns-ratio then power can be pumped or pulled from the capacitor to maintain a power factor of 1.0 over each AC power cycle.

[381] Any number of ports can be created for example to add battery charge/ discharge ports.

Adiabatic Transformer Operation

[382] A transformer is driven with a square wave power waveform in an adiabatic fashion. The transformer can have hundreds of nanofarads directly across the winding or from each winding to ground.

[383] For the first cycle (a runt quarter-cycle) there is a loss of energy. +1000 V, 0 V is applied to the winding terminals respectively, taking a large amount of energy into the capacitor, never to be recovered.

[384] The winding is driven solidly in this manner for one quarter of a power cycle. During this time, the magnetization current is rising with a triangular ramp. After this quarter-cycle, the magnetization current will peak at a design point. This might be about 50 A (the transformer is gapped so it has a fairly low inductance and a deliberately high magnetization current).

[385] Next, the +1000 V, 0 V transistors are turned off. The magnetization current peak has been designed to be sufficient such that with all the transistors turned off, it can slew any attached capacitance and reverse the transformer from +1000 V, 0 V to 0 V,+1000 V without the aid of any active devices. The inductive energy achieves the slewing, with all transistors off.

[386] When the transformer winding has slewed to the 0 V,+1000 V, then the opposite pair of transistors are switched on to 'catch' the swing and hold it to the rails - timing is critical, but if diodes catch it the losses are still very small.

[387] At first the magnetization current is pushing power back to the supplies through 'catcher' switches, but one quarter of a cycle later (i.e. midway through the half cycle) it reaches zero before going on to reverse and by the end of this half-cycle it has peaked again in the opposite sign. The transistors can be turned off and let the magnetic components can be allowed to slew the edge back to the initial +1000 V, 0 V on the transformer terminals.

[388] As for the waveforms of subsequent cycles, these are energy-recycling so energy is simply moving from the capacitors to the inductors without being dissipated. This is akin to resonance, but here with trapeziodal square waves.

[389] Normal (bi-directional) power transformer action is not impacted, as while the transistors are on there is a 1:1 transformer power path between primary and secondary. The magnetic self-reversal happens when all the transistors are off i.e. when the transformer is decoupled from any inputs or outputs.

[390] Figure 56 is a simplified schematic of only the power transformer part of the system, not showing any extra tapping or PWM features.

[391] Figure 57 shows the operating waveforms at 14 kHz for a 125 kW, 1000 V transformer when everything is tuned correctly at zero load. The top traces are the primary voltages, the center traces are the transistor gate waveforms, and the bottom traces are the primary current and the current in one of the capacitors which is being adiabatically driven.

[392] Figure 58a shows what happens if the magnetizing current is not sufficient, due to either too high a magnetizing inductance or too short a cycle time. The same would happen if the load capacitance was too high. It can be seen from the slopes that they do not reach the target in time and it takes a spike of current from the supplies to charge the capacitor. This is disadvantageous because it uses much power when not running adiabatically in this way. [393] Figure 58b represents the other direction of possible out-of-tune condition. The ramps rise too quickly and hit the clamp diodes before the power switches are engaged. Of the two conditions, this is the least lossy but still losses are higher due to the forward voltage of the clamp diodes.

[394] In summary, as well as other benefits, the main effectiveness of the ultra-lateral concept of the present invention versus a thin-wafer vertical device can be seen by way of an example device. Assume a wafer thickness of 500 μηι and with a lateral drift region length of 75 μηι - typical for a 600 V device - and assuming 50 μηι length overhead for the CE and base regions (giving a 125 μηι ring pitch), then a 1 cm 2 area of power device would yield a cross- sectional conduction path area of 400 mm 2 rather than the 100 mm 2 of conduction path area for a vertical device. In other waords, the device achieves 4 cm 2 of transistor area for 1 cm 2 of silicon area. Some of the die area could be given over to sophisticated driver and protection circuitry and still result in a smart-power IC of smaller dimensions and lower cost than current 'dumb' transistors.