DEVICES AND THEIR METHODS OF FABRICATION

TECHNICAL FIELD

[0001] Embodiments of the invention are in the field of integrated circuit fabrication and, in particular, layered oxygen barrier electrodes for resistive random access memory (RRAM) devices and their methods of fabrication.

BACKGROUND

[0002] For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. It has become increasingly significant to rely heavily on innovative fabrication techniques to meet the exceedingly tight tolerance requirements imposed by scaling.

[0003] Non-volatile embedded memory with RRAM devices, e.g., on-chip embedded memory with non-volatility can enable energy and computational efficiency. However, the technical challenges of creating an appropriate stack for fabrication of RRAM devices that exhibit high device endurance, high retention and operability at low voltages and currents presents formidable roadblocks to commercialization of this technology today. Specifically, the objective of memory technology to control tail bit data in a large array of memory bits necessitates tighter control of the variations in voltage break down of the switching layer and switching events in individual bits. Furthermore, in filamentary RRAM systems, the latter is dictated by controlling movement of oxygen vacancy which is widely understood to drive filament formation and dissolution in metal oxide films. As such, significant improvements are still needed in the area of RRAM stack engineering. This area of process development is an integral part of the non-volatile memory roadmap.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 A illustrates a cross-sectional view of a resistive random access memory

(RRAM) cell formed on a conductive interconnect and a first dielectric layer, and surrounded by a dielectric spacer and a second dielectric layer, in accordance with an embodiment of the present invention. [0005] Figure IB illustrates a cross-sectional view of a stack of three conductive layers, in accordance with an embodiment of the present invention.

[0006] Figure 2A illustrates a cross-sectional view of a resistive random access memory

(RRAM) cell formed on a conductive interconnect where a top electrode includes a stack of conductive layers, in accordance with an embodiment of the present invention.

[0007] Figure 2B illustrates a cross-sectional view of a stack of four conductive layers, in accordance with an embodiment of the present invention.

[0008] Figure 3 illustrates a cross-sectional view of a resistive random access memory

(RRAM) cell formed on a conductive interconnect where a top electrode and a bottom electrode include a stack of conductive layers, in accordance with an embodiment of the present invention.

[0009] Figures 4A-4G illustrate cross-sectional and plan views representing various operations in a method of fabricating an RRAM device integrated on a conductive interconnect, which may be used to fabricate a memory device such as described in association with Figure 1 A, in accordance with an embodiment of the present invention.

[0010] Figure 4A illustrates a conductive interconnect surrounded by a first dielectric layer and a bottom electrode layer formed on the conductive interconnect.

[0011] Figure 4B illustrates the structure of Figure 4 A following the formation of an oxygen exchange layer on the conductive interconnect, and a switching layer on the oxygen exchange layer, in accordance with an embodiment of the present invention.

[0012] Figure 4C illustrates the structure of Figure 4B following an etch process used to pattern the dielectric hardmask layer and an RRAM material layer stack to form an RRAM device.

[0013] Figure 4E illustrates the structure of Figure 4D following the formation of a dielectric spacer layer laterally adjacent to sidewalls of the RRAM device and laterally adjacent the patterned dielectric hardmask layer.

[0014] Figure 4F illustrates the structure of Figure 4E following formation of a second dielectric layer surrounding the resistive random access memory device and the dielectric spacer, and on the first dielectric layer.

[0015] Figure 4G illustrates a plan view of an array of RRAM devices of the type illustrated in Figure 4F, in accordance with an embodiment of the present invention.

[0016] Figures 5A illustrates an I-V plot, demonstrating concepts involved with filament formation and voltage cycling (reading and writing) in an RRAM device, in accordance with embodiments of the present invention.

[0017] Figure 5B illustrates a cross-sectional view of a conductive filament formed in an RRAM device, in an accordance with an embodiment of the present invention. [0018] Figure 5C illustrates a cross-sectional view of an RRAM device where the conductive filament is broken, in an accordance with an embodiment of the present invention.

[0019] Figure 6 illustrates a cross-sectional view of an RRAM element coupled to a drain side of a select transistor, in accordance with an embodiment of the present invention.

[0020] Figures 7A-7E illustrate schematic views of several options for positioning an

RRAM element in an integrated circuit, in accordance with embodiments of the present invention.

[0021] Figure 8 illustrates a block diagram of an electronic system, in accordance with embodiments of the present invention.

[0022] Figure 9 illustrates a computing device in accordance with embodiments of the present invention.

[0023] Figure 10 illustrates an interposer that includes one or more embodiments of the invention. DESCRIPTION OF THE EMBODIMENTS

[0024] Layered oxygen barrier electrodes for resistive random access memory (RRAM) devices and their methods of fabrication are described. In the following description, numerous specific details are set forth, such as novel structural schemes and detailed fabrication methods in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known features, such as switching operations associated with embedded memory, are described in lesser detail in order to not unnecessarily obscure embodiments of the present invention. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

[0025] Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as "upper", "lower", "above", and "below" refer to directions in the drawings to which reference is made. Terms such as "front", "back", "rear", and "side" describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

[0026] Integrating a non-volatile memory device such as an RRAM device onto an access transistor enables the formation of embedded memory for system on chip or for other applications. However, integrating a new memory device onto an access transistor while decreasing memory cell footprint presents its own set of challenges. In this regard, a class of RRAM devices that depend on creation and dissolution of a conductive filament is sought after for its relative ease of fabrication and potential to scale down to dimensions of 30nm or less. Additionally, RRAM devices have attractive device features such as low current and voltage operation. However, RRAM devices face several challenges from the perspective of memory operation. Examples of such challenges include controlling migration of oxygen into electrodes, switching layers and other critical layers during fabrication and during operation. Any or all of these challenges can adversely impact the advantages offered by an RRAM device in the first place. However, with innovative fabrication techniques, practical challenges such as controlling adverse oxygen migration effects can also be overcome.

[0027] In accordance with embodiments of the present invention, a resistive random access memory (RRAM) device includes a bottom electrode disposed above a substrate, a top electrode disposed above the first electrode, an oxygen exchange layer disposed between the bottom electrode and the top electrode and a switching layer disposed between the bottom electrode and the top electrode. In an embodiment, the top electrode includes at least two conductive layers, such as a bilayer stack of a first conductive layer and a second conductive layer disposed on the first conductive layer, where the second conductive layer has grain boundaries that are offset from grain boundaries of the first conductive layer. In an embodiment, the second conductive layer includes a different material from a material of the first conductive layer. In an embodiment, offset in the grain boundaries between the two conductive layers can help prevent oxygen atoms from migrating into the switching layer or the oxygen exchange layer of the RRAM device from adjacent layers. Controlling oxygen migration can help improve reliability and switching characteristics of RRAM devices.

[0028] In an embodiment, the oxygen exchange layer is disposed on the bottom electrode, the switching layer is disposed on the oxygen exchange layer and the top electrode is disposed on the switching layer. In an embodiment, the top electrode includes the bilayer stack of first and second conductive layers having different grain boundaries, and the bottom electrode includes a single conductive layer of a material such as TiN. In an embodiment, the first conductive layer incudes a material such as TiN, the second conductive layer includes a material such as TaN and the bottom electrode includes a single layer of a material such as TiN. In an embodiment, an uppermost surface of the top electrode having a bilayer stack of conductive layers may be adjacent to a source of oxygen but, can still prevent oxygen from migrating from the uppermost surface to the switching layer due to the presence of offset grain boundaries. In an embodiment, the bottom electrode includes the stack of first and second conductive layers having different grain boundaries, or different materials and the top electrode includes a single layer of a material such as TiN or TaN. In an embodiment, a lower most surface of a bottom electrode having a stack of conductive electrodes with offset grain boundaries may be adjacent to a source of oxygen but, can prevent oxygen from migrating from the lowermost surface of the bottom electrode to the oxygen exchange layer.

[0029] In some circumstances it may be more advantageous to have the oxygen exchange layer be further away from the bottom electrode. In an embodiment, the switching layer is disposed on the bottom electrode, the oxygen exchange layer is disposed on the switching layer and the top electrode is disposed on the oxygen exchange layer. In an embodiment, the bottom electrode includes a bilayer stack of first and second conductive layers with offset grain boundaries and the top electrode includes a single conductive layer. In an embodiment, a lower most surface of bottom electrode including a bilayer stack of conductive layers with offset grain boundaries may be adjacent to a source of oxygen but, can prevent oxygen from migrating from the lowermost surface of the bottom electrode to the switching layer.

[0030] In another embodiment, the bottom electrode includes a first stack of conductive layers and the top electrode includes a second stack of conductive layers as will be discussed in Figure 3.

[0031] Control of oxygen migration from the uppermost surface of the top electrode or from the lower most surface of the bottom electrode into either the switching layer or the oxygen exchange layer can help to reduce variability in RRAM device parameters such as filament forming voltage, switching voltage and current, device endurance and reliability. It is to be appreciated that memory technology relies on a very large array of discrete RRAM devices. Hence uniform behavior in filament forming voltage, switching voltage and switching current in important to preventing potential erroneous programming states in the RRAM device array.

[0032] The forming voltage, VF, is the voltage required to initiate cycling of the RRAM device from a high resistance state to a low resistance state and depends partially on the quality of the switching layer and the oxygen exchange layer. When a forming voltage is applied between the bottom electrode and the top electrode of the RRAM device, a filament is formed in the switching layer by movement of oxygen vacancies. The filament, once formed provides a path for current to flow. The oxygen exchange layer helps to initiate filament formation by scavenging oxygen from the switching layer, thereby creating oxygen vacancies in the switching layer even before any forming voltage is applied. In essence, the oxygen exchange layer helps to reduce the amount of voltage required to form a filament through the existence of oxygen vacancies in the switching layer. However, if the switching layer is directly below an oxidized top electrode then the oxygen scavenged by the oxygen exchange layer in the switching layer can be replaced by oxygen from the oxidized top electrode. Hence, forming a filament in the switching layer would require a proportionally larger forming voltage because a portion of the forming voltage would go into creating oxygen vacancies in the first place. A larger forming voltage can damage the switching layer or create a large filament. To dissolve and reconstruct a large filament during RRAM device operation requires a larger voltage than to dissolve and reconstruct a smaller filament. Thus in an embodiment, the top electrode layer having two conductive layers with offset grain boundaries and or different materials can help to mitigate the problems stemming from having an oxidized top electrode adjacent to the switching layer.

[0033] In an embodiment, the bottom electrode layer having two conductive layers with offset grain boundaries and or different materials can help to mitigate the problems stemming from having an oxidized bottom electrode that is adjacent to the switching layer.

[0034] Figure 1 A illustrates a cross-sectional view of an RRAM device 100, with a top electrode 108 that includes a stack of conductive layers, in accordance with an embodiment of the present invention. The RRAM device 100 further includes a bottom electrode 102 disposed above a conductive interconnect structure 160, an oxygen exchange layer 104 disposed on the bottom electrode 102, and a switching layer 106 disposed on the oxygen exchange layer 104. The top electrode 108 is disposed on the oxygen exchange layer 104. In an embodiment, the top electrode 108 includes a first conductive layer 108 A and a second conductive layer 108B disposed on the first conductive layer 108 A and the bottom electrode 102 includes a single conductive layer. In an embodiment, the first conductive layer 108 A has grain boundaries 120 A and the second conductive layer 108B has grain boundaries 120B. In an embodiment, the first conductive layer 108 A has grain boundaries 120 A and the second conductive layer 108B has grain boundaries 120B that are offset from the grain boundaries of the first conductive layer 108 A as shown in the enhanced cross sectional illustration of Figure 1 A. In an embodiment, the grain boundaries 120A and 120B extend in a direction that is approximately transverse to the horizontal axis of the RRAM device 100. In an embodiment, the grain boundaries 120A and 120B are nearly vertical.

[0035] In an embodiment, the first conductive layer 108 A and the second conductive layer 108B are a same material such as TiN, but the grain boundaries in second conductive layer 108B are offset from grain boundaries 120A of the first conductive layer 108A. In an embodiment, the first conductive layer 108 A includes a layer of a nearly amorphous TiN having grain boundaries 120 A and the second conductive layer 108B includes a layer of crystalline TiN having well defined grain boundaries 120B that are offset from the grain boundaries 120 A.

[0036] In an embodiment, the first conductive layer 108 A includes a metal such as but not limited to W, Ru, Ti or Ta or a compound such as but not limited to WN, TiN or TaN. In an embodiment, the second conductive layer 108B includes a metal such as but not limited to W, Ru, Ti or Ta or a compound such as WN, TiN or TaN.

[0037] In an embodiment, the first conductive layer 108 A and the second conductive layer 108B include a different material. In an embodiment, the first conductive layer 108 A includes a layer of TiN and the second conductive layer 108B includes a layer such as TaN. In an embodiment, the first conductive layer 108 A includes a layer of TiN having grain boundaries 120A and the second conductive layer 108B includes a layer of TaN having grain boundaries 120B that are offset from the grain boundaries 120 A.

[0038] In an embodiment, the bottom electrode 102 includes the first conductive layer 108 A and the second conductive layer 108B disposed on the first conductive layer 108 A, and the top electrode 108 includes a single conductive layer (not shown).

[0039] In an embodiment, a third conductive layer 108C is disposed on the second conductive layer 108B as illustrated in Figure IB to reduce chances of forming overlapping grain boundaries. It is to be appreciated, that the grain boundaries 120A in the first conductive layer 108 A may overlap with the grain boundaries 120B in the second conductive layer 108B in some portions. Overlap of grain boundaries will create a continuous channel for any oxygen atom to diffuse across a vertical extent of the top electrode 108. The enhanced cross-sectional illustration of Figure IB shows an interface 119 between the first conductive layer 108 A and the second conductive layer 108B where at least one grain boundary line in the first conductive layer 108 A overlaps with at least one grain boundary line of the second conductive layer 108B. By forming a third conductive layer 108C having grain boundaries 120C that are substantially offset from the grain boundaries 120B of the second conductive layer 108B, any continuity in grain boundaries between the second conductive layer 108B and the first conductive layer 108 A may be broken.

[0040] In an embodiment, the third conductive layer 108C includes a different material than the material of the second conductive layer 108B. In an embodiment, the third conductive layer 108C includes a different material than the material of the second conductive layer 108B and the material of the first conductive layer 108 A. In an embodiment, third conductive layer 108C includes a metal such as Pt, Pd, W, Ru, Ti or Ti, or a compound such as but not limited to TiN, TaN or WN.

[0041] In order to reduce potential overlap in grain boundaries along a vertical extent of the top electrode 108, the top electrode 108 can include a multilayer stack of conductive electrodes. In an embodiment, a multilayer stack including 4 or more conductive layers, or a repeated stack of multilayers as will be discussed in Figure 2A.

[0042] In an embodiment, the top electrode 108 has a total combined thickness that is between lOnm-lOOnm. In an embodiment, embodiment, the first conductive layer 108A has a thickness that ranges from 2nm-20nm and the second conductive layer 108B has a thickness that ranges from 2nm-20nm. In an embodiment, third conductive layer 108C has a thickness that ranges from 4nm-50nm.

[0043] In an embodiment, the bottom electrode 102 includes a single layer of a material such as but not limited to titanium nitride, tantalum, tantalum nitride, tungsten or ruthenium. In an embodiment, the bottom electrode 102 has a thickness in the range of 30nm-100nm. In an embodiment, the bottom electrode 102 has an amorphous composition and a thickness between 50nm-75nm to meet specific device attributes such as series resistance, programming voltage and current.

[0044] In an embodiment, the oxygen exchange layer 104 acts as a source of oxygen vacancy, Vo, or as a sink for O ^2" . In an embodiment the oxygen exchange layer 104 is composed of a metal such as but not limited to, hafnium, tantalum or titanium. In an embodiment, the oxygen exchange layer 104 has a thickness in the range of 5-20nm.

[0045] In an embodiment, the switching layer 106 is composed of a metal (M), such as but not limited to, hafnium, tantalum or titanium. When the metal (M) of the switching layer 106 is titanium, hafnium, or tantalum having an oxidation state +4, the switching layer 106 has a chemical composition, MOx, where O is oxygen and X is or is substantially close to 2. When the metal (M) of the switching layer 106 is tantalum having an oxidation state +5, the switching layer 106 has a chemical composition, M ₂ Ox, where O is oxygen and X is or is substantially close to 5. In an embodiment, the switching layer 106 is highly stoichiometric. In an

embodiment, the switching layer 106 is sub-stoichiometric. A sub-stoichiometric switching layer, is inherently devoid of oxygen atoms. The percentage of missing oxygen atoms is less than 0.2% of the total oxygen atoms in a fully stoichiometric switching layer. In an embodiment, the switching layer 106 has a thickness approximately in the range of 1-5 nm.

[0046] In an embodiment, the oxygen exchange layer 104 includes a metal that is the same metal (M) in the switching layer 106. In an embodiment, when the switching layer 106 includes an oxide such as Hf02, the oxygen exchange layer 104 includes a hafnium metal. In another embodiment, the oxygen exchange layer 104 includes a metal that is different from the metal (M) of the switching layer 106. In an embodiment, when the switching layer includes an oxide such as Hf02, the oxygen exchange layer 104 includes a metal such as Ti, Ta or Hf. In an embodiment, the oxygen exchange layer 104 has a thickness that is at least two times the thickness of the switching layer 106. In another embodiment, the oxygen exchange layer 104 has a thickness that is equal to the thickness of the switching layer 106. In an embodiment, oxygen the exchange layer 104 has a thickness that is equal to the thickness of the switching layer 106 in order to scavenge sufficient 0 ₂ from the switching layer. In an embodiment, the switching layer has a thickness of 3nm and the oxygen exchange layer 104 has a thickness of 3nm.

[0047] Referring again to Figure 1 A, a dielectric spacer 1 14 is disposed adjacent to the sidewalls of the oxygen exchange layer 104, adjacent to sidewalls of the top electrode 108 and on the switching layer 106. The dielectric spacer 1 14 extends from an uppermost surface of the dielectric layer 122 to an uppermost portion of the top electrode 108. In an embodiment, the dielectric material of the dielectric spacer 1 14 is a non-oxygen-containing material such as but not limited to carbon doped silicon nitride or silicon nitride. In an embodiment, the dielectric spacer 1 14 has a thickness that ranges from 30-60nm. A second dielectric layer 1 16 is disposed laterally adjacent to the dielectric spacer 1 14. In an embodiment, an uppermost surface of the second dielectric layer 1 16 is coplanar or sufficiently coplanar with an uppermost surface of the dielectric spacer 1 14 and an uppermost surface of the top electrode 108.

[0048] Referring again to Figure 1 A, the conductive interconnect structure 160 is disposed above a substrate 101 and includes a conductive interconnect 121 such as a conductive line or via. The conductive interconnect 121 is disposed within a dielectric layer 122 disposed above the substrate 101. In an embodiment, the conductive interconnect 121 has an uppermost surface that is coplanar or substantially co-planar with an uppermost surface of the dielectric layer 122. In an embodiment, the conductive interconnect 121 includes a barrier layer, such as tantalum nitride, and a fill material, such as copper, as is known in the art. In an embodiment, the dielectric layer 122 includes dielectric materials such as but not limited to, silicon dioxide (S1O2), carbon doped oxide (CDO), silicon nitride, organic polymers such as

perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. In an embodiment, the total thickness of dielectric layer 122 may be in the range of 1000A - 3000A. In an embodiment, the substrate 101 includes a suitable semiconductor material such as but not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as similar substrates 101 formed of other semiconductor materials such as germanium, silicon germanium or a suitable group III-V compound. Devices such as access transistors may be formed on the substrate 101.

[0049] In an embodiment, the conductive interconnect 121 has a width, Wei, that is less than a width, WBE, of the bottom electrode 102 as illustrated in Figure 1 A. In one such embodiment, an uppermost portion of the dielectric layer 122 is in direct contact with the bottom electrode 102. When the dielectric layer 122 includes an oxygen containing material, oxygen can migrate from the dielectric layer 122 and penetrate into the bottom electrode 102. However, when the bottom electrode 102 includes the first conductive layer 108 A and the second conductive layer 108B with offset grain boundaries oxygen migration can be mitigated even if the dielectric layer 122 contains oxygen.

[0050] Figure 2A illustrates a RRAM device 200 disposed above the conductive electrode 160, where a top electrode 208 disposed on the switching layer 106 is a multilayer. In an embodiment, the multilayer includes a first bilayer stack and a second bilayer stack disposed on the first bilayer stack. In an embodiment, the first and second bilayer stacks each include a first conductive layer 208A and a second conductive layer 208B disposed on the first conductive layer 208A. In an embodiment, the first and second conductive layers, 208A and 208B have grain boundaries that are offset from each other. In an embodiment, at least one grain boundary of the first conductive layer 208A is aligned with the grain boundary of the second conductive layer 208B and forms a continuous grain boundary chain across the two conductive layers. By forming the second bilayer stack on the first bilayer stack, the continuous grain boundary chain may be broken. In an embodiment, the top electrode 208 may include more than 2 bilayer stacks. In an embodiment, the number of bilayer stacks ranges from 3-15.

[0051] In an embodiment, the first conductive layer 208A includes a material selected from the group consisting of Pt, Pd, W, Ru, Ti, WN, TiN or TaN and the second conductive layer 208 A includes a material selected from the group consisting of Pt, Pd, W, Ru, Ti, WN, TiN or TaN. In an embodiment, the first conductive layer 208A includes a same material as the material of the second conductive layer 208A. In an embodiment, the first conductive layer 208A includes a different material from the material of the second conductive layer 208A. In an embodiment, the first conductive layer 208A includes a TiN and the second conductive layers 208A and 208B includes a TaN.

[0052] In an embodiment, the combined total thickness of the top electrode 208 is between 40nm-100nm. In an embodiment, the first and the second conductive layers 208A, 208B, each have thicknesses between 2nm-10nm. In an embodiment, each of first and the second conductive layers 208A, 208B, respectively have similar thicknesses. In an embodiment, each of the first and the second conductive layers 208A, 208B, respectively, have dissimilar thicknesses.

[0053] Figure 2B illustrates a RRAM device 201 disposed above the conductive electrode 160, where a top electrode 210 is a multilayer including a first tri-layer stack and a second tri-layer stack disposed on the first tri-layer stack. In an embodiment, the first and second tri-layers each include a first, second and a third conductive layer 208A, 208B and 208C, respectively as shown in the cross sectional illustration of Figure 2B.

[0054] In an embodiment, the tri-layer stack including the first, second and the third conductive layer 208A, 208B and 208C, respectively are substantially similar to the first conductive layer 108 A, second conductive layer 108B and the third conductive layer 108C, respectively described above in association with Figure IB. In an embodiment, the first conductive layer 208A is TiN, the second conductive layer 208B is TaN and the third conductive layer 208C is W. In an embodiment, the first conductive layer 208A is an amorphous TiN, the second conductive layer 208B is a crystalline TiN and the third conductive layer 208C is TaN.

[0055] In an embodiment, the top electrode 210 may include a first tri-layer stack having three distinct first, second and third conductive layers 208A, 208B and 208C, respectively, and a second tri-layer stack having three distinct conductive layers, where none of the first, second and third conductive layers 208A, 208B and 208C, respectively, in the first tri-layer stack are repeated in the second tri-layer stack (not shown). In one such embodiment, the top electrode 210 includes 6 distinctive layers of conductive electrodes.

[0056] In another embodiment, the top electrode 210 may include a first tri-layer stack having three distinct first, second and third conductive layers 208A, 208B and 208C,

respectively, and a second tri-layer stack having at least two distinctive conductive layers chosen from the first, second and third conductive layers 208A, 208B and 208C, respectively. In one such embodiment, when two similar conductive layers are stacked in the second tri-layer stack, the two similar conductive layers are not disposed directly adjacent to each other. In one such embodiment, if the second tri-layer stack includes two layers of the first conductive layer 208A and one layer of second conductive layer 208B, then the second conductive layer 208B will be disposed between the two layers of the first conductive layer 208A. Such an arrangement can help to maintain offsets in grain boundaries between each of the conductive layers.

[0057] In an embodiment, the top electrode 210 may include more than 2 tri-layer stacks.

In an embodiment, the number of tri-layers stacks ranges from 3-15, having various permutations of the different conductive layers.

[0058] In other embodiments, the top electrode 210 may include a multilayer where 4 or more conductive layers are successively stacked in order to reduce the possibility of forming a channel for oxygen diffusion through the top electrode.

[0059] Figure 3 illustrates a cross-sectional view of an RRAM device 300 where the top electrode 308 includes a stack, such as a bilayer stack of conductive layers and a bottom electrode 302 includes a second stack, such as a second bilayer stack of conductive layers, in accordance with an embodiment of the present invention.

[0060] In an embodiment, the first bilayer stack of conductive layers in the top electrode

308 includes a first conductive layer 308 A and a second conductive layer 308B, such as the first conductive layer 108 A and second conductive layer 108B, respectively described above in association with Figure 1 A. In an embodiment, the first conductive layer 308 A includes a compound such as TiN and the second conductive layer 308B includes a metal such as Ti. In an embodiment, the first conductive layer 308 A and the second conductive layer 308B have grain boundaries that are offset from one another.

[0061] In an embodiment, the bottom electrode 302 includes a second stack of conductive layers including a first conductive layer 302 A and a second conductive layer 302B to provide a bottom oxygen diffusion barrier. In an embodiment, the grain boundaries of the second conductive layer 302B are offset from the grain boundaries of the first conductive layer 302 A. In an embodiment, the first conductive layer 302 A and the second conductive layer 302B each include a similar material such as TiN, where the grain boundaries are offset from each other.

[0062] It is to be appreciated that the number of conductive layers and choice of materials in the bottom electrode 302 can be independent of the number of conductive layers and choice of materials in the top electrode 308. In an embodiment, the bottom electrode 302 can include two conductive layers with offset grain boundaries and the top electrode 308 can include three conductive layers, each with grain boundaries that are offset from one another.

[0063] In an embodiment, the top electrode 308 has a total thickness that is similar to the total thickness of the bottom electrode 302. In another embodiment, the top electrode 308 has a total thickness that is different from the total thickness of the bottom electrode 302. In an embodiment, the total combined thickness of all the conductive layers in the top electrode 308 is between 50-1 OOnm. In an embodiment, the total combined thickness of all the conductive layers in the bottom electrode 308 is between 30-100nm.

[0064] Figures 4A-4F illustrate cross-sectional views representing various operations in a method of fabricating an RRAM device integrated on a conductive interconnect, which may be used to fabricate a memory device such as is described in association with Figure 1 A, in accordance with an embodiment of the present invention.

[0065] Figure 4A illustrates a conductive interconnect 402 surrounded by a first dielectric layer 404 formed above a substrate 400 and the formation of a bottom electrode on the conductive interconnect 402. In an embodiment, the conductive interconnect 402 is formed in a first dielectric layer 404 by a damascene or a dual damascene process that is well known in the art. In an embodiment, the conductive interconnect 402 includes a barrier layer, such as tantalum nitride, and a fill metal, such as copper, tungsten or ruthenium. In an embodiment, the conductive interconnect 402 is fabricated using a subtractive etch process when materials other than copper are utilized. In an embodiment, the first dielectric layer 404 includes a material such as but not limited to silicon dioxide, silicon nitride, silicon carbide, or carbon doped silicon oxide. In an embodiment, the first dielectric layer 404 has an uppermost surface substantially co-planar with an uppermost surface of the conductive interconnect 402. In an embodiment, the first dielectric layer 404 has a total thickness between 1500A - 3000A. In an embodiment, conductive interconnect 402 is electrically connected to a circuit element such as a transistor (not shown).

[0066] In an embodiment, the bottom electrode layer 405 is blanket deposited onto on an uppermost surface of the conductive interconnect 402 and on an upper most surface of the first dielectric layer 404. In an embodiment, the bottom electrode layer 405 is deposited using a physical vapor deposition (PVD) process or a plasma enhanced chemical vapor deposition (PECVD) process. In an embodiment, the bottom electrode layer 405 includes a metal such as but not limited to W, Ru, Ti or Ta or a compound such as but not limited to WN, TiN or TaN. In an embodiment, the bottom electrode layer 405 is deposited to a thickness between 30nm to 50nm.

[0067] In an embodiment the bottom electrode layer 405 is first blanket deposited on an uppermost surface of the conductive interconnect 402 and on an upper most surface of the first dielectric layer 404, and subsequently polished to achieve a surface roughness of 1 nm or less. In an embodiment, the planarization process includes a chemical mechanical polish (CMP) process to form a topographically smooth uppermost surface having a surface roughness. A surface roughness of less than 1 nm is sufficient to enable various layers of the RRAM material layer stack 420 to be sufficiently free of any surface defects. Reducing surface roughness and defects using a CMP process may offer advantages during cycling of an RRAM device, such as reducing abrupt filament nucleation and reducing uncontrolled breakdown at low operating voltages, such as below IV. Reducing abrupt filament nucleation and uncontrolled breakdown at low voltages (less than IV) can prevent erratic switching and also lessen variation in switching voltage in a large array of RRAM devices. In an embodiment, when the bottom electrode layer 405 has been polished a wet chemical cleaning process is performed to ensure that that an uppermost surface of the bottom electrode layer 405 is sufficiently free of any contaminants.

[0068] Figure 4B illustrates a cross-sectional view of the structure in Figure 4A following the formation of an oxygen exchange material layer 407 and a switching material layer 409, in an accordance with an embodiment of the present invention.

[0069] An oxygen exchange material layer 407 is deposited on the bottom electrode layer

405. In an embodiment, the oxygen exchange material layer 407 is blanket deposited using a PVD metal deposition process. In an embodiment, the oxygen exchange material layer 407 includes a metal such as but not limited to Ti, Ta, W or Hf. In an embodiment, an additional pre- clean of the surface of the bottom electrode layer 405 is performed using an Ar sputter clean, immediately prior to deposition of the oxygen exchange material layer 407. In an embodiment, the oxygen exchange material layer 407 is deposited in-situ after forming the bottom electrode layer 405. In one such embodiment, the bottom electrode layer 405 and the oxygen exchange material layer 407 are deposited by a PVD process.

[0070] A switching material layer 409 is deposited on the uppermost surface of the oxygen exchange material layer 407. In an embodiment, the switching material layer 409 includes an oxide of a metal such as but not limited Ti, Hf, Ta, Zr or W. In an embodiment, the switching material layer 409 is deposited immediately after formation of the oxygen exchange material layer 407 and without an air break. Eliminating an air break can help avoid nonuniform surface oxidation of the oxygen exchange material layer 407.

[0071] In one embodiment, the switching material layer 409 is deposited using a reactive sputter deposition process. The reactive sputter deposition process utilizes a controllable oxygen flow during a metal deposition process resulting in a sub-stoichiometric metal oxide switching material that is oxygen deficient. In an embodiment, the oxygen flow rate is varied during the deposition process leading, to an oxygen concentration gradient within the resulting sub- stoichiometric switching material. A higher oxygen concentration near an oxygen exchange material layer 407 interface will help to scavenge the O ^2" from the sub-stoichiometric layer during an annealing process leading to the formation of oxygen vacancies, V ₀ . Enhanced formation of oxygen vacancies can lead to lower forming voltages and consequently smaller filament sizes in the switching material layer 409.

[0072] In another embodiment, there is no oxygen concentration gradient in the switching material layer 409 and the resultant metal oxide is highly stoichiometric. In an embodiment, the switching material layer 409, may be formed using an ALD process. The ALD process may be characterized by a slow and a highly controlled deposition rate of the switching material layer 409. The ALD process may be highly uniform (e.g., approximately 0. lnm level variation) as well as result in a switching material layer 409 that is highly stoichiometric. In an embodiment, the switching material layer 409 deposited by such an ALD process has a thickness that is between lnm-5nm. In an embodiment, an ultra-thin layer of a Hf0 ₂ switching material layer 409 can be deposited to a thickness of less than 2nm by using an ALD process. In an RRAM device, the filament forming voltage is directly proportional to the thickness of the switching material layer 409. In an embodiment, a Hf0 ₂ switching material layer 409 having a thickness of less than 2nm is sufficiently thin enough to reduce the filament forming voltage to less than 1.5 V.

[0073] In another embodiment, the switching material layer 409 is deposited on the bottom electrode layer 405 and the oxygen exchange material layer 407 is deposited on the switching material layer 409. [0074] Figure 4C illustrates a cross-sectional view of the structure in Figure 4B following the formation of a top electrode 411 having a stack of conductive layers, in an accordance with an embodiment of the present invention.

[0075] The top electrode layer 411 is formed on the switching material layer 409. In an embodiment, the top electrode 411 is formed by blanket depositing a first conductive layer 411 A on the switching material layer 409 and then depositing a second conductive layer 41 IB on the first conductive layer 41 1 A. In an embodiment, the first conductive layer 411 A and the second conductive layer 41 IB are both blanket deposited using a PVD or an ALD process. In an embodiment, the first conductive layer 411 A is blanket deposited using a PVD process and the second conductive layer 41 IB sequentially blanket deposited using an ALD process. In another embodiment, the first conductive layer 411 A is blanket deposited using an ALD process and the second conductive layer 41 IB sequentially blanket deposited using a PVD process. In an embodiment, the first conductive layer 411 A and the second conductive layer 41 IB are deposited sequentially in a same chamber or in a same tool but without air exposure.

[0076] In an exemplary embodiment, a PVD deposition process is utilized to form the first conductive layer 41 1 A including TiN and the PVD deposition process is continued to deposit the second conductive layer 41 IB including TaN. In another embodiment, the first conductive layer 411 A including a TiN is deposited using a PVD process and the second conductive layer 41 IB including a TiN is deposited on the first conductive layer 411 A using an ALD process. It is to be appreciated that the ALD and the PVD deposition processes may be carried out sequentially without breaking vacuum, in a same tool.

[0077] When the first conductive layer 411 A and the second conductive layer 41 IB are deposited by utilizing differing methods such as PVD and ALD, and include deposition of a same material such as TiN, the deposition processes give rise to materials with microstructures having offset grain boundaries. For example, a first conductive layer 411 A including a TiN deposited by an ALD process is compositionally more uniform and has grain boundaries that are substantially further apart from each other compared to a second conductive layer 41 IB that includes a TiN that is deposited by a PVD process. Differences in the deposition characteristics as well as deposition temperatures and pressures can impact formation of grain boundaries. In an embodiment, PVD deposition process is carried out between 20 - 70 degrees Celsius while an ALD deposition process is carried out between 200-400 degrees Celsius. In an embodiment, a compound such as TiN that is deposited by a PVD process results in a microstructure with columnar grains separated by a few nm. In an embodiment, a compound such as TiN deposited by an ALD process results in a microstructure with grain boundaries separated by at least ten nanometers. In an embodiment, when the first conductive layer 411 A and the second conductive layer 41 IB are formed with a same material, the deposition process may be halted after depositing the first conducive layer 411 A and re-initiated to form the second conductive layer 41 IB under a different deposition condition. Such a deposition method with a process break can lead to misalignment in the grain boundaries between the two conductive layers as the nucleation sites for the second conductive layer 41 IB may not align with the grain boundaries of the underlying first conductive layer 411 A.

[0078] It is to be appreciated that the first conductive layer 411 A and the second conductive layer 41 IB can have thicknesses that are independently chosen. In an embodiment, the first conductive layer 411 A has a thickness between 2-20nm and the second conductive layer 41 IB has a material thickness between 2nm-20nm. In an embodiment, when the first conductive layer 411 A or the second conductive layer 41 IB are deposited by an ALD deposition method, the thickness is between 2nm-10nm. The ALD process may offer advantages such as greater film thickness uniformity (~1 %) compared to a PVD process (-5%), but may have a slower deposition rate, e.g., a deposition rate of 0.5 nm - 2nm/min.

[0079] Depending on the desired embodiment, the top electrode 411 can be formed of more than two layers sequentially deposited by one or more of the deposition methods described above. In one specific embodiment, the top electrode 411 further includes a third conductive layer including an inert metal such as Pt or Pd deposited on the second conductive layer 41 IB. In an embodiment, the third conductive layer including an inert metal has offset grain boundaries compared to the grain boundaries of the second conductive layer 41 IB. In an embodiment, the third conductive layer is deposited to a thickness of less than 2nm due to difficulties associated with etching inert metals. In an embodiment, the total combined thickness of all the conductive layers in the top electrode 308 is between 50-100nm.

[0080] In an embodiment, while not illustrated in Figure 4A or 4B, the bottom electrode may also be formed to include two or more conductive layers such as first conductive layer 411 A and second conductive layer 41 IB.

[0081] A dielectric hardmask layer 413 is then deposited on the RRAM material layer stack 420. In an embodiment, the dielectric hardmask layer 413 is blanket deposited using a PVD process. In an embodiment, the dielectric hardmask layer 413 is devoid of oxygen. In one embodiment, the dielectric hardmask layer 413 is a material such as, but not limited to, silicon nitride, silicon carbide or carbon-doped silicon nitride. In one embodiment, the dielectric hardmask layer 413 has a thickness approximately in the range of 50-100nm. The thickness of the dielectric hardmask layer 413 may be determined by patterning fidelity and subsequent processing tolerances, as will be discussed further below.

[0082] In an embodiment, the bottom electrode layer 405, the oxygen exchange material layer 407, the switching material layer 409 and the top electrode 411 are deposited in-situ without breaking vacuum.

[0083] Figure 4D illustrates the structure of Figure 4C following an etch process used to pattern the dielectric hardmask layer 413 to form a dielectric hardmask 414 and continuing the etch process to pattern the RRAM material layer stack 420 to form an RRAM device 430. A fully patterned RRAM device 430 includes a top electrode 412, a switching layer 410, an oxygen exchange layer 408 and a bottom electrode 406.

[0084] In an embodiment, the dielectric hardmask layer 413 is lithographically patterned and etched using an anisotropic plasma etch process. The lithographic process defines a location where the RRAM device 430 will be formed with respect to the conductive interconnect 402 located below the RRAM material layer stack 420. In an embodiment, different chemistries are utilized as part of numerous etch operations to etch the RRAM material layer stack 420. In an embodiment, a reactive ion etch utilizing a chemistry including Ar, CF ₄ and Cl ₂ is utilized to pattern the top electrode layer 411 that includes a compound such as TiN or TaN. It is to be appreciated that as layers of the RRAM material layer stack 420 are progressively etched, notching of a given layer may take place if the etch is too selective to the underlying material. For example, when the first conductive layer 411 A including tungsten is etched more selectively compared to the second conductive layer 41 IB such as TiN, notching may occur in sidewalls of the second conductive layer 41 IB. Furthermore, notching of the first conductive layer 411 A may result if the switching material layer 409 is etched at a slower rate compared to etching of the first conductive layer 411 A.

[0085] In an embodiment, the width of the bottom electrode 406 is larger than the width of the conductive interconnect 402, as is also depicted in Figure 4D. When the bottom electrode layer 405 is completely etched the underlying first dielectric layer 404 is exposed. Having a bottom electrode 406 that is larger than the width of the conductive interconnect 402 prevents etching of the conductive interconnect 402 during the patterning process.

[0086] Figure 4E illustrates the structure of Figure 4D following the formation of a dielectric spacer 416 laterally adjacent to the sidewalls of the RRAM device 430 and the dielectric hardmask 414, and on the first dielectric layer 404. In an embodiment, deposition of the dielectric spacer material is performed immediately after etching the RRAM device 430, but prior to air exposure. In an embodiment, the dielectric spacer material is deposited in the same tool or chamber used for the etch process. Such a procedure, known in the art, as in-situ deposition, may hermetically seal the device and potentially decrease oxidation of sensitive oxidizable layers. In an embodiment, the dielectric spacer material is a material such as, but not limited to, silicon nitride, silicon carbide, carbon-doped silicon nitride, or any suitable non- oxygen containing material. In an embodiment, the dielectric spacer material has a thickness approximately in the range of 20-50nm. In an embodiment, the dielectric spacer 416 is formed by an anisotropic plasma etch process.

[0087] Figure 4F illustrates the structure of Figure 4E following formation of a second dielectric layer 418 on the first dielectric layer 404 and laterally adjacent to the dielectric spacer 416. In an embodiment, a second dielectric layer 418 is disposed on the dielectric hardmask 414, the dielectric spacer 416 and on the first dielectric layer 404. In an embodiment, the second dielectric layer 418 includes materials similar to the materials chosen for the first dielectric layer 404. In an embodiment, a planarization process is carried out to remove a portion of the second dielectric layer 418, remove an upper portion of the dielectric spacer 416, remove an upper portion of the top electrode 412 and remove all of the dielectric hardmask 414. In an

embodiment, a chemical mechanical polishing (CMP) process is used for the planarizing. In an embodiment, uppermost portions of the second dielectric layer 418, the dielectric spacer 416 and the top electrode 412 are substantially co-planar after the CMP process.

[0088] In an embodiment, RRAM device 430 is annealed in a high temperature furnace at the end of the RRAM device fabrication process. In an embodiment, the anneal process is carried out at temperatures between 300-400 degrees C, for a time period between 30-60min. In an embodiment, the anneal process is carried out in a forming gas environment. A forming gas environment is one where a gas containing mostly N ₂ , diluted with 3-4% H ₂ , is flowed constantly over the surface of the RRAM device 430 while annealing is being performed. The anneal process drive the O ^2" from the switching layer 410 to the oxygen exchange layer 408 thus creating oxygen vacancies, V ₀ in the switching layer 410.

[0089] Figure 4G illustrates a plan view of an array of RRAM cells of the type illustrated in Figure 4F, in accordance with an embodiment of the present invention. In an embodiment, each RRAM device 430 has a circular shape from a plan view perspective, as is shown. In other embodiments, the shape of each RRAM device 430 from the plan view perspective is a shape such as, but not limited to, a square, a rectangle, or an oval.

[0090] Figures 5 A illustrates an I-V plot, demonstrating concepts involved with filament formation and voltage cycling (reading and writing) in an RRAM device such as the RRAM device 430 depicted in Figure 4F, in accordance with embodiments of the present invention.

[0091] In an embodiment, prior to filament formation the RRAM device 430 depicted in

Figures 4F is annealed in a high temperature furnace at the end of the RRAM device fabrication process. In an embodiment, the anneal process is performed at temperatures between 300-450 degrees Celsius and lasts for a time period of 30- 60 minutes. In an embodiment, the RRAM device 430 is annealed at 400 degrees Celsius for 30min. Annealing is a thermal phenomenon that serves to drive the O ^2" from the switching layer 410 in to the oxygen exchange layer 408 thus creating oxygen vacancies, V ₀ in the switching layer 410.

[0092] Referring to Figure 5 A, the initial operation of an RRAM device begins by gradually applying a voltage that is increasing in magnitude (from point A to point B), between the top electrode 412 and the bottom electrode 406. In an "intentional" one-time breakdown process, known as forming, oxygen vacancies, V ₀ , are pumped in from the oxygen exchange layer 408 into the switching layer 410 to augment the vacancies created during the anneal process described above. A "conductive" V ₀ filament is formed in the switching layer 410 at point B when sufficient vacancies are created. With an incrementally small increase in voltage beyond point B, a conductive filament 501 bridges the top electrode 412 and the bottom electrode 406, as illustrated in Figure 5B. The RRAM device 430 becomes conductive and is said to be in a low resistance state (point C). By sweeping the voltage between the top electrode 412 and bottom electrode 406 in a reverse direction (point C to D and then to F), a reversal in the electric field direction, causes the oxygen vacancies (technically positively charged ions) to be directed towards the oxygen exchange layer 408 leading to an onset of a break in the conductive filament in the switching layer 410 at point G in the plot in Figure 5 A. Filament breaking takes place at some critical voltage (point F), termed VRESET, and the device returns to a high resistance state (point G) when the applied voltage, V, is increased by a small negative value up to a point VRESET.STOP as indicated in the plot in Figure 5 A.

[0093] Figure 5C illustrates a cross-sectional view of the RRAM device 430 where the conductive filament 501 is broken and represents a momentary state of the RRAM device 430 at some point immediately after F or at any point in between points F and G, and between G and B in the plot in Figure 5 A. It is to be appreciated that the high resistance level of the RRAM device, point G, is different and lower in magnitude compared to the resistance level of the device before the onset of the forming process. The high resistance state of the RRAM device is the highest resistance value of the RRAM during voltage cycling of the RRAM device. By once again "sweeping" the applied voltage in the opposite direction, traversing from point G to H and then to point I in the I-V plot in Figure 5 A, the broken filament begins to manifests again under the action of vacancy migration (driven by the electric field). At some critical voltage, VSET, the filament completely bridges the top electrode 412 and the bottom electrode 406 and the device is once again said to be in a conductive or in a low resistance state, point J. Figure 5B once again illustrates a cross-sectional view of the RRAM device 430 where the conductive filament 501 bridges the top electrode 412 and the bottom electrode 406 and represents a momentary state of the RRAM device 430 at some point immediately after I or at any point in between points I and J, and between J and F in the plot in Figure 5A. The cycling of the RRAM device in this manner, creates an RRAM device having two defined resistance levels, high and low. The resistance level in RRAM device 430 remains unchanged about the OV level when the RRAM device 430 is either in the high resistance state or in the low resistance state and leads to the effect of nonvolatile memory. In other words, even with the voltage turned off, the resistance of the RRAM device 430 is maintained at either the high resistance value or at the low resistance value. To determine the resistance state of the RRAM device 430 after having turned off the applied voltage for some finite period of time, the RRAM device 430 undergoes a read operation. The read operation involves applying a voltage between the top electrode 412 and bottom electrode 406 that is less than the switching voltage (VSET or VRESET). In an embodiment, the read voltage is between plus or minus 0.1 - 0.2V. A low voltage range such as 0.1 -0.2 provides enables a low current from flowing through the device and enables resistance measurements to be made without accidentally causing the RRAM device to change resistance state.

[0094] It is to be appreciated that the values VSET and VRESET, generally refer to a portion of a voltage that is applied to a transistor which may be in series with the RRAM device 430. A large array of RRAM devices, where each RRAM device 430 is coupled to a transistor such as an access transistor leads to the formation of embedded memory.

[0095] Figure 6 illustrates a RRAM device 630, formed on a conductive interconnect 602 disposed in a via and integrated with a logic transistor 650 disposed above a substrate 605.

RRAM device 630 includes a bottom electrode 606, an oxygen exchange layer 608, a switching layer 610 and a top electrode 612. In one such embodiment, the RRAM device 630 is a device such as described in association with Figure 1 A. In an embodiment, the RRAM device 630 includes a bottom electrode 606, an oxygen exchange layer 608, the switching layer 610 and top electrode 612. In an embodiment, the top electrode 612 includes a first conductive layer 612A and a second conductive layer 612B. In an embodiment, the RRAM device 630 is laterally surrounded by a dielectric spacer 613. In one such embodiment, the RRAM device 630 is disposed directly on a conductive interconnect 602 coupled to a contact structure 614 connected to the drain end 620 of the transistor. In an embodiment, the contact structure 614 is disposed in a first dielectric layer 607. In an embodiment, the conductive interconnect 602 is disposed in a second dielectric layer 624. In other embodiments, the RRAM device 630 is a device such as described in association with Figure 2A or Figure 3. In an embodiment, the RRAM device 630 is surrounded by a third dielectric layer 609.

[0096] In an embodiment, the underlying semiconductor substrate 605 represents a general workpiece object used to manufacture integrated circuits. The semiconductor substrate 605 often includes a wafer or other piece of silicon or another semiconductor material. Suitable semiconductor substrates 605 include, but are not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials. The substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates.

[0097] In an embodiment, transistors associated with substrate 605 are metal-oxide- semiconductor field-effect transistors (MOSFET or simply MOS transistors), fabricated on the substrate 605. In various implementations of the invention, the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.

[0098] In an embodiment, each MOS transistor 650 of substrate 605 includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (S1O2) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.

[0099] The gate electrode layer of each MOS transistor 650 of substrate 605 is formed on the gate dielectric layer and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor 650 is to be a PMOS or an MOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a conductive fill layer.

[00100] For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.

[00101] In some implementations, the gate electrode may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the invention, the gate electrode may consist of a combination of U- shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

[00102] In some implementations of the invention, a pair of sidewall spacers 660 may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process operations. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[00103] As is well known in the art, source 632 and drain 620 regions are formed within the substrate adjacent to the gate stack of each MOS transistor. The source 632 and drain 620 are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source 632 and drain 620. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source 632 and drain 620. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source 632 and drain 620. In some implementations, the source 632 and drain 620 may be fabricated using a silicon compound such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon compound may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source 632 and drain 620 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or compound. And in further embodiments, one or more layers of metal and/or metal compounds may be used to form the source 632 and drain 620.

[00104] In an embodiment, the transistor 650 is further contacted at the source 632 by a source contact 615 and at the transistor gate structure 645 by a gate contact 615.

[00105] To provide further context, integrating memory directly onto a microprocessor chip would be advantageous since it enables higher operation speeds compared to having physically separate logic and memory chips. Unfortunately, traditional charge-based memory technologies such as DRAM and NAND Flash are now facing severe scalability issues related to increasingly precise charge placement and sensing requirements. As such, embedding charge- based memory directly onto a high performance logic chip is not very attractive for future technology nodes. However, a memory technology that does have the potential to scale to much smaller geometries compared to traditional charge-based memories is resistive random access memory (RRAM), since it relies on resistivity rather than charge as the information storage. However, in order to exploit the potential benefits of a high performance logic chip with embedded RRAM memory, an appropriate integrated logic plus RRAM structure and fabrication method is needed. Embodiments of the present invention include such structures and fabrication processes.

[00106] Relating to one or more embodiments described herein, it is to be appreciated that traditional DRAM memory is facing severe scaling issues and, so, other types of memory devices are being actively explored in the electronics industry. One future contender is RRAM devices. Embodiments described herein include a fabrication method for embedding RRAM bit cell arrays into a logic process technology. Embodiments described may be advantageous for processing schemes involving the fabrication of logic processors with embedded memory arrays.

[00107] In an aspect, an RRAM element may be included in an integrated circuit in regions typically referred to as back end or back end of line (BEOL) layers of the integrated circuit. As examples, Figures 7A-7E illustrate schematic views of several options for positioning an RRAM element in an integrated circuit, in accordance with embodiments of the present invention.

[00108] Referring to all Figures 7A-7E, in each case, a memory region 700 and a logic region 702 of an integrated circuit are depicted schematically. Each memory region 700 includes a select transistor 704 and overlying alternating metal lines and vias. Each logic region includes a plurality of transistors 706 and overlying alternating metal lines and vias which can be used to connect the plurality of transistors 706 into functional circuits, as is well known in the art.

[00109] Referring to Figure 7A, an RRAM device 720 is disposed between a lower conductive via 722 and an upper conductive line 724. In one embodiment, the lower conductive via 722 is in electrical contact with a bottom electrode of the RRAM device 720, and the upper conductive line 724 is in electrical contact with an upper electrode of the RRAM device 720. In a specific embodiment, the lower conductive via 722 is in direct contact with a bottom electrode of the RRAM device 720, and the upper conductive line 724 is in direct contact with an upper electrode of the RRAM device 720.

[00110] Referring to Figure 7B, an RRAM device 730 is disposed between a lower conductive line 732 and an upper conductive via 734. In one embodiment, the lower conductive line 732 is in electrical contact with a bottom electrode of the RRAM device 730, and the upper conductive via 734 is in electrical contact with an upper electrode of the RRAM device 730. In a specific embodiment, the lower conductive line 732 is in direct contact with a bottom electrode of the RRAM device 730, and the upper conductive via 734 is in direct contact with an upper electrode of the RRAM device 730.

[00111] Referring to Figure 7C, an RRAM device 740 is disposed between a lower conductive line 742 and an upper conductive line 744 without an intervening conductive via. In one embodiment, the lower conductive line 742 is in electrical contact with a bottom electrode of the RRAM device 740, and the upper conductive line 744 is in electrical contact with an upper electrode of the RRAM device 740. In a specific embodiment, the lower conductive line 742 is in direct contact with a bottom electrode of the RRAM device 740, and the upper conductive line 744 is in direct contact with an upper electrode of the RRAM device 740.

[00112] Referring to Figure 7D, an RRAM device 750 is disposed between a lower conductive via 752 and an upper conductive via 754 without an intervening conductive line. In one embodiment, the lower conductive via 752 is in electrical contact with a bottom electrode of the RRAM device 750, and the upper conductive via 754 is in electrical contact with an upper electrode of the RRAM device 750. In a specific embodiment, the lower conductive via 752 is in direct contact with a bottom electrode of the RRAM device 750, and the upper conductive via 754 is in direct contact with an upper electrode of the RRAM device 750.

[00113] Referring to Figure 7E, an RRAM device 760 is disposed between a lower conductive line 762 and an upper conductive via 764 in place of an intervening conductive line and conductive via pairing. In one embodiment, the lower conductive line 762 is in electrical contact with a bottom electrode of the RRAM device 760, and the upper conductive via 764 is in electrical contact with an upper electrode of the RRAM device 760. In a specific embodiment, the lower conductive line 762 is in direct contact with a bottom electrode of the RRAM device 760, and the upper conductive via 764 is in direct contact with an upper electrode of the RRAM device 760.

[00114] In an embodiment, RRAM devices 720, 730, 740, 750 and 760 include RRAM devices such as RRAM device 150 described in association with Figure 1A.

[00115] Figure 8 illustrates a block diagram of an electronic system 800, in accordance with an embodiment of the present invention. The electronic system 800 can correspond to, for example, a portable system, a computer system, a process control system, or any other system that utilizes a processor and an associated memory. The electronic system 800 may include a microprocessor 802 (having a processor 804 and control unit 806), a memory device 808, and an input/output device 810 (it is to be appreciated that the electronic system 800 may have a plurality of processors, control units, memory device units and/or input/output devices in various embodiments). In one embodiment, the electronic system 800 has a set of instructions that define operations which are to be performed on data by the processor 804, as well as, other transactions between the processor 804, the memory device 808, and the input/output device 810. The control unit 806 coordinates the operations of the processor 804, the memory device 808 and the input/output device 810 by cycling through a set of operations that cause instructions to be retrieved from the memory device 808 and executed. The memory device 808 can include a memory element having a conductive oxide and electrode stack as described in the present description. In an embodiment, the memory device 808 is embedded in the microprocessor 802, as depicted in Figure 8. In an embodiment, the processor 804, or another component of electronic system 800, includes an array of RRAM devices such as RRAM device 150 described in association with Figure 1 A.

[00116] Figure 9 illustrates a computing device 900 in accordance with one embodiment of the invention. The computing device 900 houses a board 902. The board 902 may include a number of components, including but not limited to a processor 904 and at least one

communication chip 906. The processor 904 is physically and electrically coupled to the board 902. In some implementations the at least one communication chip 906 is also physically and electrically coupled to the board 902. In further implementations, the communication chip 906 is part of the processsor 904.

[00117] Depending on its applications, computing device 900 may include other components that may or may not be physically and electrically coupled to the board 902. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

[00118] The communication chip 906 enables wireless communications for the transfer of data to and from the computing device 900. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 906 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 900 may include a plurality of communication chips 906. For instance, a first communication chip 906 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 906 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[00119] The processor 904 of the computing device 900 includes an integrated circuit die packaged within the processor 904. In some implementations of embodiments of the invention, the integrated circuit die of the processor includes one or more arrays, such as RRAM memory arrays integrated into a logic processor, built in accordance with embodiments of the present invention. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

[00120] The communication chip 906 also includes an integrated circuit die packaged within the communication chip 906. In accordance with another implementation of an embodiment of the invention, the integrated circuit die of the communication chip includes RRAM memory arrays integrated into a logic processor, built in accordance with embodiments of the present invention.

[00121] In further implementations, another component housed within the computing device 900 may contain a stand-alone integrated circuit memory die that includes one or more arrays, such as RRAM memory arrays integrated into a logic processor, built in accordance with embodiments of the present invention.

[00122] In various implementations, the computing device 900 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 900 may be any other electronic device that processes data.

[00123] Accordingly, one or more embodiments of the present invention relate generally to the fabrication of embedded microelectronic memory. The microelectronic memory may be non-volatile, wherein the memory can retain stored information even when not powered. One or more embodiments of the present invention relate to the fabrication of RRAM memory arrays integrated into a logic processor. In an embodiment, the RRAM memory arrays includes individual RRAM devices such as an RRAM device 150 described in association with Figure 1 A. Such arrays may be used in an embedded non -volatile memory, either for its non-volatility, or as a replacement for embedded dynamic random access memory (eDRAM). For example, such an array may be used for 1T-1R memory or 2T-1R memory (R = resistor) at competitive cell sizes within a given technology node.

[00124] Figure 10 illustrates an interposer 1000 that includes one or more embodiments of the invention. The interposer 1000 is an intervening substrate used to bridge a first substrate 1002 to a second substrate 1004. The first substrate 1002 may be, for instance, an integrated circuit die. The second substrate 1004 may be, for instance, a memory module, a computer mother, or another integrated circuit die. Generally, the purpose of an interposer 1000 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 1000 may couple an integrated circuit die to a ball grid array (BGA) 1006 that can subsequently be coupled to the second substrate 1004. In some embodiments, the first and second substrates 1002/1004 are attached to opposing sides of the interposer 1000. In other embodiments, the first and second substrates 1002/1004 are attached to the same side of the interposer 1000. And in further embodiments, three or more substrates are interconnected by way of the interposer 1000.

[00125] The interposer 1000 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further

implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

[00126] The interposer may include metal interconnects 1008 and vias 1010, including but not limited to through-silicon vias (TSVs) 1010. The interposer 1000 may further include embedded devices 1014, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, transistors, RRAM devices, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 1000. In accordance with embodiments of the invention, apparatuses or processes disclosed herein may be used in the fabrication of interposer 1000.

[00127] Thus, embodiments of the present invention include layered oxygen barrier electrodes for resistive random access memory (RRAM) devices and their methods of fabrication.

[00128] Specific embodiments are described herein with respect to RRAM devices. It is to be appreciated that embodiments described herein may also be applicable to other non-volatile memory devices. Such non-volatile memory devices may include, but are not limited to, magnetic random access memory (MRAM) devices, spin torque transfer memory (STTM) devices, perpendicular spin torque transfer memory (pSTTM) devices, and spin orbit torque (SOT) memory devices.

[00129] Example 1 : A resistive random access memory (RRAM) device includes a first electrode disposed above a substrate, a second electrode disposed above the first electrode, an oxygen exchange layer disposed between the first electrode and the second electrode and a switching layer disposed between the first electrode and the second electrode. The first or the second electrode comprises at least two conductive layers, a first conductive layer and a second conductive layer disposed above the first conductive layer, wherein the first conductive layer has grain boundaries that are offset from grain boundaries of the second conductive layer.

[00130] Example 2: The RRAM device of example 1 or 2, wherein the first conductive layer and the second conductive layer include material selected from the group consisting of WN, TiN, TaN, W, Ti, Ru or Ta.

[00131] Example 3 : The RRAM device of example 1 or 2, wherein the first conductive layer and the second conductive layer include material selected from the group consisting of WN, TiN, TaN, W, Ti, Ru or Ta.

[00132] Example 4: The RRAM device of example 1, 2 or 3, wherein the first conductive layer includes a material, different from the material of the second conductive layer, wherein the first conductive layer includes a material selected from the group consisting of WN, TiN, TaN, W, Ti, Ru or Ta and the second conductive layer includes a material selected from the group consisting of WN, TiN, TaN, W, Ti, Ru or Ta.

[00133] Example 5: The RRAM device of example 1, wherein the switching layer is closer to the second electrode than to the first electrode, and wherein the second electrode includes the first conductive layer and the second conductive layer.

[00134] Example 6: The RRAM device of example 1, wherein the switching layer is closer to the second electrode than to the first electrode, and wherein the first electrode includes the first conductive layer and the second conductive layer

[00135] Example 7: The RRAM device of example 1, wherein a third conductive layer is disposed on the second conductive layer and wherein the third conductive electrode has grain boundaries that are offset from the grain boundaries of the second conductive layer [00136] Example 8: The RRAM device of example 1, wherein the switching layer and the oxygen exchange layer include a same metal, the metal selected from the group consisting of hafnium, tantalum and titanium.

[00137] Example 9: A resistive random access memory (RRAM) device includes a bottom electrode layer disposed above a substrate, an oxygen exchange layer disposed on the bottom electrode, a switching layer disposed on the oxygen exchange layer, and a top electrode disposed on the switching layer. The bottom or the top electrode includes a stack of conductive layers, wherein the stack of conductive layers includes a first conductive layer and a second conductive layer disposed on the first conductive layer, and wherein the first conductive layer includes a material that is different from a material of the second conductive layer.

[00138] Example 10: The RRAM device of example 9, wherein the stack of conductive layers further includes a third conductive layer disposed on the third conductive layer.

[00139] Example 11 : The RRAM device of example 10, wherein the stack of conductive layers further includes a fourth conductive layer disposed on the third conductive layer.

[00140] Example 12: The RRAM device of example 9, 10 or 11, wherein the third conductive layer is a same material as the material of the first conductive layer and the fourth conductive layer is a same material as the material of the second conductive layer.

[00141] Example 13 : The RRAM device of example 9, wherein the top electrode includes the stack of conductive layers, wherein the first conductive layer includes a material selected from the group consisting of WN, TiN, TaN, W, Ti, Ru or Ta and the second conductive layer includes a material selected from the group consisting of WN, TiN, TaN, W, Ti, Ru or Ta.

[00142] Example 14: The RRAM device of example 9, wherein the bottom electrode includes the stack of conductive layers, wherein the first conductive layer includes a material selected from the group consisting of WN, TiN, TaN, W, Ti, Ru or Ta and the second conductive layer includes a material selected from the group consisting of WN, TiN, TaN, W, Ti, Ru or Ta.

[00143] Example 15: The RRAM device of example 9 or 14, wherein the bottom electrode includes a second stack of conductive layers, wherein the second stack of conductive layers includes a third conductive layer and a fourth conductive layer disposed on the fourth conductive layer, and wherein the third conductive layer includes a material substantially different from a material of the fourth conductive layer.

[00144] Example 16: The RRAM device of example 15, wherein the third conductive layer includes a material selected from the group consisting of WN, TiN, TaN, W, Ti, Ru or Ta and the fourth conductive layer includes a material selected from the group consisting of WN, TiN, TaN, W, Ti, Ru or Ta.

[00145] Example 17: The RRAM device of example 15, wherein the first conductive electrode has a thickness between 2-10nm, the second conductive electrode has a thickness between 2-10nm, the third conductive electrode has a thickness between 2-10nm and the fourth conductive electrode has a thickness between 2-10nm.

[00146] Example 18: The RRAM device of example 9, wherein the switching layer and the oxygen exchange layer include a same metal, the metal selected from the group consisting of hafnium, tantalum and titanium.

[00147] Example 19: The RRAM device of example 9, wherein the switching layer has a chemical composition, MOx, where M is a metal and O is an oxide with a numerical value of X close to 2.

[00148] Example 20: The RRAM device of example 9, wherein the bottom electrode layer, the switching layer, the oxygen exchange layer and the top electrode layer of the RRAM device have sidewalls, and wherein the RRAM device further includes a dielectric spacer film laterally disposed on the sidewalls, extending from a lowermost portion of the bottom electrode to an uppermost portion of the top electrode.

[00149] Example 20: A method of fabricating resistive random access memory (RRAM) device includes forming an RRAM material layer stack for an RRAM device. The method of the forming the RRAM material layer stack includes forming a bottom electrode layer above a substrate, forming an oxygen exchange material layer above the bottom electrode layer, forming a switching oxide material layer above the bottom electrode layer, and forming a top electrode layer above the oxygen exchange material layer. Forming the top electrode layer includes forming a first conductive layer on the switching oxide material layer and forming a second conductive layer on the first conductive layer without an air break. The method further includes forming a dielectric hardmask material on the RRAM material layer stack. The method of fabricating the RRAM device further includes patterning the dielectric hardmask material and using the dielectric hardmask layer as a mask to etch the top electrode layer, the switching oxide material layer, the oxygen exchange material layer and the bottom electrode layer to form a top electrode, a switching layer, an oxygen exchange layer and a bottom electrode.

[00150] Example 22: The method of example 21, wherein forming the top electrode includes depositing a first conductive layer having a first material using a physical vapor deposition process and then depositing a second conductive layer with a second material, different from the first material using a physical vapor deposition process, wherein the physical vapor deposition process of forming the first conductive layer and the second conductive layer results in formation of grain boundaries of the first conductive layer to be offset from grain boundaries of the second conductive layer.

[00151] Example 23 : The method of example 21, wherein forming the RRAM material layer stack includes depositing the oxygen exchange material layer on the bottom electrode layer, then depositing the switching oxide material layer on the oxygen exchange material layer, and then depositing the top electrode layer on the oxygen exchange material layer.

[00152] Example 24: The method of example 21, wherein forming the RRAM material layer stack includes depositing the switching oxide material layer on the bottom electrode layer, then depositing the oxygen exchange material layer on the switching oxide material layer, and then depositing the top electrode layer on the oxygen exchange material layer.