Title:
LAYOUT DESIGN SYSTEM, AND LAYOUT DESIGN METHOD
Document Type and Number:
WIPO Patent Application WO/2018/234945
Kind Code:
A1
Abstract:
The present invention performs the layout design for a small area in a short period of time while satisfying design rules. This layout design system comprises a processing unit. A circuit diagram and layout design information are input into the processing unit. The processing unit includes a function for generating layout data from the circuit diagram and the layout design information by performing Q learning. The processing unit includes a function for outputting the layout data. The processing unit comprises a first neural network. The first neural network estimates an action value function for the Q learning.
Inventors:
TSUTSUI NAOAKI (JP)
KOUMURA YUSUKE (JP)
IWAKI YUJI (JP)
YAMAZAKI SHUNPEI (JP)
KOUMURA YUSUKE (JP)
IWAKI YUJI (JP)
YAMAZAKI SHUNPEI (JP)
Application Number:
PCT/IB2018/054348
Publication Date:
December 27, 2018
Filing Date:
June 14, 2018
Export Citation:
Assignee:
SEMICONDUCTOR ENERGY LAB (JP)
International Classes:
G06F17/50
Foreign References:
| JP2015148926A | 2015-08-20 |
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