Title:
LAYOUT STRUCTURE FOR TESTING JUNCTION CAPACITOR, AND DESIGN METHOD THEREFOR
Document Type and Number:
WIPO Patent Application WO/2023/035453
Kind Code:
A1
Abstract:
Provided in the embodiments of the present disclosure are a layout structure for testing a junction capacitor, and a design method therefor. The layout structure for testing a junction capacitor comprises: a well region, which is used for forming a test structure of a MOS transistor, wherein the test structure is used for testing a junction capacitor of the MOS transistor; an ion implantation region, which is located in the well region and is flush with the surface of the well region, and is used for forming a source electrode or a drain electrode of the MOS transistor, wherein a PN junction can be formed between the ion implantation region and the well region; and a functional layer, which covers the surface of the well region, wherein the functional layer does not cover the ion implantation region, and is used for forming a specific type of junction capacitor.
Inventors:
QIAN SHIBING (CN)
Application Number:
PCT/CN2021/137410
Publication Date:
March 16, 2023
Filing Date:
December 13, 2021
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H01L23/544; G11C11/413; H01L27/02
Foreign References:
| CN102956620A | 2013-03-06 | |||
| JP2003068756A | 2003-03-07 | |||
| CN102945841A | 2013-02-27 | |||
| KR20090072035A | 2009-07-02 | |||
| US20050260776A1 | 2005-11-24 |
Attorney, Agent or Firm:
CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)
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