FIELD OF THE INVENTION

This invention relates to light emitting diodes (LEDs) and, in particular, to a method of employing a carrier wafer for wafer level processing of LEDs. BACKGROUND

In a typical LED fabrication process, a wafer containing many semiconductor LEDs is diced, and the individual LED dies are mounted on a submount wafer. Electrodes on the LEDs are bonded to metal pads on the top surface of the submount wafer. The metal pads on the top surface are typically interconnected to broader area metal pads on the bottom surface of the submount wafer for eventual bonding to a circuit board. Prior to the LEDs being mounted on the submount wafer, the submount wafer is fully processed to incorporate its various electrical interconnections.

The LED dies on the submount wafer are then further processed using wafer level processing. Such wafer level processing typically includes removing the growth substrate (e.g., sapphire for GaN LEDs), roughening the exposed semiconductor layer for increasing light extraction, and forming encapsulating lenses over the LEDs. The submount wafer is then diced to separate out the individual LEDs/submounts.

Handling the LED dies and electrically bonding the individual LED dies to the submount wafer are time consuming and prone to damaging the LEDs. Additionally, the resulting size of a diced submount is larger than the LED die, and it may be desirable in some cases to reduce the size of the completed surface mounted LED. There are other drawbacks with the above-described process.

It would be desirable to provide an improved wafer level process for forming LEDs that is simpler and more reliable. SUMMARY

In the example given below, the LEDs are flip-chips, having both electrodes on the bottom surface of the LED. The invention also applies to other types of LEDs.

In one embodiment, an LED wafer containing LED areas (corresponding to LED dies) is fabricated, and the LEDs are tested. The LED areas have flip chip metal electrodes on a "bottom" surface of the wafer. A carrier wafer, of a size similar to the LED wafer, is also fabricated and separately tested. The carrier wafer may be silicon with insulated electrodes terminating in top and bottom bonding pads. Prior to singulating the LED wafer, the electrodes of the LED areas are bonded to the top bonding pads of the carrier wafer. Bonding may be performed ultrasonically using gold stud bumps, or a solder may be used, or anisotropic conductive films may be used.

The LED wafer is now supported by the carrier wafer, which helps prevent breakage of the LED wafer during subsequent wafer level processing of the LED wafer. Such wafer level processing may include removal of the growth substrate (e.g., by chemical-mechanical polishing (CMP), etching, or laser lift-off), roughening of the exposed semiconductor layer for increased light extraction, depositing phosphor, encapsulation, etc.

The bonded wafers are then singulated to create individual surface mounted LED dies comprising the LED semiconductor layers and the bonded carrier portion. Very little carrier wafer material is wasted, since the carrier dice are the same size as the LED dice.

Additionally, bonding of pre-tested fully finished LED wafers and pre-tested carrier wafers allows us to employ only known-good-wafers, thus avoiding bonding of good LED wafers to bad carrier wafers or vice-versa, and thus improving the overall yields. The bottom pads of the carrier portion of the LED assembly may be bonded to pads of a printed circuit board or other substrate. Subsequent processing may also be performed such as encapsulating the LED dies and molding lenses over the LED dies.

In another embodiment, the carrier wafer is not fully fabricated before being bonded to the LED wafer. This may be desirable in order to provide more robust electrical and mechanical bonding to the LED electrodes, described below. In such an embodiment, the LED wafer is affixed, using a polymer adhesive layer, to a silicon wafer that has no conductors. Holes (vias) are then etched through the silicon wafer and adhesive layer to expose the LED electrodes. The sidewalls of the holes are insulated with a layer of nitride or oxide, and the holes are filled with a metal to electrically contact the LED electrodes. The metal terminates in bottom pads on the carrier wafer. The bonded wafer assembly may be further processed, as described with the first embodiment. The bonded wafers are then singulated to create individual LED dies.

The carrier wafer may be formed to contain integrated electronics for each LED, such as ESD protection devices, controllers, sensors, or other circuitry. Other embodiments are described.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a simplified top down view of an LED wafer with a plurality of LEDs formed in it.

Fig. 2 is a simplified top down view of a carrier wafer, where each carrier area aligns with an LED area in the LED wafer.

Fig. 3 is a cross-sectional view of a single LED in the LED wafer prior to singulation.

Fig. 4 illustrates a simplified LED, showing only the growth substrate, semiconductor LED layers, and metal electrodes.

Fig. 5 is a cross-sectional view of a single carrier in the carrier wafer prior to singulation.

Fig. 6 illustrates the electrodes of the LEDs in the LED wafer being bonded to the top metal pads of the carrier wafer.

Fig. 7 illustrates the LED wafer being processed, such as by removing the growth substrate, roughening the exposed semiconductor layer, and depositing a phosphor layer. The bonded wafers are then singulated. Figs. 8-20 illustrate a second embodiment where the carrier wafer is fabricated after bonding to the LED wafer.

Fig. 8 is a cross-sectional view of a single LED in the LED wafer, prior to singulation, after an adhesive layer has been formed on the bottom surface of the LED wafer.

Fig. 9 is a cross-sectional view of a starting carrier wafer, such as a silicon wafer.

Fig. 10 illustrates the carrier wafer having an oxidized bottom surface.

Fig. 11 illustrates the carrier wafer after being thinned by a CMP process.

Fig. 12 illustrates the carrier wafer bonded to the LED wafer by the adhesive layer.

Fig. 13 illustrates vias etched through the carrier wafer and adhesive layer to expose the LED electrodes.

Fig. 14 illustrates the surfaces of the carrier wafer, including the walls of the vias, coated with a dielectric.

Fig. 15 illustrates the dielectric formed in Fig. 14 etched away over the LED electrodes to expose the electrodes.

Fig. 16 illustrates a metal, such as a barrier metal and copper, deposited in the vias and over a portion of the bottom surface of the carrier wafer to form carrier electrodes connected to the LED electrodes.

Fig. 17 illustrates a patterned dielectric exposing portions of the carrier electrodes and illustrates Ni/Au bond pads formed over the exposed carrier electrodes.

Fig. 18 illustrates the growth substrate removed and any other wafer level processes performed on the LED wafer, such as thinning and roughening the exposed LED layer for increasing light extraction. Fig. 19 illustrates a phosphor layer deposited over the LED wafer. The bonded wafers are then singulated after any further wafer level processing. The singulated LEDs may be identical to Fig. 19.

Elements that are the same or equivalent are labeled with the same numeral. DETAILED DESCRIPTION

The figures illustrate some of the many possible embodiments of the invention.

Fig. 1 is a simplified top down view of an LED wafer 10 with a plurality of LEDs 16 formed in it.

Fig. 2 is a simplified top down view of a carrier wafer 18 with a plurality of carriers 20 formed in it, where each carrier 20 aligns with an LED 16 in the LED wafer 10.

The two wafers 10 and 18 will typically be the same size. The narrow spaces between LEDs 16 and between carriers 20 correspond to singulation lines.

Fig. 3 is a cross-sectional view of a portion of the LED wafer 10 illustrating a single flip chip LED. The growth substrate 24 may be sapphire, SiC, GaN, or other material used to grow epitaxial layers for forming a GaN-based LED. Also shown are the LED's n-layer 26, active layer 28, p-layer 30, p-contact layer 32, dielectric layers 34 for electrical insulation and mechanical support, and metal electrodes 36 and 38 electrically contacting the p-layer 30 and n-layer 26, respectively. There are many other configurations of LEDs that are suitable in the present invention. Various techniques for forming the LED wafer 10 are well known. For a flip-chip, portions of the p-layer 30 and active layer 28 are etched away to expose the n-layer 26 for metallization. In this way, the electrodes 36/38 are on the same side of the chip. Current from the n-metal electrode 38 initially flows laterally through the n- layer 26. The electrodes 36/38 are typically formed of a reflective metal. Collectively, LED layers 40 comprise n-layer 26, active layer 28, p-layer 30 and contact layer 32. Other types of LEDs that can be used in the present invention include AlInGaP LEDs, which can produce light in the red to yellow range. Non- flip-chip LEDs can also be used. Figs. 4-7 illustrate one embodiment of the invention. The LED 16 of Fig. 3 is simplified in Figs. 4-7 as being comprised of LED layers 40, the growth substrate 24, and the electrodes 36 and 38.

Fig. 5 is a cross-sectional view of a single carrier 20 in the carrier wafer 18 prior to singulation. The carrier 20 comprises a silicon wafer 42 having etched vias 44 A and 44B. The sidewalls of the vias 44A and 55B and the surfaces of the silicon wafer 42 are insulated with a dielectric layer, such as an oxide or nitride. The vias 44A and 44B are then filled, or partially filled, with a metal 46A and 46B. Metal 46A and 46B may be any conductive material such as copper. The metal 46A and 46B may be deposited by plating, sputtering, or other technique.

Top metal bonding pads 48 and 50 and bottom metal bonding pads 52 and 54, such as Ni/Au, are formed using conventional techniques. The bonding pads 48 and 52 are electrically connected through the metal 46A, and the bonding pads 50 and 54 are electrically connected through the metal 46B. .

Fig. 6 illustrates the electrodes 36/38 of the LEDs 16 in the LED wafer 10 being electrically bonded to the top metal pads 48/50 of the carriers 20 in the carrier wafer 18. Ultrasonic welding using gold stud bumps, solder or any other suitable method may be used for the bonding.

The LED wafer 10 then undergoes further wafer level processing such as removing the growth substrate 24, and thinning and roughening the exposed semiconductor layer. The carrier wafer 18, being much thicker than the LED semiconductor layers, helps prevent breakage of the LED wafer 10 during the wafer level processing of the LED wafer 10.

Fig. 7 illustrates a phosphor layer 56 deposited over the exposed portion of LED layers 40. The phosphor layer 56 may be a pre-formed phosphor wafer affixed to the LED wafer 10, or a deposited phosphor in a binder, or other type of phosphor layer.

An encapsulation layer and lenses may also be deposited over the LED wafer 10. The bonded wafers are then singulated, such as by sawing, to produce individual surface mounted LED dies, which may be similar to Fig. 7.

As seen in the embodiment of Figs. 4-7, the LEDs are not first singulated prior to being mounted on a carrier. This wafer level mounting process thus saves processing time and costs. Further, there is a minimum of carrier wafer waste since the carriers are the same size as the LED dies. Other processing and cost advantages exist.

Figs. 8-20 illustrate a second embodiment where the carrier wafer is fabricated after bonding to the LED wafer.

Fig. 8 is a cross-sectional view of a single LED 16 in the LED wafer 10, prior to singulation, after a dielectric adhesive layer 60 has been formed on the planarized bottom surface of the LED wafer 10. The adhesive layer 60 may be a benzocyclobutene (BCB) polymer layer. BCB hardens upon curing with heat.

Fig. 9 is a cross-sectional view of a starting carrier wafer 62, such as a silicon wafer. The carrier wafer 62 will typically be thicker than 200 microns. Fig. 10 illustrates the carrier wafer 62 after being subject to a thermal oxidation step to form an oxide 64 on its bottom surface.

Fig. 11 illustrates the carrier wafer 62 after being thinned by a CMP process to less than 100 microns. Optionally, a BCB adhesive layer is added to the top surface of the carrier wafer 62. Fig. 12 illustrates the carrier wafer 62 bonded to the LED wafer 10 under pressure and heat to cure the adhesive layer 60.

Fig. 13 illustrates vias 66A and 66B etched through the carrier wafer 62 and adhesive layer 60 to expose the LED electrodes 36/38. RIE etching or another etching process can be used. Fig. 14 illustrates the surfaces of the carrier wafer 62, including the walls of the vias

66A and 66B, coated with a dielectric 68, such as a PECVD nitride. Fig. 15 illustrates the dielectric 68 formed in Fig. 14 etched away over the LED electrodes 36/38 to expose the electrodes 36/38. The etching may be a blanket RIE etch. This etching also etches away some or all of the dielectric 68 over the bottom surface of the carrier wafer 62.

Fig. 16 illustrates a patterned metal 70, such as a barrier metal followed by copper, deposited in the vias 66 and over a portion of the bottom surface of the carrier wafer 62 to form isolated carrier electrodes 72/74 connected to the LED electrodes 36/38, respectively. The vias 66 may be partially filled as shown in Fig. 16 or completely filled as shown in Fig. 17. The metal 70 is patterned by conventional masking and deposition techniques. The deposition may be by plating, sputtering, or other technique. An adhesion layer may be needed, depending on the materials use, to ensure the metal 70 adequately adheres to the oxide 64.

Fig. 17 illustrates a patterned dielectric 76 filling the remaining volume of the vias 66A and 66B, if needed, and exposing areas of the isolated carrier electrodes 72/74. A bonding layer of Ni/Au is then patterned to form bond pads 78/80 over the carrier electrodes 72/74.

Fig. 18 illustrates the growth substrate 24 removed and any other wafer level processes performed on the LED wafer 10, such as thinning and roughening the exposed LED layer for increasing light extraction.

Fig. 19 illustrates a phosphor layer 56 deposited over the LED wafer 10. The phosphor layer 56 may be a pre-formed phosphor wafer affixed to the LED wafer 10 or may be deposited by any means. A typical thickness of the phosphor layer 56 may be between 50-100 microns.

The bonded wafers 10/62 are then singulated by, for example, sawing, after any further wafer level processing. The singulated LEDs may be identical to Fig. 19.

The LEDs may be encapsulated and lenses formed over them either prior to or before singulation. The carrier bond pads 78/80 may then be bonded to pads of a printed circuit board, or a submount.

Relative to the first embodiment of Figs. 4-7 where the carrier wafer is fully processed prior to bonding, one concern of the second embodiment of Figs. 8-19 is the increased risk of damaging the relatively expensive LED wafer 10 by the processes performed on the carrier wafer 62. However, the electrical bond between the LED electrodes and the carrier wafer electrodes may be improved using the second embodiment. In both embodiments, there is excellent heat conduction through the carrier wafer due to the metal deposited in the vias and thinness of the carrier wafer (e.g., less than 100 microns). The carrier wafer may be formed to contain integrated electronics for each LED, such as ESD protection devices, controllers, sensors, or other circuitry.

Although two vias are shown in each embodiment, only one via or more than two vias may be created for each LED or for other components requiring a submount.

While particular embodiments of the present invention have been shown and described, it will be obvious to those skilled in the art that changes and modifications may be made without departing from this invention in its broader aspects and, therefore, the appended claims are to encompass within their scope all such changes and modifications as fall within the true spirit and scope of this invention.