Title:
LEVEL SHIFT CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2012/063382
Kind Code:
A1
Abstract:
In a level shift circuit capable of providing a preferable operation with short delay time even when low voltage is established from a low voltage source, for example, when an input signal (IN) is state-changed from a high (VDD) level to a low level, a node (W2) pre-charged at a high (VDD3) level is discharged to ground (VSS) via a discharge circuit (N2) and the potential is dropped, the potential drop is sent to a latch circuit (LA) and the output of the latch circuit (LA) is sent to an output circuit (OC). Further, a reversed signal of the node (W2) is inputted into the output circuit (OC) while bypassing the latch circuit (LA). As such, the output circuit (OC) at an early stage starts the operation prior to the operation based on the output of the latch circuit (LA). Thus, even when a normal voltage is established where the voltage of the low voltage source is established as the normal voltage, a preferable level shift is performed having an output signal with reduced delay time.
Inventors:
GION, Masahiro (())
Application Number:
JP2011/004016
Publication Date:
May 18, 2012
Filing Date:
July 13, 2011
Export Citation:
Assignee:
PANASONIC CORPORATION (1006, Oaza Kadoma Kadoma-sh, Osaka 01, 〒5718501, JP)
パナソニック株式会社 (〒01 大阪府門真市大字門真１００６番地 Osaka, 〒5718501, JP)
パナソニック株式会社 (〒01 大阪府門真市大字門真１００６番地 Osaka, 〒5718501, JP)
International Classes:
H03K19/0185
Attorney, Agent or Firm:
MAEDA, Hiroshi et al. (Osaka-Marubeni Bldg, 5-7Hommachi 2-chome, Chuo-ku, Osaka-sh, Osaka 53, 〒5410053, JP)
Claims:
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