Title:
LEVEL SHIFTING CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2017/159058
Kind Code:
A1
Abstract:
The present invention prevents malfunctions when dV/dt noise occurs for an extended period of time on a high-side reference potential line. Series-connected transistors (PM1, PM1X and PM2, PM2X) are respectively connected in parallel with level shifting resistors (LSR1, LSR2). One of the transistors (PM1, PM2) is turned on or off in accordance with an output from a latch circuit (113), in a direction in which the latched state is less liable to change. The other transistor (PM1X, PM2X) is turned on while a dV/dt period detecting circuit (114) is detecting the occurrence of dV/dt, and when for example the output from the latch circuit (113) is at the low level, the level shifting resistor (LSR1) is lowered by the ON-resistance of the transistors (PM1, PM1X), relatively lowering the potential of a connecting point (resdrn) and making the latched state less liable to change. When the dV/dt period detecting circuit (114) detects that dV/dt has ended, the transistors (PM1X, PM2X) are both turned off.
Inventors:
AKAHANE MASASHI (JP)
Application Number:
PCT/JP2017/002667
Publication Date:
September 21, 2017
Filing Date:
January 26, 2017
Export Citation:
Assignee:
FUJI ELECTRIC CO LTD (JP)
International Classes:
H03K19/0185; H03K17/16; H03K17/687; H03K19/0948
Domestic Patent References:
| WO2012070174A1 | 2012-05-31 |
Foreign References:
| JP2013219714A | 2013-10-24 | |||
| JP2013179501A | 2013-09-09 | |||
| JP2012075267A | 2012-04-12 | |||
| JP2003273715A | 2003-09-26 |
Attorney, Agent or Firm:
HATTORI, Kiyoshi (JP)
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