Field of the Invention

The present invention relates to level shifting circuitry for shifting digital signals from a first voltage domain with a first threshold voltage to a second voltage domain with a second threshold voltage higher than the first threshold voltage.

Background of the Invention

Level shifters are typically needed in high-voltage electronic systems, such as TFT-based systems, where various signals generated in a lower voltage domain are used for controlling the high-voltage system.

Control signals are often generated by CMOS circuitry, for which the operating voltage has been decreasing over time with the introduction of new CMOS manufacturing processes. This reduction in operating voltage has led to challenges in achieving the desired level shifting.

In particular, the signal levels that can be output by CMOS circuitry may be insufficient to achieve switching, or may only achieve partial switching of transistors included in the level shifting circuitry if conventional level shifting circuitry configurations are used.

This problem is addressed by US 2004/0032291 , which proposes a solution involving “pre-shifters” for lifting the control signals input to the level shifting circuitry to an intermediate level to achieve satisfactory level shifting.

However, the solution according to US 2004/0032291 requires additional components, which increases the space occupied by the level shifting circuitry, and may also be expected to result in a higher current consumption.

In view of this, it would be desirable to provide for improved level shifting, in particular requiring less space and/or providing for a lower current consumption. Summary

It is thus an object of the present invention to provide improved level shifting, in particular requiring less space and/or providing for a lower current consumption.

According to the present invention, it is therefore provided level shifting circuitry for shifting digital signals from a first voltage domain with a first threshold voltage to a second voltage domain with a second threshold voltage higher than the first threshold voltage, the level shifting circuitry comprising: a first terminal for connection to a first voltage being higher than the second threshold voltage; a second terminal for connection to a second voltage being lower than the second threshold voltage; toggle circuitry having a toggle input and a toggle output, the toggle circuitry being configured to alternate an output voltage at the toggle output between a logic low voltage for the second voltage domain and a logic high voltage for the second voltage domain in response to a voltage at the toggle input becoming lower than a predefined threshold voltage for the toggle circuitry; a reset switch coupled between the first terminal of the level shifting circuitry and the toggle input, and having a reset switch control input to allow control of the reset switch between a nonconducting state and a conducting state in which the first terminal of the level shifting circuitry and the toggle input are conductively connected through the reset switch; a resistive element connected in parallel with the reset switch between the first terminal of the level shifting circuitry and the toggle input, for allowing a leakage current to flow from the first terminal of the level shifting circuitry through the resistive element, when the reset switch has been controlled to its non-conducting state; and pull-down circuitry coupled between the toggle input and the second terminal of the level shifting circuitry, and having an input for receiving a control signal for the level shifting circuitry, the pull-down circuitry being configured to open a current path from the toggle input through the pull-down circuitry in response to a transition of the control signal from a logic low voltage to a logic high voltage for the first voltage domain and in response to a transition of the control signal from a logic high voltage to a logic low voltage for the first voltage domain. The present invention is based on the realization that the use of toggle circuitry configured to alternate the output voltage at the toggle output between a logic low voltage for the second voltage domain and a logic high voltage for the second voltage domain in response to a voltage pull-down at the toggle input allows level shifting using low voltage controllable pull-down only. This provides for compact level shifting circuitry with a relatively low current consumption.

Since the pull-down circuitry is configured to temporarily open a current path from the toggle input through the pull-down circuitry in response to a transition of the control signal from a logic low voltage to a logic high voltage for the first voltage domain and in response to a transition of the control signal from a logic high voltage to a logic low voltage for the first voltage domain, the voltage at the toggle input can be pulled down in response to a transition from logic low to logic high of the control signal, and following operation of the reset switch, the voltage at the toggle input can again be pulled down in response to a transition from logic high to logic low of the control signal. This results in the desired level shifted output from the toggle circuitry.

According to various embodiments of the level shifting circuitry, the pull-down circuitry may advantageously comprise switching circuitry having a first terminal connected to the toggle input, a second terminal, and a third terminal, the switching circuitry being configured to open the current path through the pull-down circuitry when a voltage between the second terminal and the third terminal of the switching circuitry exceeds a predefined threshold voltage for the switching circuitry; and routing circuitry coupled to the second terminal and the third terminal of the switching circuitry, the input of the pull-down circuitry, and the toggle output, the routing circuitry being configured to connect the control signal for the level shifting circuitry to either the second terminal or the third terminal of the switching circuitry depending on the output voltage at the toggle output.

The switching circuitry may advantageously be an NMOS-transistor having a source, a gate and a drain, where the first terminal is the drain, the second terminal is the gate and the third terminal is the source. According to embodiments, the level shifting circuitry may comprise reset control signal generating circuitry coupled to the toggle circuitry and to the reset switch control input, and configured to generate a control signal for the reset switch based on an output of the toggle circuitry. When the toggle circuitry has toggled - as the result of the voltage at the toggle input becoming lower than the predefined threshold voltage for the toggle circuitry - the reset control signal generating circuitry can thus control the reset switch to bypass the resistive element, to again pull up the voltage at the toggle input to a level that is higher than the threshold voltage of the toggle circuitry.

In summary, the present invention thus relates to level shifting circuitry comprising toggle circuitry having a toggle input and a toggle output, the toggle circuitry being configured to alternate an output voltage at the toggle output between a logic low and a logic high for the second voltage domain in response to a voltage at the toggle input becoming lower than a predefined threshold voltage; a reset switch coupled between a first terminal of the level shifting circuitry and the toggle input; a resistive element connected in parallel with the reset switch; and pull-down circuitry coupled between the toggle input and a second terminal of the level shifting circuitry, and having an input for receiving a control signal, the pull-down circuitry being configured to open a current path from the toggle input through the pull-down circuitry in response to transition of the control signal from low to high and from high to low.

Brief Description of the Drawings

These and other aspects of the present invention will now be described in more detail, with reference to the appended drawings showing example embodiments of the invention, wherein:

Fig 1 is an illustration of an exemplary electronic system according to an embodiment of the present invention, in the form of a fingerprint sensing system;

Fig 2 is a schematic illustration of level shifting circuitry according to a first example embodiment of the present invention;

Fig 3 is a schematic illustration of level shifting circuitry according to a second example embodiment of the present invention; and Figs 4A-C are timing diagrams for assisting description of the operation of the level shifting circuitry in fig 3.

Detailed Description of Embodiments

In the present detailed description, various embodiments of the level shifting circuitry according to the present invention are mainly described with reference to an electronic system in the form of a TFT-based fingerprint sensing system. However, this should not be construed as limiting the present invention, as defined by the claims.

On the contrary, it should be understood that the level shifting circuitry according to embodiments of the present invention may advantageously be included in various other types of electronic systems, that may or may not be TFT-based. One example of another type of TFT-based electronic system is a display.

Fig 1 is an illustration of an exemplary electronic system according to an embodiment of the present invention, in the form of a fingerprint sensing system 1 . As is schematically indicated in fig 1 , the fingerprint sensing system 1 comprises structures formed on a substrate or carrier 3. In particular in embodiments where the fingerprint sensing system 1 is primarily manufactured using TFT-techniques, which are perse known to those skilled in the art, the carrier 3 may advantageously be made of glass or plastic. On the carrier 3 are formed a plurality of conductive selection lines 5 and a plurality of conductive read-out lines 7. The selection lines 5 are arranged in parallel to each other, and the read-out lines 7 are arranged in parallel to each other and crossing the selection lines 5. The selection lines 5 are conductively separated from the read-out lines 7, typically by a dielectric layer deposited between a first conductive layer including the selection lines 5 and a second conductive layer including the read-out lines 7. A plurality of pixel elements 9, here forming a pixel element array, are formed at respective intersections between the selection lines 5 and the read-out lines 7. In addition to the selection lines 5 and the read-out lines 7, the fingerprint sensing system 1 in fig 1 comprises selection circuitry 11 coupled to each of the selection lines 5, and read-out circuitry 13 coupled to each read-out line 7. In the example configuration of fig 1 , the functionality of the read-out circuitry 13 is partly provided by a portion 15 of the TFT-module, and partly by an ASIC 17 coupled to the TFT-module.

The ASIC 17 may comprise CMOS-based processing circuitry configured to operate in a first voltage domain with a first threshold voltage, and the TFT-module - including the above-mentioned portion 15 thereof - may be configured to operate in a second voltage domain with a second threshold voltage higher than the first threshold voltage. To allow communication within the read-out circuitry 13 of the fingerprint sensing system 1 , the fingerprint sensing system 1 may be provided with level shifting circuitry 19 for shifting digital signals from the first voltage domain to the second voltage domain. As is indicated by the dashed arrow in fig 1 , the level shifting circuitry 19 may optionally also be used for allowing the ASIC 17 to control the selection circuitry 11. Alternatively, the level shifting circuitry 19 - or additional level shifting circuitry - may be configured to allow control of the selection circuitry 11 (or other circuitry of the fingerprint sensing system 1 ) by external CMOS-based processing circuitry not shown in fig 1 .

Fig 2 is a schematic illustration of level shifting circuitry 19 according to a first example embodiment of the present invention. Referring to fig 2, the level shifting circuitry 19 comprises a first terminal 21 , a second terminal 23, toggle circuitry 25 having a toggle input 27 and a toggle output 29, a reset switch 31 , a resistive element 33, and pull-down circuitry 35. The first terminal 21 is configured for connection to a first voltage Vi being higher than the second threshold voltage, and the second terminal 23 is configured for connection to a second voltage V2 being lower than the second threshold voltage.

For digital signals in a voltage domain, voltages that are lower than the threshold voltage of the domain are generally interpreted as logic low or ‘0’ and voltages that are higher than the threshold voltage of the domain are interpreted as logic high or T in that voltage domain.

Furthermore, when a certain voltage is described as being “higher” or “lower” than another voltage, it should be understood that this refers to a magnitude in relation to a common reference potential, such as 0V (ground). For example, the first threshold voltage may be 1 ,8V, the second threshold voltage may be 5V, the second voltage V2 may be 0V, and the first voltage Vi may be 10V, where all of these voltages are given in relation to the same reference potential.

Moreover, it should be understood that the term “terminal” can refer to a node in a circuit diagram, and does not require any ability to directly connect the “terminal” to external circuitry.

The toggle circuitry 25 is configured to alternate an output voltage V _ou t at the toggle output 29 between a logic low voltage for the second voltage domain and a logic high voltage for the second voltage domain, in response to a voltage Vt.in at the toggle input 27 becoming lower than a predefined threshold voltage for the toggle circuitry 25. In other words, the toggle circuitry 25 is configured to change the present logic state at its output in response to the voltage Vt.in at the toggle input 27 changing from a voltage that is higher than the toggle threshold voltage to a voltage that is lower than the toggle threshold voltage. The predefined threshold voltage for the toggle circuitry 25 may be equal to or higher than the second threshold voltage for the second voltage domain. In fig 2, it is schematically indicated that the toggle circuitry 25 is coupled to power rails indicated by a relatively high supply potential V3 and a relatively low supply potential V4. The relatively high supply potential V3 is higher than the threshold voltage for the toggle circuitry 25, and may advantageously be the same as the above-mentioned first voltage Vi. The relatively low supply potential V4 is lower than the second threshold voltage, and may advantageously be the same as the above-mentioned second voltage V2.

It should be understood that the toggle circuitry 25 may, in principle, be implemented using any combination of circuitry elements providing the described functionality, and that it will be apparent to one of ordinary skill in the relevant art that various suitable toggle circuitry configurations are, perse, well known. Examples of such known suitable toggle circuitry configurations include a T flip-flop and a JK flip-flop.

The reset switch 31 is coupled between the first terminal 21 of the level shifting circuitry 19 and the toggle input 27, and has a reset switch control input 37 to allow control of the reset switch 31 between a non-conducting state and a conducting state in which the first terminal 21 of the level shifting circuitry 19 and the toggle input 27 are conductively connected through the reset switch 31 .

The resistive element 33 is connected in parallel with the reset switch 31 between the first terminal 21 of the level shifting circuitry 19 and the toggle input 27, for allowing a leakage current to flow from the first terminal 21 of the level shifting circuitry 19 through the resistive element 33, when the reset switch 31 has been controlled to its non-conducting state.

The pull-down circuitry 35 is coupled between the toggle input 27 and the second terminal 23 of the level shifting circuitry 19, and has an input 39 for receiving a control signal Vctri for the level shifting circuitry. The pull-down circuitry 35 is configured to open a current path from the toggle input 27 through the pull-down circuitry 35 in response to a transition of the control signal Vctri from a logic low voltage to a logic high voltage for the first voltage domain and in response to a transition of the control signal Vctri from a logic high voltage to a logic low voltage for the first voltage domain.

The configuration of the level shifting circuitry 19 described above with reference to fig 2 provides level shifting without “pull-up” circuitry that is controllable by the control signal Vctri, which is in the first voltage domain. In particular, due to the provision of the toggle circuitry 25 the output voltage Vout, in the second voltage domain, can be controlled using pull-down circuitry only. In particular, the pull-down circuitry 35 may be temporarily controllable from a non-conducting state to a conducting state by transitions of the control signal Vctri from logic low to logic high (in the first voltage domain) as well as by transitions of the control signal Vctri from logic high to logic low (in the first voltage domain). Furthermore, the reset switch 31 is controllable to conductively connect the toggle input 27 and the first terminal 21 of the level shifting circuitry 19, to thereby “pull up” the toggle input 27. By operating the reset switch 31 during a reset period between possible state transitions (logic low to logic high or logic high to logic low) of the control signal Vctri, each state transition of the control signal Vctri can cause the voltage Vt.in at the toggle input to be “pulled down” from a voltage above the threshold voltage for the toggle circuitry 25 to a voltage below the threshold voltage for the toggle circuitry 25. This, in turn, causes the toggle circuitry 25 to toggle the voltage at the toggle output 29 between logic low and logic high, in the second voltage domain. During the reset period between possible state transitions of the control signal Vctri and before operation of the reset switch 31 , the pulldown circuitry 35 may be controlled to close the current path from the toggle input 27 through the pull-down circuitry 35. This will allow the toggle input 27 to be pulled up between possible state transitions of the control signal Vctri.

The function of the resistive element 33 is to counter-act the leakage current of the pull-down circuitry 35, when the current path through the pulldown circuitry 35 is closed. Hereby, it can be prevented that “pull-down” occurs as a result of a long period without level transitions of the control signal Vctri. From the intended function of the resistive element 33 follows that the resistance can typically be very high, such as higher than 100 MQ. It will also be understood by one of ordinary skill in the relevant art that there are several ways to implement the resistive element 33, including using resistive structures and/or semiconductor circuitry. For example, the resistive element may be provided as a TFT-resistor, or as suitably configured TFT-transistor circuitry.

Fig 3 is a schematic illustration of level shifting circuitry 19 according to a second example embodiment of the present invention, and figs 4A-C are timing diagrams for assisting description of the operation of the level shifting circuitry in fig 3.

The second example embodiment of the level shifting circuitry 19 in fig 3 mainly differs from the first example embodiment in fig 2 in that a more detailed configuration of an example of the pull-down circuitry 35 in fig 2 is provided and in that an exemplary way of generating various internal control signals for the level shifting circuitry 19 are shown.

Referring first to the toggle circuitry 25, it comprises a second toggle output 45 providing an inverse V _ou t,n of the output voltage V _ou t at the first toggle output 29. Additionally, the toggle circuitry 25 comprises a delay element 47 and an AND-gate 49. Through the AND-combination of the output voltage Vout, and the delayed inverse signal V _ou t,n, the internal reset signal Vreset can conveniently be formed.

In the second example embodiment in fig 3, the pull-down circuitry 35 comprises switching circuitry 51 and routing circuitry 52. The switching circuitry 51 has a first terminal 40 connected to the toggle input 27, a second terminal 41 , and a third terminal 43. The switching circuitry 51 , which is here provided in the form of an NMOS transistor, may be configured to open the above-mentioned current path through the pull-down circuitry 35 when a voltage between the second terminal (here gate) 41 and the third terminal (here source) 43 of the switching circuitry 51 exceeds a predefined threshold voltage for the switching circuitry 51 . The routing circuitry 52 is coupled to the second terminal 41 and the third terminal 43 of the switching circuitry 51 , the input 31 of the pull-down circuitry 35, and at least one output of the toggle circuitry 25. The routing circuitry is configured to connect the control signal Vctri for the level shifting circuitry 19 to either the second terminal 41 or the third terminal 43 of the switching circuitry 51 depending on the output voltage Vout at the toggle output 29. In the example configuration of fig 3, the routing circuitry 52 is further configured to connect the third terminal 43 of the switching circuitry 51 to either the control signal Vctri for the level shifting circuitry 19 or a reference potential, in this example the above-mentioned second voltage V2, for the level shifting circuitry.

In the example configuration of fig 3, the routing circuitry 52 is implementing using a first switch 59 for controllably connecting the third terminal 43 of the switching circuitry 51 to the control signal Vctri, and a second switch 61 for controllably connecting the third terminal 43 of the switching circuitry 51 to the low reference potential V2. In addition, the routing circuitry comprises an third switch 63 for controllably adding the control signal Vctri potential to the second terminal 41 of the switching circuitry 51 , via a capacitor 65.

In fig 3, the pull-down circuitry 35 is also shown to comprise optional pre-biasing circuitry 53 controllable to provide a pre-bias voltage V5 to the second terminal 43 of the switching circuitry 51 . The pre-bias voltage V5 may be lower than the predefined threshold voltage for the switching circuitry 51 . In fig 3, the pre-bias voltage Vs is provided by a schematic constant voltage source 55. As is well known to those of ordinary skill in the relevant art, this functionality can be achieved using, for example, a diode or a diode-coupled transistor. Pre-biasing may increase the speed of switching of the level switching circuitry 19. It should, however, be noted that the level switching circuitry 19 according to embodiments of the present invention may be configured to operate without this optional pre-biasing circuitry 53.

An example operation sequence for the level shifting circuitry 19 in fig 3 will now be described with additional reference to figs 4A-C. At an initial time to, the control signal Vctri is at the logic low level for the first voltage domain (in this case indicated as 0V), and the output signal V _ou t and the reset signal V _re set are both at the logic low level for the second voltage domain (in this case indicated as 0V).

At this initial time to, the reset switch 31 has previously been operated, so that the toggle input 27 has been pulled up to the first reference potential Vi (such as 10V) for the level switching circuitry 19. Furthermore, the second terminal 41 of the NMOS transistor 51 in the pull-down circuitry 35 has previous been connected to the constant voltage source 55, but is now disconnected from the constant voltage source 55. The gate of the NMOS transistor 51 has therefore been pre-charged to the pre-bias voltage Vs, which is at or slightly below the threshold voltage of the NMOS transistor 51 . Since the output voltage signal V _ou t is low, the inverse output voltage signal V _ou t,n is high, so that the first switch 59 of the routing circuitry 52 is non-conducting, the second switch 61 of the routing circuitry 52 is conducting, and the third switch 63 of the routing circuitry 52 is conducting. The source of the NMOS transistor 51 is therefore at the low reference potential V2 (in this case 0V) of the level switching circuitry 19.

Referring to fig 4A, at a first time ti , the control voltage signal Vctri transitions from the logic low level to the logic high level for the first voltage domain. As a result, the logic high level voltage of the control voltage signal Vctri is added to the pre-bias voltage V5 already present at the gate of the NMOS transistor 51 , so that the gate-source voltage of the NMOS transistor 51 becomes sufficiently high to transition the NMOS transistor 51 from its non-conducting state to its conducting state. Due to this transition, the NMOS-transistor 51 will “pull down” the toggle input 27 so that the voltage Vt.in at the toggle input 27 becomes lower than the above-mentioned predefined threshold voltage for the toggle circuitry 25. As a consequence, the toggle circuitry will, at a second time t2, toggle the output signal V _ou t from the logic low level to the logic high level (for the second voltage domain) and toggle the inverse output signal V _ou t,n from the logic high level to the logic low level (for the second voltage domain).

Since the output voltage signal V _ou t is now high and the inverse output voltage signal V _ou t,n is low, the first switch 59 of the routing circuitry 52 becomes conducting, the second switch 61 of the routing circuitry 52 becomes non-conducting, and the third switch 63 of the routing circuitry 52 becomes non-conducting. The source of the NMOS transistor 51 is thus connected to the control voltage signal Vctri (which is now at the logic high level for the first voltage domain). As a consequence, the NMOS transistor 51 is controlled to transition from its conducting state to its non-conducting state.

Following an additional small delay caused by the AND-gate 49 in the toggle circuitry 25, the reset signal Vreset goes from the logic low level to the logic high level (for the second voltage domain) at a third time ts. This results in operation of the reset switch 31 , so that the toggle input 27 is pulled high, and in renewed connection of the pre-bias voltage source 55 to the gate of the NMOS transistor 51 . The latter transition, however, does not result in any change in the gate voltage of the NMOS transistor 51 , because the pre-bias voltage V5 is added to the control voltage signal Vctri, which is still at the logic high voltage for the first voltage domain.

At a fourth time t4, determined by the delay implemented by the delay element 47 of the toggle circuitry 25, the reset voltage signal Vreset again transitions to the low logic level (for the second voltage domain), so that the toggle input 27 becomes disconnected from the first reference voltage (except for the leakage current compensating path provided through the resistive element 33), and the gate of the NMOS transistor 51 of the pull-down circuitry 35 is again disconnected from the pre-bias voltage source 55. The level switching circuitry 19 is now ready for a transition of the control voltage signal from the high logic level to the low logic level (for the first voltage domain).

Referring to fig 4A, this transition takes place at a fifth time ts. The gate of the NMOS transistor 51 is now pre-biased to the pre-bias voltage Vs plus the logic high voltage level for the first voltage domain and disconnected from the control voltage signal Vctri, and the source of the NMOS transistor 51 is connected to the control signal Vctri. The transition of the control voltage signal Vctri from the high logic level to the low logic level therefore results in the gatesource voltage of the NMOS transistor 51 increasing from the pre-bias voltage Vs to the pre-bias voltage Vs plus the logic high voltage level for the first voltage domain. This causes the NMOS transistor 51 to transition from its non-conducting state to its conducting state, so that the voltage Vt.in at the toggle input 27 again becomes lower than the above-mentioned predefined threshold voltage for the toggle circuitry 25. As a consequence, the toggle circuitry will, at a sixth time te, toggle the output signal V _ou t from the logic low level to the logic high level (for the second voltage domain) and toggle the inverse output signal V _ou t,n from the logic high level to the logic low level (for the second voltage domain).

Since the output voltage signal V _ou t is now low and the inverse output voltage signal V _ou t,n is high, the first switch 59 of the routing circuitry 52 becomes non-conducting, the second switch 61 of the routing circuitry 52 becomes conducting, and the third switch 63 of the routing circuitry 52 becomes conducting. The source of the NMOS transistor 51 is thus connected to the low reference potential V2, resulting in an unchanged source potential, and the control voltage signal Vctri is connected to capacitor 65 and added to the gate of the NMOS transistor 51 .

Following an additional small delay caused by the AND-gate 49 in the toggle circuitry 25, the reset signal V _re set again goes from the logic low level to the logic high level (for the second voltage domain) at a seventh time t?. This results in operation of the reset switch 31 , so that the toggle input 27 is pulled high, and in renewed connection of the pre-bias voltage source 55 to the gate of the NMOS transistor 51 . This latter transition changes the gate voltage of the NMOS transistor 51 to the pre-bias voltage V5, so that the NMOS transistor 51 is controlled to transition from its conducting state to its nonconducting state.

At an eighth time ts, determined by the delay implemented by the delay element 47 of the toggle circuitry 25, the reset voltage signal V _re set again transitions to the low logic level (for the second voltage domain), so that the toggle input 27 becomes disconnected from the first reference voltage (except for the leakage current compensating path provided through the resistive element 33), and the gate of the NMOS transistor 51 of the pull-down circuitry 35 is again disconnected from the pre-bias voltage source 55. The level shifting circuitry 19 is now back in the same configuration as at the initial time to and is ready for a new transition of the control voltage signal Vctri from the low logic level to the high logic level (for the first voltage domain).

In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measured cannot be used to advantage.