BACKGROUND

[0001] Many printers include light emitting diodes (LEDs), which are used in stages of a printing operation. During printing, printing fluid may be applied to a substrate, which may be subsequently heated by the light or radiation output from the LEDs. In some examples, the LEDs may be used in a curing or drying stage of the printing operation.

BRIEF DESCRIPTION OF DRAWINGS

[0002] Non-limiting examples will now be described with reference to the accompanying drawings, in which:

[0003] Figure 1 is a simplified schematic of an example of circuitry for bypassing a faulty LED in a printer;

[0004] Figure 2 is another example of circuitry for bypassing a faulty LED in a printer;

[0005] Figure 3 is an example of signals during start-up of an apparatus for bypassing a faulty LED in a printer;

[0006] Figure 4 is a simplified schematic of an example of an LED module for bypassing a faulty LED in a printer;

[0007] Figure 5 is another simplified schematic of an example of an LED module for bypassing a faulty LED in a printer;

[0008] Figure 6 is a flowchart of an example of a method of bypassing a faulty LED;

[0009] Figure 7 is a flowchart of another example of a method of bypassing a faulty LED. DETAILED DESCRIPTION

[0010] As noted above, many printers include an array of LEDs, which may be used in post-processing during a printing operation, e.g., drying, curing and/or sublimating a printing fluid. To form the array, a plurality of series connected LEDs, also referred to as a string of LEDs, may be arranged together to form the array. Each plurality of series connected LEDs may be connected to a power source, such as a current source, which supplies power to the LEDs.

[0011] Due to the series connection of the LEDs, if one LED in a connection becomes faulty, this may create an open circuit fault that results in each LED of the series connection failing to conduct current and failing to output light. In such examples, if the printer continued to be operational, the processing provided by the LED array e.g. curing or drying, may not result in the desired effect, as the intensity of light output by the array may have decreased due to the faulty series of connected LEDs failing to output light. As a result, this may lead to a final printed product of poor quality. In such examples, the printer may therefore be shut down and cannot perform a printing operation until the LED array with the faulty LED is replaced. LEDs arrays can be complex and expensive parts, which may involve the intervention of a service engineer to replace the faulty LED array.

[0012] Examples according to the present disclosure present apparatuses and methods, which aim to bypass a faulty LED of string of LEDs in a printer, such that the string can continue to output light and the printer can carry out a printing operation even with a string of LEDs comprising the faulty LED.

[0013] Figure 1 is an example of circuitry 100 for bypassing a faulty LED in a printer. The circuitry 100 comprises a first terminal 102 to connect to a first LED node of an LED of a plurality of LEDs connected in series in an LED module of a printer. Circuitry 100 further comprises a second terminal 104 to connect to a second LED node of the LED. Circuitry 100 further comprises a switch 106 connected between the first and second terminals 102, 104 and to bypass the LED. Circuitry 100 further comprises a fault detection circuit 108 to detect a characteristic voltage indicative of a fault associated with the LED. Responsive to the detection of the characteristic voltage, the fault detection circuit 108 is further to activate the switch 106 to bypass the LED.

[0014] Circuitry 100 may thus be operable to bypass a faulty LED by activating a switch connected in parallel with the faulty LED. By bypassing the faulty LED, the switch conducts a current and thus, the remaining non-faulty LEDs of the plurality of series connected LEDs may continue to output light. As such, a printer may perform a printing operation with the plurality of series connected LEDs, comprising the faulty LED, and the printer may not need to be shut down in response to detecting the faulty LED.

[0015] Figure 2 is another example of circuitry 200 for bypassing a faulty LED in a printer. Circuitry 200 comprises a first terminal 202 to connect to a first LED node 210 of an LED 212 of a plurality of LEDs 214 connected in series. In some examples, each of the LEDs of the plurality may comprise an ultraviolet (UV) LED to output UV light. Circuitry 200 further comprises a second terminal 204 to connect to a second LED node 216 of the LED 212. In the illustrated example of Figure 2, the plurality of LEDs 214 comprises 16 LEDs. In some examples, the plurality of LEDs 214 may be arranged in an array in an LED module of a printer. In such examples, the LED module may comprise an array of LEDs comprising a plurality of the plurality of LEDs 214.

[0016] An operating current may be supplied to the plurality of LEDs 214 from current source 218. Current source 218 may be powered by a power source 220. In some examples, the current source 218 supplies a nominal current of about 890 mA to the plurality of LEDs 214 and the power source 220 may drive the current source 218 with a nominal voltage of about 60 V. In such examples, under normal operating conditions where none of the plurality of LEDs 214 are faulty, a voltage of about 3.7 V may be applied across each of the 16 LEDs of the plurality of LEDs 214.

[0017] Circuitry 200 further comprises a switch 206 connected between the first terminal 202 and the second terminal 204 and operable to bypass the LED 212. In some examples, switch 206 may comprise a transistor, such as, a field-effect transistor (FET), a metal-oxide-semiconductor FET (MOSFET), a junction-gate FET (JFET) or a bipolar junction transistor (BJT). In the illustrated example of Figure 2 switch 206 comprises an n-channel MOSFET (nMOS). As will be described in more detail below, upon detection that LED 212 is faulty, switch 206 may be activated to bypass the LED 212. For example, an activation voltage may be applied to a terminal of the transistor for controlling the conduction of the transistor, such that the transistor is turned on. In the illustrated example of Figure 2, the activation voltage may thus comprise a gate voltage, which may be applied to the gate terminal 222 of switch 206 to turn the switch on to bypass the LED 212. Under normal operating conditions, when LED 212 is not faulty, an activation voltage or a gate voltage sufficient to turn on the switch 206 may thus not be applied to the gate terminal 222 and the switch 206 may be turned off. In such examples, with the switch 206 turned off, switch 206 may not bypass the LED 212.

[0018] Circuitry 200 further comprises a reference node 224 connected to the second terminal 204. In the illustrated example of Figure 2, the reference node comprises a floating ground node. Circuitry 200 further comprises voltage sense circuitry 226 connected to the first terminal 202. The voltage sense circuitry 226 may receive a voltage from the first LED node 210, via the first terminal 202, and output a characteristic voltage, indictive of a fault associated with the LED 212, with respect to the reference node 224. Thus, in the illustrated example of Figure 2, voltage sense circuit 226 comprises a voltage divider formed of first resistor 228 and second resistor 230 to output the characteristic voltage with respect to the reference node 224.

[0019] Circuitry 200 further comprises fault detection circuit 208 to detect a characteristic voltage indicative of a fault associated with the LED 212. In some examples, the fault detection circuit may comprise logic circuitry to detect the fault associated with the LED 212. In the illustrated example of Figure 2, the logic circuitry of the fault detection circuit 208 comprises first NOR gate 234 and second NOR gate 236. In the illustrated example of Figure 2, the first NOR gate 234 and the second NOR gate 236 are arranged in a flip-flop circuit. In some examples, the fault detection circuit 208 comprises a comparator circuit comprising a first input to connect to the first LED node 210 to receive a first voltage and a second input connected to a terminal of the switch 206 for controlling the conduction of the switch 206, such as the gate terminal 222 of the switch 206, to receive a second voltage. The comparator circuit may detect the characteristic voltage based on a comparison of the first voltage to the second voltage. In the illustrated example of Figure 2, the comparator circuit comprises the first NOR gate 234 comprising a first input 232 to receive the first voltage from first LED node 210. The first NOR gate 234 may thus receive the voltage output from voltage sense circuit 226 at the first input 232. First NOR gate 234 further comprises a second input 238 connected to the gate terminal 222 of switch 206 to receive a second voltage.

[0020] The signal output from the first NOR gate 234 is received at a first input of the second NOR gate 236. The second NOR gate 236 may further receive a reset signal supplied from reset node 240 at a second input of the second NOR gate 236. The reset signal may comprise a two-level logic signal with may take a high or low value, which may be referred to as 1 and 0, respectively. As will be described in more detail below, the reset signal at logic level 1 may be applied to the flip-flop circuit formed of first NOR gate 234 and second NOR gate 236, to reset the flip-flop circuit. The second NOR gate 236 may thus compare the output of the first NOR gate 234 and the reset signal and output a voltage to the gate terminal 222 of switch 206. The voltage output from second NOR gate 236 may thus control operation of the switch 206. For example, the second NOR gate 236 may output a voltage signal with a logic level 1 or 0 depending on the signals received at the inputs of the second NOR gate 236, as will be described in more detail below. A logic level 1 output from the second NOR gate 236 may correspond to a voltage signal to apply an activation voltage to a terminal of the switch 206 to turn on the switch 206. For example, the activation voltage may comprise a gate voltage applied to the gate terminal 222 to turn on the switch 206 to bypass the LED 212. A logic level 0 output from the second NOR gate 236 may correspond to a voltage signal applied to the gate terminal 222 which may not turn on the switch 206 to bypass the LED 212. In some examples, a logic level 0 output from the second NOR gate 236 may correspond to a voltage signal applied to a terminal of the switch 206 which may turn off the switch 206.

[0021] The truth table for the flip-flop circuit formed of first NOR gate 234 and second NOR gate 236 is presented in table 1:

Table 1

[0022] As illustrated in Figure 2, ‘s’ is the logic signal input to the first input 232 of the first NOR gate 234, which in some examples may be referred to as the set signal s. ‘r’ is the reset signal which is received at the second input of the second NOR gate 236 from the reset node 240. ‘n’ and ‘m’ are the outputs of the first NOR gate 234 and the second NOR gate 236, respectively. In some examples, the output of the second NOR gate 236 may correspond to the output of the fault detection circuit 208.

[0023] As will be described in more detail below, on start-up of the circuitry 200, a reset signal of logic level 1 may be applied to the second input of the second NOR gate 236. From Table 1 above, this may reset the flip-flop circuit such that the signal m is reset to logic level 0. In some examples, the signal output from the second NOR gate 236 and thus the fault detection circuit 208 may thus be a logic level 0. In some examples, this may thus apply a second voltage to the gate terminal of the 222 of the switch 206, which is not sufficient to turn on the switch 206 to bypass the LED 212. Following this reset operation, the reset signal may then be output to the second input of the second NOR gate 236 at logic level 0.

[0024] Following the reset operation and under normal operating conditions where all of the of the LEDs of the plurality of LEDs 214 are not faulty and are supplied with a current, the first voltage signal supplied to the first input 232 of the first NOR gate 234 or the set signal s, may be a magnitude which is received at the first input 232 as a logic level of 0. In one example, the voltage at the first LED node 210 may be about 3.7 V. The voltage sense circuit 226 may receive this voltage and provide appropriate scaling of the voltage such that a first voltage signal is output to the first input 232 of first NOR gate 234, at a magnitude which is considered a set signal s of logic level 0. As described above, following the reset operation and under such operating conditions, the reset signal r may also be input to the second input of the second NOR gate 236 at a logic level of 0. As such, from the truth table displayed in Table 1 above, when the set signal s and the reset signal r are both at logic level 0, the outputs of the NOR gates m and n, do not change and maintain their value from the previous state of the flip flop circuit. Due to the reset operation described above, the output of the second NOR gate 236 may thus be a voltage signal at logic level 0, as this was the logic level of the signal applied in response to the reset condition. This voltage signal may correspond to a voltage signal with a magnitude which is not sufficient to turn on the switch 206 to bypass the LED 212. The LED 212 may thus not be faulty and conduct a current to output light.

[0025] In response to a fault at the LED 212, the voltage received at the first input of the first input 232 of the first NOR gate 234 or the set signal s, may increase in magnitude, such that the set signal s is received at a logic level of 1. In some examples, the detection of such a voltage at the fault detection circuit 208 may comprise a characteristic voltage indicative of a fault associated with the LED. For example, the voltage at the first LED node 210 may increase by a factor based on the number of LEDs forming the plurality 214. For example, the voltage at the first LED node 210 may increase by a factor of 16 to about 60 V. In some examples, such a voltage magnitude may damage components of the circuitry 200. Thus, in some examples, voltage sense circuitry 226 may again scale the voltage such that a first voltage is output to the first input 232 of first NOR gate 234, at a magnitude which is considered a set signal of logic level 1 , but may not damage the circuitry 200. The reset signal r may also be input to the second input of the second NOR gate 236 at a logic level of 0. As such, from the truth table displayed in Table 1 above, the output of the second NOR gate 236 may be a voltage signal at logic level 1. This voltage signal may correspond to an activation voltage signal with a magnitude which is sufficient to turn on the switch 206 to bypass the LED 212. Thus, in some examples, the fault detection circuit 208 may, responsive to the detection of the characteristic voltage, activate the switch 206 to bypass the LED 212. For example, the voltage signal output form the second NOR gate 236 and, as such, the fault detection circuit 208, may comprise a gate voltage applied to the gate terminal of the switch 206 to activate the switch 206 to bypass the LED 212. In such examples, the activation of the switch 206 to bypass the LED 212, which may have become faulty, enables the remaining LEDs of the plurality 214, which may not be faulty, to conduct a current and output light. Thus, in some examples, the LED 212 becoming faulty may not prevent the remaining LEDs of the plurality 214 from outputting light.

[0026] In some examples, following activating the switch 206 to bypass the LED 212, the fault detection circuit may further maintain the switch 206 in an active state to bypass the LED 212, responsive to not detecting the characteristic voltage indicative of a fault associated with the LED 212. For example, following activation of the switch 206, the voltage at the first LED node 210 may decrease. In such examples, the voltage received at the first input 232 of the first NOR gate 234 may comprise a magnitude corresponding to a set signal s of logic level 0. The reset signal r may again be maintained at logic level 0. From Table 1 above, with these set signal s and reset signal r values, the outputs m, n of the NOR gates 234, 236 does not change and they maintain their previous values. Thus, the output of the second NOR gate 236 and thus the fault detection circuit 208 does not change and continues to apply an activation voltage, such as a gate voltage to the switch 206 sufficient to maintain the switch 206 in an active state to conduct a current to bypass the LED 212. Thus, in some examples, the fault detection circuit 208 may comprise a memory to store a state indicative that the fault associated with the LED has been detected, and wherein responsive to not detecting the characteristic voltage, the fault detection module is to maintain the switch 206 in the active state based on the state of the memory. In the illustrated example of Figure 2, the flip-flop circuit formed of first and second NOR gates 234, 236, may thus comprise the memory of the fault detection circuit 208. The fault detection circuit 208 may thus control the switch 206 based on the set and reset signal s, r and the previous state of the flipflop circuit.

[0027] Circuitry 200 further comprises a supply node 242 to provide a supply voltage to the fault detection circuit 208. The supply voltage may thus further be provided to the first NOR gate 234 and the second NOR gate 236. In some examples, the supply voltage received at the fault detection circuit may be about 5 V.

[0028] Circuitry 200 further comprises first diode 244, second diode 246 and first capacitor 248. In some examples, circuitry 200 may comprise a charge pump circuit to supply the supply voltage to the fault detection circuit 208. In the illustrated example of Figure 2, first diode 244, second diode 246 and first capacitor 248 are arranged in a charge pump circuit. In such examples, the first capacitor 248 may act as a reservoir capacitor, which may be charged and discharged by application of the voltage output from the supply node 242. As will be described in more detail below, the voltage output from the supply node 242 may comprise a pulse-width modulated (PWM) signal, which may take one of a high and low value to cause the first capacitor 248 to be charged and discharged.

[0029] Circuitry 200 further comprises second capacitor 250, third capacitor 252 and fourth capacitor 254. The second capacitor 250, third capacitor 252 and fourth capacitor 254 may provide capacitive isolation for the supply node 242, reset node 240 and reference node 224, respectively.

[0030] Circuitry 200 further comprises third diode 256 and third resistor 258. In some examples, third diode 256 and third resistor 258 may provide conditioning of the reset signal output from the reset node 240.

[0031] Circuitry 200 further comprises 5V float node 260 and reset float node 262. The signals present at these nodes will be described in more detail below with respect to Figure 3.

[0032] Figure 3 illustrates signals present in circuitry 200 during a start-up procedure of the circuitry 200. The operation of the circuitry described with reference to Figure 3 may thus be used to reset the fault detection circuit 208 and thus the flip-flop circuit formed of first NOR gate 234 and second NOR gate 236, during the start-up procedure of the circuitry 200. Figure 3 illustrates the signals present at nodes, which are labelled in Figure 2. [0033] In a first block of the start-up procedure, a PWM voltage signal is output from the supply node 242. In the illustrated example of Figure 3, the PWM voltage signal is output with a 50% duty cycle. The PWM voltage signal charges and discharges the first capacitor 248 and supplies a supply voltage to the fault detection circuit 208. As illustrated in Figure 3, the voltage at 5V float node 260 is charged up over a first period 302 by application of the PWM signal before levelling off over the second period 304. Once the voltage at the 5V float node 260 has levelled off, a constant supply voltage may be provided to the fault detection circuit 208 to power up the circuit.

[0034] In a second block of the start-up procedure, after the voltage at the 5V float node 260 has levelled off and the fault detection circuit 208 has powered on, the reset node 240 pulses the reset signal to a logic level 1 , before returning the reset signal to logic level 0. The reset signal is received at the reset float node 262 and may thus be applied to an input of the fault detection circuit 208 to reset the fault detection circuit 208. As illustrated in Figure 3, due to the coupling of third capacitor 252 between the reset node 240 and the fault detection circuit 208, the third capacitor 252 is charged up by the application of the reset signal at a logic level 1 and then discharges over a period of time after the reset signal falls back to logic level 0. As described above and from Table 1 , the application of the reset signal at logic level 1 resets the flip-flop circuit and thus the fault detection circuit 208, such that, the output m 238 of the second NOR gate 236 is a voltage signal at logic level 0, as illustrated in Figure 3. In such examples, the voltage output from the fault detection circuit 208 may thus be a voltage which is not sufficient to turn on the switch 206 to bypass the LED 212. Therefore, in a third block of the start-up procedure, power is supplied to the current source 218 to provide a current to the plurality of the LEDs 214 to output light.

[0035] In some examples, the start-up procedure described above may provide a method to reset the fault detection circuit 208 on start-up. For example, on start-up a processor monitoring the fault detection circuit may be unaware of the state that the fault detection circuit is configured in. As such, by applying a supply voltage to the fault detection circuit 208 and the reset signal to the fault detection circuit 208, the processor can then be assured that the fault detection circuit has been reset such that the switch 206 is not activated to bypass the LED 212 before the current is supplied to the LED 212.

[0036] In some examples, circuitry corresponding to circuitry 100 or circuitry 200 may be connected across each of the LEDs of the plurality of LEDs 214. The circuitry connected across each of the LEDs of the plurality 214 may thus be operable to bypass each of the LEDs of the plurality 214 in the event of a fault occurring at any of the plurality 214. In some examples an LED array may comprise circuitry corresponding to circuitry 100 or circuitry 200 connected across each LED of the array operable to bypass each of the LEDs of the plurality 214 in the event of a fault occurring at any of the LEDs of the array.

[0037] Referring again to Figure 2, in some examples, circuitry 200 may further comprise control circuitry 264 to adjust a printing operation of the printer responsive to bypassing the LED. For example, the control circuitry 264 may monitor the plurality of LEDs 214 to detect a condition that one of the LEDs of the plurality 214 has been bypassed. For example, the control circuitry 264 may monitor a voltage across the plurality of LEDs and a detection that the voltage has decreased below a threshold value may be indicative that an LED of the plurality 214 has been bypassed. For example, under normal operating conditions where each of the LEDs 214 conduct a current the voltage across the plurality 214 may be N*k V, where N is the number of LEDs in the plurality and k is the voltage value across each LED. In response to an LED being bypassed, the voltage across the plurality 214 may decrease to (N-1)*k V. This decrease may be detected by the control circuitry 264 as a condition indicative that an LED of the plurality has been bypassed. In some examples the control circuitry 264 may comprise a microcontroller.

[0038] In some examples, to adjust the printing operation of the printer, the control circuitry 264 may increase a current through the plurality of LEDs 214. For example, the control circuitry 264 may adjust the current applied to the plurality of LEDs 214 by controlling the current source 218 to increase the current applied to the plurality of LEDs 214. For example, the increase in current may increase the power through each of the remaining non-faulty LEDs of the plurality 214, which may therefore increase the intensity of light output from the plurality of LEDs 214. In examples, where the plurality of LEDs are part of a curing or drying module of a printer, the increase in power and thus light intensity may enable the plurality of LEDs 214, with the faulty LED, to perform the drying or curing operation.

[0039] In some examples, to adjust the printing operation of the printer, the control circuitry 264 may reduce a printing speed of the printing operation. For example, the reduction in the voltage across the plurality of LEDs 214 may reduce the output power of the plurality of LEDs 214. In examples where the plurality of LEDs 214 are comprised in a curing module or drying module of the printer, the reduction in output power may reduce the speed at which plurality of LEDs 214 are able to perform the curing or drying. Therefore, by reducing the printing speed or the speed at which the printing substrate is passed under the plurality of LEDs 214 for illumination, the plurality of LEDs outputting the reduced power may be able to sufficiently perform the curing or drying operations.

[0040] In some examples, to adjust the printing operation of the printer the control circuitry 264 may implement a combination of adjustments. For example, the control circuitry 264may increase the current through the plurality of LEDs 214 and reduce the printing speed. In some examples, the adjustment to the printing operation may be selectable by a user of the printer. In some examples, the above-described functionality of the control circuitry 264 may be performed by a processor of a printer.

[0041] Figure 4 is an example of an LED module 400 of a printer. The LED module 400 comprises a plurality of series connected LEDs 402. The LED module 400 further comprises a switch 404 connected in parallel with an LED of the plurality of series connected LEDs 402. The LED module 400 further comprises a detection module 406 to detect a characteristic signal from the LED indicative of a fault associated with the LED and responsive to the detection of the characteristic signal, activate the switch 404 to bypass the LED.

[0042] In some examples, the switch 404 may comprise a transistor, such as a field-effect transistor (FET), a metal-oxide-semiconductor FET (MOSFET), a junctiongate FET (JFET) or a bipolar junction transistor (BJT). In some examples, the detection module may comprise a memory to store a state indicative that the fault associated with the LED has been detected, and wherein responsive to no longer detecting the characteristic signal, the detection module is to maintain the switch in an active state based on the state of the memory. Thus, in some examples, the fault detection module 406 may comprise a fault detection circuit such as that descried above with reference to Figure 2. In other examples, the fault detection module 406 may comprise a processor operable to perform at least some of the above discussed functionality of the fault detection circuit 208 described above with reference to Figure 2.

[0043] Figure 5 is another example of LED module 400 further comprising a processor 508. In some examples, the processor 508 may adjust a printing operation of the printer responsive to bypassing the LED. [0044] Figure 6 is a flowchart of an example of a method 600. The method 600 comprises, in a block 602, detecting a fault of one LED of a series connected string of LEDs to output light in a printer. The method 600 further comprises, in a block 604, responsive to detecting the fault of the one LED, bypassing the one LED, such that, the series connected string of LEDs continues to output light.

[0045] Figure 7 is a flowchart of another example the method 600. In some examples, the method 600 may further comprise, in block 706, adjusting a printing operation of the printer responsive to bypassing the one LED. In some examples, adjusting the printing operation may comprise increasing a current through the series connected string of LEDs. In some examples, adjusting the printing operation may comprise reducing a printing speed of the printing operation.

[0046] Examples in the present disclosure can be provided as methods, systems or machine readable instructions, such as any combination of software, hardware, firmware or the like. Such machine readable instructions may be included on a computer readable storage medium (including but not limited to disc storage, CD-ROM, optical storage, etc.) having computer readable program codes therein or thereon.

[0047] The present disclosure is described with reference to flow charts and/or block diagrams of the method, devices and systems according to examples of the present disclosure. Although the flow diagrams described above show a specific order of execution, the order of execution may differ from that which is depicted. Blocks described in relation to one flow chart may be combined with those of another flow chart. It shall be understood that each block in the flow charts and/or block diagrams, as well as combinations of the blocks in the flow charts and/or block diagrams can be realized by machine readable instructions.

[0048] The machine readable instructions may, for example, be executed by a general purpose computer, a special purpose computer, an embedded processor or processors of other programmable data processing devices to realize the functions described in the description and diagrams. In particular, a processor or processing apparatus may execute the machine readable instructions. Thus functional modules of the apparatus and devices may be implemented by a processor executing machine readable instructions stored in a memory, or a processor operating in accordance with instructions embedded in logic circuitry. The term ‘processor’ is to be interpreted broadly to include a CPU, processing unit, ASIC, logic unit, or programmable gate array etc. The methods and functional modules may all be performed by a single processor or divided amongst several processors.

[0049] Such machine readable instructions may also be stored in a computer readable storage that can guide the computer or other programmable data processing devices to operate in a specific mode.

[0050] Such machine readable instructions may also be loaded onto a computer or other programmable data processing devices, so that the computer or other programmable data processing devices perform a series of operations to produce computer-implemented processing, thus the instructions executed on the computer or other programmable devices realize functions specified by block(s) in the flow charts and/or block diagrams.

[0051] Further, the teachings herein may be implemented in the form of a computer software product, the computer software product being stored in a storage medium and comprising a plurality of instructions for making a computer device implement the methods recited in the examples of the present disclosure.

[0052] While the method, apparatus and related aspects have been described with reference to certain examples, various modifications, changes, omissions, and substitutions can be made without departing from the spirit of the present disclosure. It is intended, therefore, that the method, apparatus and related aspects be limited only by the scope of the following claims and their equivalents. It should be noted that the above-mentioned examples illustrate rather than limit what is described herein, and that those skilled in the art will be able to design many alternative implementations without departing from the scope of the appended claims.

[0053] The word “comprising” does not exclude the presence of elements other than those listed in a claim, “a” or “an” does not exclude a plurality, and a single processor or other unit may fulfil the functions of several units recited in the claims.

[0054] The features of any dependent claim may be combined with the features of any of the independent claims or other dependent claims.