Title:
LOCAL AMPLIFICATION CIRCUIT, DATA READOUT METHOD, AND MEMORY
Document Type and Number:
WIPO Patent Application WO/2023/133973
Kind Code:
A1
Abstract:
The present disclosure relates to the field of semiconductor circuit design, and in particular to a local amplification circuit, a data readout method, and a memory. The local amplification circuit comprises: a write control transistor (101), configured to connect a global data line to a local data line on the basis of a write enable signal; a column select transistor (102), configured to connect a bit line to the local data line on the basis of a column select signal; a first control PMOS transistor (110), a gate being connected to the local data line, and one end of a source or drain being connected to the global data line, and the other end being connected to a read control transistor (103); a second control PMOS transistor (120), a gate being connected to a complementary local data line, and one end of a source or drain being connected to a complementary global data line, and the other end being connected to the read control transistor (103); and the read control transistor (103), configured to, on the basis of a read enable signal, pull up/down terminals of the first control PMOS transistor (110) and the second control PMOS transistor (120) connected to the read control transistor (103) to a preset level, thereby shortening a time interval between the column select signal and the read enable signal.
Inventors:
WANG YING (CN)
Application Number:
PCT/CN2022/078105
Publication Date:
July 20, 2023
Filing Date:
February 25, 2022
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
G11C7/10
Foreign References:
| CN113760174A | 2021-12-07 | |||
| CN113760173A | 2021-12-07 | |||
| CN113823342A | 2021-12-21 | |||
| US20110116334A1 | 2011-05-19 |
Attorney, Agent or Firm:
SHANGHAI CHENHAO INTELLECTUAL PROPERTY LAW FIRM GENERAL PARTNERSHIP (CN)
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