BACKGROUND

Beamforming systems in wireless networks, e.g., beamforming transmitters, beamforming receivers, etc., provide directional signal control by combining signals transmitted or received by two or more antenna elements of an antenna array such that signals at particular angles experience constructive interference, while other signals experience destructive interference. Such directional control provides improved coverage and less interference in the wireless network. For simplicity, the following refers to beamforming transmitters. It will be appreciated, however, that the problems and solutions discussed herein apply to any element utilizing beamforming or phase control, including beamforming receivers.

The directional control of beamforming transmitters may be achieved by controlling the phase and relative amplitude of the signal applied to each antenna element. Thus, the performance of the beamforming transmitter is inextricably tied to the accuracy of the phase control of each antenna element. Some systems implement local oscillator beamforming, which involves phase shifting the local oscillator (LO) signal for each antenna element to achieve the desired phase shift for the corresponding antenna element. Such phase control of the LO signal requires good control of the static phase differences between the separate transmitters.

The static phase differences between the transmitters, however, can be difficult to predict. For example, an integrated direct upconversion radio typically produces the upconversion mixing signal by dividing the LO signal with, e.g., a digital quadrature frequency divider. Such a divider may start up in any one of its possible internal states, where each state is associated with a different phase. This is a problem for beamforming transmitters, particularly in time-division duplex (TDD) systems, where each transmitter is powered down between transmission slots. Because each antenna element has its own transmitter, the resulting radiation pattern will constantly change between the transmission slots because the initial phase for each antenna element is unknown every time the transmitter is powered back on. This same problem also exists for TDD beamforming receivers, and transmitters and/or receivers in Multiple Input, Multiple Output (MIMO) systems. Thus, there remains a need for accounting for such start-up phase variations when controlling the phase of the antenna signals.

SUMMARY

The solution presented herein determines an initial phase of each output signal generated by a plurality of radio frequency (RF) front-end circuits by mixing an input signal with a mixing signal in a mixer of the corresponding RF front-end circuit. To that end, the solution presented herein measures a time difference for each of the plurality of RF front-end circuits by measuring a time difference between a reference signal (common to all of the RF front-end circuits) and each mixing signal. The initial phase for each output signal is then determined based on the measured time difference for the corresponding RF front-end circuit. In so doing, the solution presented herein accounts for any uncertainty of the phase when the RF front-end is activated, enabling the phase of the corresponding antenna element to be accurately controlled.

One exemplary embodiment provides a method of determining an initial phase of each output signal generated by a plurality of RF front-end circuits, each of said RF front-end circuits comprising a mixer configured to mix an input signal with a mixing signal to generate the output signal for that RF front-end circuit. The method comprises generating a reference signal common to the plurality of RF front-end circuits. For each of the plurality of RF front- end circuits, the method further comprises measuring a time difference between a start edge of the reference signal and a stop edge of the corresponding mixing signal. The start edge defines a beginning of a measurement period and each stop edge defines an end of the measurement period for the corresponding RF front-end circuit. The method further comprises determining the initial phase of each output signal from the time difference measured for the corresponding RF front-end circuit.

An exemplary wireless transceiver comprises a plurality of RF front-end circuits, a reference circuit, and a plurality of time measurement circuits, one for each RF front-end circuit. Each of the RF front-end circuits comprises a mixer configured to mix an input signal with a mixing signal to generate an output signal for that RF front-end circuit. The reference circuit is configured to generate a reference signal common to the plurality of RF front-end circuits. Each time measurement circuit is operatively connected to an input of the corresponding mixer and the reference circuit. Further, each time measurement circuit is configured to measure a time difference between a start edge of the reference signal and a stop edge of the mixing signal of the corresponding RF front-end circuit. The start edge defines a beginning of a measurement period, and each stop edge defines an end of the measurement period for the corresponding RF front-end circuit. The wireless transceiver is configured to determine the initial phase of each output signal from the time difference measured for the corresponding RF front-end circuit.

In another exemplary embodiment, a computer program product stored in a non- transitory computer readable medium controls a phase of each of a plurality of radio frequency (RF) front-end circuits of a wireless transceiver. The computer program product comprises software instructions which, when run on the wireless transceiver, causes the wireless transceiver to generate an output signal for each RF front-end circuit by mixing an input signal with a mixing signal, and generate a reference signal common to the plurality of RF front-end circuits. The software instructions further cause the wireless transceiver to measure a time difference between a start edge of the reference signal and a stop edge of the mixing signal of the corresponding RF front-end circuit. The start edge defines a beginning of a measurement period and wherein each stop edge defines an end of the measurement period for the corresponding RF front-end circuit. The software instructions further cause the wireless transceiver to determine an initial phase of each output signal from the time difference measured for the corresponding RF front-end circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 shows an exemplary block diagram for beamforming system.

Figure 2 shows a block diagram for a beamforming transmitter according to one exemplary embodiment.

Figure 3 shows an exemplary block diagram for a transmission RF front-end for the beamforming system of Figure 1.

Figure 4 shows a phase determination method according to one exemplary embodiment.

Figure 5 shows an exemplary signaling diagram for determining the initial phase according to one exemplary embodiment.

Figure 6 shows an exemplary signaling diagram for determining the initial phase according to another exemplary embodiment.

Figure 7A shows one exemplary circuit implementation for the TDC.

Figure 7B shows an exemplary signaling diagram for the TDC of Figure 7A.

Figure 8 shows a block diagram for a beamforming transmitter according to another exemplary embodiment.

Figure 9 shows an exemplary signaling diagram for determining the initial phase according to another exemplary embodiment.

Figure 10 shows an exemplary block diagram for a reception RF front-end for the beamforming system of Figure 1.

Figure 1 1 shows a block diagram for a beamforming receiver according to one exemplary embodiment.

DETAILED DESCRIPTION

Figure 1 shows a beamforming system 10 comprising an antenna array 20 with M antenna elements 22, where the m' ^h antenna element 22 is coupled to the m' ^h radio frequency (RF) front end 30. Each RF front end 30 comprises a phase-locked loop (PLL) 32, as shown in Figure 2. One way to control the direction of the beam for the antenna element 22is to have the PLL 32 control the phase of the PLL output signal responsive to an input control signal input to the PLL 32 relative to the reference clock. In some

embodiments, the PLL control signal indicates the desired phase shift of the PLL output signal, where the desired phase shift was determined by a controller (not shown) external to the PLL 32, e.g., an array controller, based on a location of the antenna element 22 in the antenna array 20, a desired beam direction, and/or a desired beam shape. In other embodiments, the PLL control signal indicates the location of the antenna element 22 in the antenna array 20, the desired beam direction, and/or the desired beam shape, and the PLL 32 determines or otherwise selects the desired phase shift based on the information provided by the PLL control signal. The phase of the transmitter, and thus the direction of the beam, may also or additionally be controlled by rotating the phase of the digital or analog baseband signal applied to the corresponding RF front-end 30. For example, the phase of the digital baseband signal may be rotated by a desired amount. After rotation, the digital baseband signal may be converted to an analog signal and applied to the corresponding RF front-end 30 for upconversion and transmission.

It will be appreciated that Figure 1 shows a simplified block diagram of the exemplary beamforming system 10. Other components not pertinent to the discussion have been excluded from the drawings for simplicity.

The following will first describe the embodiments disclosed herein in terms of a beamforming transmitter 100, such as shown in Figure 3. It will be appreciated, however, that the embodiments disclosed herein apply to other beamforming elements, e.g., beamforming receivers (Figures 10 and 1 1 ), and/or any similar system requiring knowledge of an initial phase for phase control.

Figure 2 shows a block diagram of an exemplary RF front-end 30, e.g., the m ^th RF front-end of the beamforming system 10 shown in Figure 1 . Each RF front-end 30 comprises a phase-locked loop (PLL) 32, a divider 34 operatively coupled to an output of the PLL 32, an upconversion mixer 36 operatively coupled to an output of the divider 34, and an amplifier 38 operatively coupled to an output of the mixer 36. PLL 32 outputs a signal at a desired PLL frequency f _L0 responsive to a reference signal. Divider 34 divides the frequency f _L0 of the PLL output signal by N to achieve a mixing signal S _mix at a desired radio frequency, where N may be a fraction or an integer. Upconversion mixer 36 upconverts an input signal S ₇ responsive to the frequency of the mixing signal S _mix . An amplifier 38, e.g., a power amplifier, amplifies the upconverted signal to generate the output signal S _out (m) , e.g., a transmission signal for transmission by the corresponding antenna element 22.

As shown in Figure 3, transmitter 100 also includes a reference circuit 40 and plurality of time measurement circuits 50, e.g., a Time-to-Digital Converter (TDC), one for each RF front-end circuit 30. The reference circuit 40 is configured to generate a reference clock signal S _R common to the plurality of RF front-end circuits 30. Reference circuit 40 may comprise any known clock circuit capable of generating a reference clock signal at the desired frequency. Further, while not required, the reference clock signal S _R output by reference circuit 40 may also be used as the phase-locked loop reference signal provided to the phase-locked loop 32 in each RF front-end circuit 30.

Each TDC 50 is operatively connected to the reference clock circuit 40 to receive the common reference clock signal S _R , and to the corresponding RF front-end circuit 30 to receive the mixing signal S _mix generated by that RF front-end circuit 30. Each TDC 50 measures a time difference related to the current phase of the corresponding mixing signal S _mjx , and determines the initial phase for the output of the corresponding RF front-end circuit

30 based on the measured time difference. By using a common reference signal for all time difference measurements/initial phase determinations, the solution presented herein makes sure that the time difference measurements executed by each TDC 50 occur simultaneously, e.g., with the next edge of the reference clock signal. As a result, the correct initial phase can be determined for each output signal. The TDC 50 may output the time difference, or may compute the initial phase from the time difference, e.g., according to Equation (1 ), and output the computed initial phase.

More particularly, Figure 4 shows an exemplary method 200 for determining the initial phase of each output signal S _out generated by each of the plurality of RF front-end circuits 30. After reference circuit 40 generates the reference signal S _R (block 210), the TDC 50 measures the time difference At(m) for the m' ^h RF front-end circuit 30 by measuring a difference between a start edge t _ed (S _R ) of the reference clock signal S _R and a stop edge t _edge (S _mix (m)) of the mixing signal S _mix (block 220) for the m ^th RF front-end circuit 30. The transmitter 100 determines the initial phase of the output signal, in this case transmission signal S _out (m) , output by each RF front-end circuit 30 as a function of the corresponding measured time difference (block 230).

Figures 5 and 6 show signaling diagrams illustrating the time measurement process of Figure 4 according to various embodiments. The TDC 50 triggers on an edge of the reference clock signal S _R , e.g., a rising edge, and measures how long after that rising edge the mixing signal S _mjx has a rising edge. In Figure 5, the TDC stops the measurement window at the next rising edge of the mixing signal S _mjx after detecting the rising edge of the reference clock signal S _R . In Figure 6, the TDC 50 stops the measurement window at a rising edge of the mixing signal S _mix several clock cycles after detecting the rising edge of the reference clock signal S _R . The measurement of the time difference over multiple LO clock cycles, such as shown in Figure 6, may be used to avoid metastability in the triggering logic without adding complexity to the solution or impacting the accuracy of the

measurement. In either case, the initial phase Αφ _ι (m) for the m' ^h output signal S _r m) may be calculated accordin

where n _TDC (m) represents the number of TDC quantization steps measured by the m ^th

TDC 50 between the start edge (e.g., the reference clock rising edge t _ed (S _R ) ) and the stop edge (e.g., the mixing signal rising edge t _ed (S _m!x ) ), and Astep represents TDC

quantization step size in seconds. It will be appreciated that the embodiments disclosed herein do not require the TDC 50 to use the rising edges of the mixing and reference clock signals; any signaling edge, e.g., a falling edge, may alternatively be used.

Figure 7A shows one exemplary circuit/logic implementation for the TDC 50, while Figure 7B shows one exemplary signaling diagram corresponding to the TDC 50 of Figure 7A. As noted herein, the arm signal is not required for all embodiments. The configuration of AND, XOR, and timing gates shown in Figure 7A perform the corresponding logic functions on the input signals (S _R , S _mlx , and optionally, the arm signal) to trigger the beginning and end of the measurement window, and thus to enable the measurement of the duration of the measurement window. Because each TDC 50 has the same input reference clock signal S _R , and the same arm signal (when used), the determination of the duration of the measurement window enables the initial phase to be simultaneously determined for each output signal.

The transmitter 100 uses the determined initial phase Αφ _ι (m) to facilitate accurate phase control of the corresponding antenna element 22. To that end, the transmitter 100 may also include a phase control circuit 60 for each RF front-end circuit 30, as shown in Figure 3. The phase control circuit 60 may receive the determined initial phase Αφ _ι [m) from the corresponding TDC 50. Alternatively, the phase control circuit 60 may receive the measured time difference At m) from the corresponding TDC 50, and then compute the initial phase Αφ _ι (m) from the received measured time difference. In any event, the phase control circuit 60 uses the initial phase Αφ _ι (m) to initialize or "calibrate" the phase of the corresponding m' ^h RF front-end circuit 30 so that the m' ^h RF front-end circuit 30 executes any phase control activities from a known initial phase. The phase control circuits 60 may then adjust, e.g., rotate, the initial phase determined for that output signal to achieve the desired phase value for that output signal. For example, the phase control circuit 60 may use the initial phase to adjust the input control signal used to control the phase of the PLL output signal. Alternatively, the phase control circuit 60 may use the initial phase to control/adjust the phase of the baseband signal S ₇ . Because the phase control circuit 60 effectively starts the phase adjustment from the known initial phase value, the resulting phase control is accurate and reliably achieves the desired performance, e.g., beamforming.

Figure 3 involves a transmitter with all of the RF front-end circuits 30 on a single integrated circuit. The solution presented herein, however, may also be used when different RF front-end circuits 30 are disposed on different integrated circuits, such as shown in Figure 8. In such cases, transmitter 100 will further include a synchronization circuit 70 for each integrated circuit. Each synchronization circuit 70 may be implemented, e.g., using a counter running with a clock common to all of the integrated circuits. The synchronization circuits 70 synchronize the timing measurements occurring on different integrated circuits. To synchronize the timing measurements, each synchronization circuit 70 provides an arm signal, such as shown in Figure 9, to the TDCs 50 on that integrated circuit. Further, the synchronization circuits 70 are also synchronized across the integrated circuits to makes sure that the arm signals provided to each TDC 50 in the transmitter 100 are synchronized. As shown in Figure 9, once the arm signal is activated, e.g., goes high, the TDC 50 triggers on an edge of the reference clock signal S _R , e.g., a rising edge, and measures how long after that rising edge the mixing signal S _mix has a rising edge to determine At[m) . The initial phase Αφ _ι (m) for the m ^th output signal S _out (m) may be calculated according to

Equation (1 ). While the above-described examples only use the synchronization circuit 70 and corresponding "arm" signals when different circuits of the transmitter 100 are disposed on different integrated circuits, the use of the synchronization circuit 70 is not so limited. It will be appreciated that the transmitter 100 may use synchronization circuit(s) 70 and the corresponding arm signal(s) for any transmitter configuration, including when all of the RF front-end circuits 30 are disposed on a single integrated circuit. As noted above, the solution presented herein also applies to beamforming receivers. In this case, the phase control circuit controls how the received signals are combined to achieve the desired beamforming benefits.

Figure 10 shows a block diagram of the m ^th antenna element 22, m ^th receiving RF front-end 30, and the corresponding m ^th TDC 50. In this case, the antenna element 22 provides a received signal to an amplifier 39, which generates an amplified input signal S ₇ for the mixer 36 of that RF front-end circuit 30. Like with the transmitter embodiment, a reference circuit 40 (Figure 1 1 ) generates a reference clock signal S _R common to the plurality of RF front-end circuits 30. Further, while not required, the reference clock signal S _R output by reference circuit 40 may also be used as the phase-locked loop reference signal provided to the phase-locked loop 32 in each RF front-end circuit 30.

Each TDC 50 is operatively connected to the reference clock circuit 40 to receive the common reference clock signal S _R , and to the corresponding RF front-end circuit 30 to receive the mixing signal S _mix generated by that RF front-end circuit 30. Each TDC 50 measures a time difference related to the current phase of the corresponding mixing signal S _mix , and determines the initial phase for the output of the corresponding RF front-end circuit 30 based on the measured time difference. For reception beamforming, this involves the TDC 50 measuring the time difference At (m) for the m ^th RF front-end circuit 30 by measuring a difference between a start edge t _ed (S _R ) of the reference clock signal S _R and a stop edge t _ed (S _m!x (m)) of the mixing signal S _mlx for the m ^th RF front-end circuit 30. The transmitter 100 determines the initial phase of the output signal, in this case reception output signal S _out (m) output by each RF front-end circuit 30, as a function of the corresponding measured time difference.

Figure 1 1 shows another block diagram of a beamforming receiver that includes synchronization circuit 70. Synchronization circuit 70 provides an arm signal to the corresponding TDCs 50. Further, if there are multiple synchronization circuits 70, each of the synchronization circuits are also synchronized across the integrated circuits to makes sure that the arm signals provided to each TDC 50 in the transmitter 100 are synchronized. Once the arm signal is activated, e.g., goes high, the TDC 50 triggers on an edge of the reference clock signal S _R , e.g., a rising edge, and measures how long after that rising edge the mixing signal S _mix has a rising edge to determine ht (rn) . The initial phase Α _ι (m) for the m ^th output signal S _T (m) may be calculated according to Equation (1 ). The solution presented herein provides an efficient and cost-effective way to determine the initial phase for scenarios where the phase caused by RF circuit components, e.g., a frequency divider, changes periodically, e.g., each time the circuit is powered on. By simultaneously determining the initial phase of the output signal of multiple RF circuits, the solution presented herein enables accurate phase control.

The present invention may, of course, be carried out in other ways than those specifically set forth herein without departing from essential characteristics of the invention. The present embodiments are to be considered in all respects as illustrative and not restrictive, and all changes coming within the meaning and equivalency range of the appended claims are intended to be embraced therein.