LOG-LIKELIHOOD RATIO (LLR) COMPUTATION

USING PIECEWISE LINE AR APPROXIMATION

OF LLR FUNCTIONS

[0001] The present application claims priority to provisional U.S. Application Serial No. 60/782,378, entitled "ESTIMATION FOR SIGNAL CONSTELLATION AND NOISE VARIANCE FOR 16QAM," filed March 14, 2006, assigned to the assignee hereof and incorporated herein by reference.

BACKGROUND

I. Field

[0002] The present disclosure relates generally to communication, and more specifically to techniques for computing log-likelihood ratio (LLRs) for code bits.

II. Background

[0003] In a communication system, a transmitter typically encodes traffic data based on a coding scheme to obtain code bits and further maps the code bits to modulation symbols based on a modulation scheme. The transmitter then processes the modulation symbols to generate a modulated signal and transmits this signal via a communication channel. The communication channel distorts the transmitted signal with a channel response and further degrades the signal with noise and interference. [0004] A receiver receives the transmitted signal and processes the received signal to obtain received symbols, which may be distorted and noisy versions of the modulation symbols sent by the transmitter. The receiver may then compute LLRs for the code bits based on the received symbols. The LLRs are indicative of the confidence in zero (O') or one (T) being sent for each code bit. For a given code bit, a positive LLR value may indicate more confidence in '0' being sent for the code bit, a negative LLR value may indicate more confidence in ' 1 ' being sent for the code bit, and an LLR value of zero may indicate equal likelihood of '0' or ' 1 ' being sent for the code bit. The receiver may then decode the LLRs to obtain decoded data, which is an estimate of the traffic data sent by the transmitter.

[0005] The computation for the LLRs may be complex. However, accurate LLRs may result in good decoding performance. There is therefore a need in the art for techniques to efficiently and accurately compute LLRs for code bits.

SUMMARY

[0006] Techniques for efficiently and accurately computing LLRs for code bits are described herein. A set of code bits may be mapped to a modulation symbol in a signal constellation for quadrature phase shift keying (QPSK), quadrature amplitude modulation (QAM), etc. Different code bits in the set may be associated with different LLR functions. The LLRs for the code bits may be derived based on piecewise linear approximation of the LLR functions.

[0007] In one design, a receiver obtains received symbols for a transmission sent via a communication channel. The transmission may comprise modulation symbols from a QPSK or QAM signal constellation. The receiver derives LLRs for code bits based on the received symbols and piecewise linear approximation of at least one LLR function. The received symbols may be complex values having real and imaginary components. The receiver may derive LLRs independently for the real and imaginary components of each received symbol, if permitted by the signal constellation for the modulation symbols.

[0008] The at least one LLR function may comprise a first LLR function for first code bits, e.g., sign bits that determine the sign of the real and imaginary components of the modulation symbols. The piecewise linear approximation of the first LLR function may comprise three linear functions for three ranges of input values. The receiver may select one of the three linear functions for each first code bit based on a corresponding received symbol component value. The receiver may then derive an LLR for each first code bit based on the linear function selected for that first code bit. [0009] The at least one LLR function may comprise a second LLR function for second code bits, e.g., magnitude bits that determine the magnitude of the real and imaginary components of the modulation symbols. The piecewise linear approximation of the second LLR function may comprise two linear functions for two ranges of input values. The receiver may select one of the two linear functions for each second code bit based on a corresponding received symbol component value. The receiver may then

derive an LLR for each second code bit based on the linear function selected for that second code bit.

[0010] The receiver may decode the LLRs for the code bits to obtain decoded data for the transmission sent via the communication channel. The receiver may perform

Turbo decoding on the LLRs if Turbo encoding was used for the transmission and may perform Viterbi decoding on the LLRs if convolutional encoding was used for the transmission.

[0011] Various aspects and features of the disclosure are described in further detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] FIG. 1 shows a block diagram of a transmitter and a receiver.

[0013] FIG. 2 shows an encoder and a symbol mapper at the transmitter.

[0014] FIG. 3 shows an example signal constellation for 16-QAM.

[0015] FIG. 4 shows a plot of a decision threshold for an LLR function.

[0016] FIGS. 5A and 5B show piecewise linear approximation of two LLR functions for two code bits.

[0017] FIG. 6 shows an LLR computation unit at the receiver.

[0018] FIGS 7A, 7B and 7C show plots of parameters used for approximation of

LLR functions.

[0019] FIG. 8 shows a decoder at the receiver.

[0020] FIG. 9 shows a process for computing LLRs for code bits.

DETAILED DESCRIPTION

[0021] FIG. 1 shows a block diagram of a design of a transmitter 100 and a receiver 150 in a communication system. At transmitter 100, an encoder 120 receives a block of data from a data source 112, encodes the data block based on a coding scheme, and provides code bits. A data block may also be referred to as a transport block, a packet, a frame, etc. Encoder 120 may perform rate matching and delete or repeat some or all of the code bits to obtain a desired number of code bits for the data block. Encoder 120 may also perform channel interleaving and reorder the code bits based on an interleaving scheme. A symbol mapper 130 maps the code bits to modulation symbols

based on a modulation scheme, which may be QPSK, QAM, etc. A modulator (MOD) 132 may perform processing for coding division multiplexing (CDM) and spread the modulation symbols with orthogonal codes. Modulator 132 may also perform processing for frequency division multiplexing (FDM), orthogonal frequency division multiplexing (OFDM), single-carrier FDM (SC-FDM), etc. Modulator 132 then processes (e.g., converts to analog, amplifies, filters, and frequency upconverts) the resultant output symbols and generates a modulated signal, which is transmitted via an antenna 134.

[0022] At receiver 150, an antenna 152 receives the modulated signal from transmitter 100 and provides a received signal. A demodulator (DEMOD) 154 processes (e.g., filters, amplifies, frequency downconverts, and digitizes) the received signal to obtain samples. Demodulator 154 may further process the samples (e.g., for CDM, FDM, OFDM, SC-FDM, etc.) to obtain received symbols. A signal and noise estimator 162 may estimate signal and noise characteristics and/or the wireless channel response based on the received symbols. An LLR computation unit 160 computes LLRs for code bits based on the received symbols and the signal, noise and/or channel estimates. A decoder 170 decodes the LLRs in a manner complementary to the encoding performed by transmitter 100 and provides decoded data. In general, the processing by demodulator 154, LLR computation unit 160, and decoder 170 at receiver 150 is complementary to the processing by modulator 132, symbol mapper 130, and encoder 120 at transmitter 100.

[0023] Controllers/processors 140 and 180 direct the operation of various processing units at transmitter 100 and receiver 150, respectively. Memories 142 and 182 store data and program codes for transmitter 100 and receiver 150, respectively. [0024] In general, encoder 120 may implement any coding scheme, which may include a Turbo code, a convolutional code, a low density parity check (LDPC) code, a cyclic redundancy check (CRC) code, a block code, etc., or a combination thereof. Encoder 120 may generate and append a CRC value to a data block, which may be used by receiver 150 to determine whether the data block was decoded correctly or in error. Turbo code, convolutional code, and LDPC code are different forward error correction (FEC) codes that allow receiver 150 to correct errors caused by impairments in the wireless channel.

[0025] FIG. 2 shows a block diagram of a design of encoder 120 and symbol mapper 130 at transmitter 100 in FIG. 1. In this design, encoder 120 implements a Turbo code, which is also referred to as a parallel concatenated convolutional code. Within encoder 120, a code interleaver 222 receives a block of data bits (denoted as {d}) and interleaves the data bits in accordance with a code interleaving scheme. A first constituent encoder 220a encodes the data bits based on a first constituent code and provides first parity bits (denoted as {z}). A second constituent encoder 220b encodes the interleaved data bits from code interleaver 222 based on a second constituent code and provides second parity bits (denoted as {z'}). Constituent encoders 220a and 220b may implement two generator polynomials, e.g., g _o (D) = l + D ² + D ³ and g^D) = \ + D + D ³ used in Wideband Code Division Multiple Access (W-CDMA). A multiplexer (Mux) 224 receives the data bits and the parity bits from constituent encoders 220a and 220b, multiplexes the data and parity bits, and provides code bits. Multiplexer 224 may cycle through its three inputs and provide one bit at a time to its output, or ...}. A rate matching unit 226 receives the code bits from multiplexer 224 and may delete some of the code bits and/or repeat some or all of the code bits to obtain a desired number of code bits for the data block. Although not shown in FIG. 2, encoder 120 may also perform channel interleaving on the code bits from rate matching unit 226.

[0026] Within symbol mapper 130, a demultiplexer (Demux) 230 receives the code bits from encoder 120 and demultiplexes the code bits into an inphase (I) stream {/} and a quadrature (Q) stream {q}. Demultiplexer 230 may provide the first code bit to the I stream, then the next code bit to the Q stream, then the next code bit to the I stream, etc. A QAM/QPSK look-up table 232 receives the I and Q streams, forms sets of B bits, and maps each set of B bits to a modulation symbol based on a selected modulation scheme, where B = 2 for QPSK, B = 4 for 16-QAM, etc. Symbol mapper 130 provides modulation symbols {x} for the data block.

[0027] FIG. 3 shows an example signal constellation for 16-QAM, which is used in W-CDMA. This signal constellation includes 16 signal points corresponding to 16 possible modulation symbols for 16-QAM. Each modulation symbol is a complex value of the form X ₁ + j x _q , where X ₁ is the real component and x _q is the imaginary component. The real component X ₁ may have a value of -3 a, -a, a or 3 a, and the

imaginary component x _q may also have a value of -3 a, -a, a or 3 a, where a is defined below.

[0028] For 16-QAM, the code bits in the I and Q streams from demultiplexer 230 may be grouped into sets of four bits, with each set being denoted as qi i ₂ qi), where bits i _\ and i ₂ are from the I stream and bits q _\ and q ₂ are from the Q stream. The 16 modulation symbols in the signal constellation are associated with 16 possible 4-bit values for {i\ qj i ₂ q ₂ }. FIG. 3 shows an example mapping of each possible 4-bit value to a specific modulation symbol. In this mapping, the real component X ₁ of a modulation symbol is determined by the two inphase bits Z ₁ and z ₂ , and the imaginary component x _q is determined by the two quadrature bits q\ and q ₂ . In particular, bit Z ₁ determines the sign of the real component X ₁ , with X ₁ > 0 for Z ₁ = 0 , and X ₁ < 0 for

Z ₁ = 1 . Bit z ₂ determines the magnitude of the real component X ₁ , with | X ₁ \ = a for Z ₂ = 0 , and \ x _t \ = 3a for Z ₂ = 1 . Bit Z ₁ may thus be considered as a sign bit for X ₁ , and bit z ₂ may be considered as a magnitude bit for X ₁ . Similarly, bit q _\ determines the sign of the imaginary component x _q , and bit q ₂ determines the magnitude of the imaginary component x _q . The mapping is independent for the real and imaginary components. For each component, 2-bit values of '11 ', ' 10', '00' and '01 ' are mapped to -3a, -a, a, and 3a, respectively, based on pulse amplitude modulation (PAM). Two 4-PAM modulation symbols may thus be generated separately based on (Z ₁ z ₂ ) and (qi q ₂ ) and then quadrature combined to obtain a 16-QAM modulation symbol. [0029] At receiver 150, the received symbols from demodulator 154 may be expressed as:

y = x + n , Eq (1)

where x is a modulation symbol sent by transmitter 100, n is the noise observed by modulation symbol x, and y is a received symbol obtained by receiver 150.

[0030] Received symbol y has (i) a real component y ₁ corresponding to the real component X ₁ of modulation symbol x and (ii) an imaginary component^ corresponding to the imaginary component x _q of modulation symbol x. Equation (1) assumes that receiver 150 performs appropriate scaling to account for amplification of modulation

symbol x, channel attenuation, and receiver processing. The modulation symbols sent by transmitter 100 may be assumed to be taken from the 16-QAM signal constellation with equal likelihood. For the 16-QAM signal constellation shown in FIG. 3, the average energy per received symbol component may be 5 a ² . For a normalized 16- QAM signal constellation with unit energy per component, a = 1 / V5 = 0.4472. [0031] For simplicity, the noise n may be assumed to be complex additive white Gaussian noise (AWGN) with independent and identically distributed (i.i.d.) real and imaginary components. Each noise component may be a Gaussian random variable with zero mean and variance of σ ² . The variance of the complex noise n may thus be N ₀ = 2σ ² . The signal-to-noise ratio (SNR) per component at receiver 150 is 5a ² 1 σ ² .

[0032] The real component X ₁ and the imaginary component x _q may be determined independently based on bits (Z ₁ z ^' ₂ ) and bits (qι q-i), respectively, as described above. The real and imaginary components of the noise n may be i.i.d. Hence, 16-QAM modulation symbol x may be considered as being composed of two independent 4-PAM modulation symbols X ₁ and x _q that may be demodulated separately. For clarity, the processing for only the real component X ₁ determined by bits Z ₁ and z ₂ is described below.

[0033] The LLRs for bits Z ₁ and z ₂ may be derived as follows. From Bayes formula, the following expression may be obtained:

n.,.|, _> | , _Eq(2)

where P(J ₁ = 0 \ y ₁ ) is an a posteriori probability that '0' was sent as bit Z ₁ given that y ₁ was received, P(y _t I Z ₁ = 0) is the probability of receiving y ₁ given that '0' was sent as bit Z ₁ ,

P(J ₁ = 0) is the a priori probability that '0' was sent as bit Z ₁ , and P(y _t ) is the probability of receiving y,.

[0034] Probability P(Z ₁ = 0 \ y ₁ ) may be conditioned on bit z ₂ as follows:

_{P(iι = 0 ] yi) =} ^p (y. ^ =θϋ)-P ⁽ h =0)+P ⁽ y, \iA = ^Q P-*β =0 , _P( ,. _{= 0)}

[0035] An a posteriori probability P(i _γ = \ \ y ₁ ) may be defined in similar manner as the a posteriori probability P(i _γ = 0 | y _t ) in equations (2) and (3).

[0036] A likelihood ratio (LR) for bit Z ₁ , LR(O , may be defined as follows:

\ - P(J ₁ = O I y ₁ ) _ P(y, I i ₁ J ₂ = 00) + PJy ₁ I i ₁ J ₂ = Ol)

LR(I ) = Eq (4)

P(Z ₁ = 1 1 y,) P(y, | Z ₁ i ₂ = 10) + P(y, | Z ₁ i ₂ = 11)

LR(i _} ) is the ratio of the a posteriori probability that '0' was sent as bit i _\ to the a posteriori probability that '1 ' was sent as bit i _\ . Equation (4) assumes that all 16 points in the 16-QAM signal constellation are equally likely to be transmitted. [0037] Using equation (4) and assuming that the noise distribution is AWGN, the likelihood ratio for bit i _\ may be expressed as:

LR(O =

-(y,+a) ² Eq (5)

+ e

The four exponential terms in equation (5) correspond to four Gaussian distributions at -3a, -a, a and 3a on the real axis for four possible 2-bit values for bits and h. [0038] An LLR for bit i\, LLR(O , ^ma Y be obtained from equation (5), as follows:

LLR(O is ^an increasing function of y _t and is equal to zero for y _ι = 0 . [0039] LLR(O ^ma Y be a positive value, zero, or a negative value. An LLR(O value of zero indicates equal confidence in '0' or '1 ' being sent for bit A positive LLR(O value indicates greater confidence in '0' being sent for bit i\. A negative LLR(O ^va l ^ue indicates greater confidence in ' 1 ' being sent for bit The sign of LLR(O thus represents whether there is more confidence in '0' or ' 1 ' being sent for bit

Z ₁ . The magnitude of LLR(i _λ ) represents the degree of confidence, with a larger magnitude corresponding to greater confidence.

[0040] In general, an LLR function may have one or more decision thresholds. A decision threshold is an input value that results in a LLR value of 0. The LLR function in equation (6) has a single decision threshold of 0, which means that LLR(I ₁ ) = 0 when y _{l =} 0 .

[0041] An LR for bit i ₂ , LR(i ₂ ) , may be defined as follows:

² P P((iI, ₂ == 1I 1I y y ₁ , )) PP((yy _t , 1 \ 1i,j i, ₂ == 0011)) ++ PP((yv _t , 1 I 1Z, ₁ iI, ₂ == 1111)) - ^Q -. - ³ * ⁾² - ⁽ ^ ^+3α)

2σ ^ι + e

[0042] An LLR for bit z ₂ , LLR(i ₂ ) , may be obtained from equation (7) as follows:

[0043] The LLR function in equation (8) has two decision thresholds that are close to 2a and -2a when the ratio a ² 1 σ ² is reasonably high. Thus, LLR(i ₂ ) = 0 when j _z is close to 2a or -2a for high a ² 1 σ ² .

[0044] An LLR for bit q _\ , LLR(q _λ ) , may be derived based on y _q in an analogous manner as LLR(i _λ ) using equation (6). Similarly, an LLR for bit q ₂ , LLR(q ₂ ) , may be derived based on y _q in an analogous manner as LLR(i ₂ ) using equation (8).

[0045] Equations (6) and (8) represent LLR functions for bits i _\ and i ₂ , respectively, for the 16-QAM signal constellation shown in FIG. 3 and with the assumptions described above. The LLR functions in equations (6) and (8) contain cosh functions and other arithmetic operations and may thus be computationally intensive.

[0046] In an aspect, the LLRs for code bits may be derived based on piecewise linear approximation of LLR functions. This may greatly reduce computation while still provide relatively accurate LLRs, so that degradation in decoding performance is negligible. The piecewise linear approximation may be obtained in several manners.

[0047] In equation (5), the four distributions have means that are spaced apart by 2a and variances of σ ² . When ratio a ² 1 σ ² is reasonably high, i.e., for high received SNR, the bulk of each distribution is relatively narrow with respect to the spacing between the distribution means. In this case, for the numerator of equation (5), the term

-{y _τ -a) -(y _s -3a) e ^2ry2 dominates when y _l is close to a, and the term e ^2ry2 dominates when y _l is close to 3a.

[0048] In a first design, which is referred to as Type 1, piecewise linear approximation of an LLR function is obtained by considering the maximum distribution in each of the numerator and denominator of the LLR function. For equation (5), the maximum of the two distributions in the numerator may be considered instead of their sum. Similarly, the maximum of the two distributions in the denominator may be considered instead of their sum. The LLR for bit Z ₁ may then be approximated as follows:

Max P(y _t \ i _{l =} OJ ₂ )

LLR(I ₁ ) « In ^^ Eq (9)

Max P(y _t I z ₁ = l,z ₂ ) z ₂ =0,1

-(y, -a) e ^2rj2 if y _t < 2a where Max P(y _t | Z ₁ = OJ ₂ ) = z, =0,1 -(y, -ϊa) ² e ^2σ2 if y _t ≥ 2a

[0049] Piecewise linear approximation of the LLR function for bit i _\ may then be expressed as:

LLR(I ₁ ) = < 2a Eq (IO)

.

[0050] As shown in equation (10), the LLR function for bit Z ₁ may be approximated with three straight lines. The first straight line is defined by a linear function (4a y _t + 4a ² ) I σ ² and covers y _t values less than -2a. The second straight line is defined by a linear function 2a yj σ ² and covers y _t values from -2a to 2a. The third straight line is defined by a linear function (4a y _t - 4a ² )lσ ² and covers y _r values of 2a and larger.

[0051] The LLR for bit Z ₂ may be approximated as follows:

-(y, +a) e ^2σl if y _t < 0 where Max P(y _t | i ₂ = OJ ₁ ) =

:, =0,1 -(y, -a) ²

„ 2σ ² if y _t ≥ 0

-(y, +3a) ² e ^2σ2 if y, < 0

Max P( V ₁ h =0,1 I ₂ = U ₁ ) = -(y, -3a) ² e ^2σl if v, > 0

[0052] Piecewise linear approximation of the LLR function for bit i ₂ may then be expressed as:

LLR(J ₂ ) = - ^2a \ ψ ^Aa2 Eq (12)

[0053] As shown in equation (12), the LLR function for bit h may be approximated with two straight lines. The first straight line is defined by a linear function (2a y _l + 4a ² )l σ ² and covers y _t values less than zero. The second straight line is defined by a linear function (-2a y _t + 4a ² )/σ ² and covers y _r values of zero and greater.

[0054] In a second design, which is referred to as Type 2, linear approximation of an LLR function may be defined around each decision threshold for the LLR function. The LLR function may have one or more decision thresholds. A linear function may be

defined for each decision threshold and used to determine the LLR over a range of input values covering that decision threshold.

[0055] The LLR function for bit Z ₁ in equation (6) has a single decision threshold for y _t = 0 . The slope of this LLR function at the decision threshold may be determined by differentiating the LLR function with respect to j _z at y _t = 0 , as follows:

where S ₁ is the slope of the LLR function for bit Z ₁ at y _ι = 0 .

[0056] For high a ² / σ ² , the slope in equation (13) may be approximated as 2a/ σ ² . Linear approximation of the LLR function for bit Z ₁ may then be expressed as:

LLR(I ₁ ) = ^^ . Eq (14) σ

[0057] As shown in equation (14), the LLR function for bit Z ₁ may be approximated with a single straight line having a slope of 2a I σ ² and a value of zero at the decision threshold of y _t = 0 .

[0058] The LLR function for bit z ₂ in equation (8) has two decision thresholds for y _t close to -2a and 2a. The slope of this LLR function at 2a may be expressed as:

Aa ¹ 12a ²

where S ₂ is the slope of the LLR function for bit h at y _t = 2a .

[0059] For high a ² 1 σ ² , the slope in equation (15) may be approximated as - 2a I σ ² for the decision threshold of 2a. Linear approximation of the LLR function for bit Z ₂ may then be expressed as:

_{τ τ τt} ,. , - 2a \ y _t \ +4a ²

LLR(i ₂ ) = — . Eq (16)

[0060] As shown in equation (16), the LLR function for bit z ₂ may be approximated with (i) a first straight line having a slope of - 2a/σ ² and a value of zero at the decision threshold of y _t = 2a and (ii) a second straight line having a slope of 2a I σ ² and a value of zero at the decision threshold of y _t = -2a .

[0061] As shown in equations (10) and (14), Type 1 approximation of the LLR function for bit Z ₁ matches Type 2 approximation of the LLR function for bit Z ₁ for y _t values in the range of -2a to 2a. For y _t values smaller than -2a or larger than 2a, the absolute value of the LLR for bit Z ₁ is smaller for Type 2 than Type 1. Hence, for a sufficiently large absolute y _t value (e.g., more than 2a), the LLR from Type 2 may reflect less confidence in a decision for bit Z ₁ than the LLR from Type 1. Type 1 approximation of the LLR for bit z ₂ in equation (12) matches Type 2 approximation of the LLR for bit z ₂ in equation (16) for all j _z values.

[0062] The LLR function for bit Z ₁ has a single decision threshold at 0. The LLR function for bit z ₂ has two decision thresholds near -2a and 2a. A decision threshold represents a point at which there is maximum uncertainty on the likelihood of a given bit having been sent as '0' or ' 1 '. Thus, it is desirable to have good approximation of LLRs around each decision threshold. [0063] The LLR value for bit z ₂ at a decision threshold may be expressed as:

a θ cosh

ZZR(I ₂ ) = -^- + In = 0 , Eq (17) σ 3a θ cosh

where θ is the decision threshold for the LLR function for bit z ₂ . LLR(I ₁ ) = 0 when

[0064] From equation (17), the decision threshold may be expressed as:

[0065] FIG. 4 shows a plot 410 of a normalized decision threshold for the LLR function for bit z ₂ . The horizontal axis represents a ² 1 σ ² in units of decibel (dB). The

vertical axis represents the normalized decision threshold, which is θla . Plot 410 indicates that the decision threshold θ is greater than 2a at low SNR and converges to 2a as SNR increases. [0066] The slope of the LLR function for bit z ₂ in equation (8) may be expressed as:

where S ₂ is the slope of the LLR function for bit z ₂ at the decision threshold θ. The slope S ₂ and/or the decision threshold θ may each be determined using hardware, software, look-up table, etc.

[0067] Linear approximation of the LLR for bit z ₂ may then be expressed as:

LLR(i ₂ ) = S ₂ - ( \ _yi \ - θ) . Eq (20)

For high SNR, S ₂ ~ -2a /σ ² and θ « 2α .

[0068] Equations (18) to (20) may be used to derive a more accurate LLR for bit z ₂ across a wide range of SNRs. Equation (18) provides the decision threshold θ as a function of a ² /σ ² . Equation (19) provides the slope S ₂ as a function of a ² 1 σ ² . The decision threshold θ and the slope S ₂ may be determined for a given received SNR and used in equation (20) to derive the LLR for bit z ₂ .

[0069] The slope of the LLR function for bit Z ₁ , Si, may also be expressed as a function of a ² 1 σ ² , as shown in equation (13). The slope Si may be determined for a given received SNR and used in equation (10) or (14) to derive the LLR for bit Z ₁ . [0070] FIG. 5A shows plots of the actual LLR function for bit Z ₁ and piecewise linear approximation of this LLR function with a ² 1 σ ² = 1 or 0 dB. The horizontal axis represents y _r value, with a = 0.4472. The four one-dimensional PAM constellation points at -3a, -a, a and 3a are labeled on the horizontal axis. The vertical axis represents the LLR for bit Z ₁ , or LLR(i _λ ) . A plot 510 shows the LLR for bit Z ₁ with the exact computation shown in equation (6). A plot 512 shows the LLR for bit Z ₁ with the piecewise linear approximation shown in equation (10). These plots indicate that the

piecewise linear approximation is accurate with respect to the actual LLR values, especially around the decision threshold of y _t = 0 where the LLR value is close to 0, which is important for good decoding performance.

[0071] FIG. 5B shows plots of the actual LLR function for bit z ₂ and piecewise linear approximation of this LLR function with a ² I σ ² = 1 . A plot 520 shows the LLR for bit Z ₂ with the exact computation shown in equation (8). A plot 522 shows the LLR for bit h with the piecewise linear approximation shown in equation (12). These plots indicate that the piecewise linear approximation is accurate with respect to the actual LLR values, especially around the decision thresholds near -2a and 2a where the LLR value is close to 0.

[0072] FIGS. 5A and 5B show plots of the LLRs for bits h and Z ₂ with a ² 1 σ ² = 1 , which corresponds to a received SNR per component of approximately 7 dB. The approximations of the LLR functions for bits Z ₁ and Z ₂ are generally more accurate for progressively higher SNRs. 16-QAM may be used at higher SNRs whereas QPSK may be used at lower SNRs. These approximations may thus provide accurate LLRs for high SNR scenarios where 16-QAM is more likely to be used.

[0073] FIG. 6 shows a block diagram of a design of LLR computation unit 160 at receiver 150 in FIG. 1. In this design, unit 160 includes a demultiplexer 610, a scale and threshold computation unit 612, and LLR computation units 620a and 620b for the real and imaginary components, respectively. Demultiplexer 610 obtains received symbols {y} from demodulator 154, provides the real component y _t of each received symbol to LLR computation unit 620a, and provides the imaginary component y _q of each received symbol to LLR computation unit 620b. Each LLR computation unit 620 computes the LLRs for its code bits based on the piecewise linear approximations shown in equations (10) and (12). To simplify the LLR computation, two quantities u and v may be defined as follows:

u = _j - ¹ - and v = — _j - . Eq (21) σ σ

[0074] Equation (10) may be expressed in terms of u and v as follows:

2u + v if u < -v

LLR(I ₁ ) = u if - v < u < v . Eq (22)

2M - v if u ≥ v

[0075] Equation (12) may be expressed in terms of u and v as follows:

LLR(i ₂ ) = v - \ u \ . Eq (23)

[0076] Signal and noise estimator 162 may estimate signal and noise characteristics based on the received symbols as described below and provide the signal amplitude a and the noise variance σ ² . Computation unit 612 may compute a scale factor 2a I σ ² and a scaled threshold v = 4a ² 1 σ ² based on a and σ ² from signal and noise estimator 162 and may provide the scale factor and the scaled threshold to both LLR computation units 620a and 620b. Within unit 620a, a scaling unit 622 scales the real component j _z with the scale factor 2a/ σ ² and provides a scaled component u = 2a yj σ ¹ . A unit

624 computes the quantity 2u + v for the top part of equation (22). A unit 626 receives and provides u for the middle part of equation (22). A unit 628 computes the quantity 2u - v for the bottom part of equation (22). Units 624, 626 and 628 implement three linear functions for the piecewise linear approximation of the LLR function shown in equation (6). A multiplexer 630 receives three values from units 624, 626 and 628 at three inputs and provides one of the three values as the LLR for bit Z ₁ . A Mux selector 632 receives u and v and generates a control for multiplexer 630. This control selects 2u + v from unit 624 if u < -v , selects u from unit 626 if - v < u < v , and selects 2u - v from unit 628 if u > v . A unit 634 computes v- | u \ for equation (23) and provides this quantity as the LLR for bit z ₂ . Unit 634 may also compute the LLR for bit Z ₂ based on equations (18) to (20).

[0077] LLR computation unit 620b may compute the LLRs for bits q\ and qi based on the imaginary component y _q . The computation of the LLRs for bits q _\ and qi may be analogous to the computation of the LLRs for bits Z ₁ and z ₂ by unit 620a. [0078] Signal and noise estimator 162 may estimate the mean of the absolute value of the received symbol components, as follows:

1 m

~- i∑ = l < ! * ⁽ *> ! ⁺ yλk) \ } Eq (24)

where }>,(&) and y (k) are the real and imaginary components of the k-th received symbol, m is the mean of the absolute value of the received symbol components, and K is the number of received symbols used to estimate the mean.

[0079] Signal and noise estimator 162 may also estimate the average energy of the received symbol components, as follows:

^E = ~ ∑ i \ y^) \ + \ y _q ² (k) \ } , Eq (25) k = \

where E is the average energy of the received symbol components.

[0080] Signal and noise estimator 162 may map m and E to a and σ ² based on one or more mappings, which may be determined based on analytical calculation, computer simulation, empirical measurement, etc. In one design, ratio m ² I E is mapped to ratio aim based on a first analytical function, and ratio m ² 1 E is mapped to ratio σ ² Im ² based on a second analytical function. The mappings may be performed with hardware, software, look-up tables, etc. a and σ ² may then be determined from aim and σ ² Im ² , respectively, since m is known.

[0081] FIG. 7A shows a plot 710 of aim versus m ² IE . Plot 710 shows aim converging to 0.5 for high SNR since m approaches 2a.

[0082] FIG. 7B shows a plot 712 of σ ² Im ² versus m ² IE . Plot 712 shows σ ² Im ² decreasing toward 0.0 for high SNR.

[0083] FIG. 7C shows a plot 714 of θlm versus m ² 1 E . Plot 714 shows θlm being close to 1.0 for a wide range of SNR. This suggests that fine representation of the scaled threshold v may be obtained even for low SNR by implementing the θlm function with few bins in a look-up table, e.g., in signal and noise estimator 162.

[0084] FIG. 8 shows a block diagram of a design of decoder 170 at receiver 150 in

FIG. 1. In this design, decoder 170 implements a Turbo decoder that may be used for the Turbo encoder shown in FIG. 2. Within decoder 170, a demultiplexer 810 receives the LLRs for bits Z ₁ , z ₂ , q\ and qi from LLR computation unit 160, provides the LLRs for the data bits, LLR(J), to maximum a posteriori (MAP) decoders 820a and 820b,

provides the LLRs for the parity bits from first constituent encoder 220a, LLR {z}, to MAP decoder 820a, and provides the LLRs for the parity bits from second constituent encoder 220b, LLR{z'}, to MAP decoder 820b.

[0085] MAP decoder 820a receives the data bit LLRs, LLR(J), and the first parity bit LLRs, LLR {z}, from demultiplexer 810 and deinterleaved data bit LLRs from a code deinterleaver 824. MAP decoder 820a derives new LLRs for the data and first parity bits based on the first constituent code used by encoder 220a. A code interleaver 822 interleaves the data bit LLRs from decoder 820a in accordance with the code interleaving scheme used at encoder 120 and provides interleaved data bit LLRs. MAP decoder 820b receives the data bit LLRs, LLR {z}, and the second parity bit LLRs, LLR{z'}, from demultiplexer 810 and the interleaved data bit LLRs from code interleaver 822. MAP decoder 820b then derives new LLRs for the data and second parity bits based on the second constituent code used by encoder 220b. Code deinterleaver 824 deinterleaves the data bit LLRs from decoder 820b and provides the deinterleaved data bit LLRs. MAP decoders 820a and 820b may implement a BCJR MAP algorithm or a lower complexity derivative, a soft-output Viterbi (SOV) algorithm, or some other decoding algorithm known in the art.

[0086] MAP decoders 820a and 820b may perform multiple decoding iterations. After all decoding iterations are completed, a detector 830 may combine the data bit LLRs from MAP decoder 820a and code deinterleaver 824 to obtain final data bit LLRs. Detector 830 may then slice the final data bit LLRs to obtain hard decisions for the data bits and provide decoded data.

[0087] The LLRs derived as described herein may also be used for other types of decoders such as Viterbi decoders commonly used with convolutional encoders. [0088] FIG. 9 shows a design of a process 900 for computing LLRs for code bits. Received symbols may be obtained for a transmission sent via a communication channel (block 912). The transmission may comprise modulation symbols from a QPSK or M- QAM signal constellation, where M may be 16 or higher. For example, the modulation symbols may be from the 16-QAM signal constellation shown in FIG. 3. [0089] LLRs for code bits may be derived based on the received symbols and piecewise linear approximation of at least one LLR function (block 914). The received symbols may be complex values having real and imaginary components. The LLRs may be computed independently for the real and imaginary components of the received

symbols, if permitted by the signal constellation for the modulation symbols, as described above.

[0090] The at least one LLR function may comprise a first LLR function for first code bits, e.g., sign bits that determine the sign of the real and imaginary components of the modulation symbols. The piecewise linear approximation of the first LLR function may comprise three linear functions for three ranges of input values, e.g., y _r oxy _q values. These three linear functions may have odd symmetry about an input value of zero, e.g., y _t = 0 as shown in FIG. 5 A. One of the three linear functions may be selected for each first code bit based on a corresponding received symbol component value, e.g., y _t or y _q value. An LLR for each first code bit may then be derived based on the linear function selected for that first code bit, e.g., as shown in equation (22) and FIG. 6. The slope of one or more linear functions may be determined based on signal and noise estimates, which may correspond to a and σ ² .

[0091] The at least one LLR function may comprise a second LLR function for second code bits, e.g., magnitude bits that determine the magnitude of the real and imaginary components of the modulation symbols. The piecewise linear approximation of the second LLR function may comprise two linear functions for two ranges of input values. These two linear functions may have even symmetry about an input value of zero, e.g., y _t = 0 as shown in FIG. 5B. One of the two linear functions may be selected for each second code bit based on a corresponding received symbol component value, e.g., y _t or y _q value. An LLR for each second code bit may be derived based on the linear function selected for that second code bit, e.g., as shown in equation (23). The slope and intercept point each linear function may be determined based on signal and noise estimates. The intercept point may be related to and determined by the decision threshold for the second LLR function.

[0092] Parameters for the piecewise linear approximation of the at least one LLR function may be derived based on the received symbols. The parameters may comprise the signal amplitude a and the noise variance σ ² , which may be estimated as described above. The parameters may also comprise a scale factor 2a I σ ² for the received symbols and a scaled threshold v = 4a ² 1 σ ² . The parameters may also include other variables and/or quantities.

[0093] In general, the piecewise linear approximation of each LLR function may comprise one or more linear functions, e.g., at least two linear functions. The linear function(s) for each LLR function may be determined based on the mathematical expression for that LLR function.

[0094] The LLRs for the code bits may be decoded to obtain decoded data for the transmission sent via the communication channel (block 916). The decoding may be dependent on the encoding performed for the transmission. For example, Turbo decoding may be performed on the LLRs if Turbo encoding was used for the transmission, and Viterbi decoding may be performed on the LLRs if convolutional encoding was used for the transmission.

[0095] For clarity, the LLR computation techniques have been described for the 16- QAM signal constellation shown in FIG. 3. In general, the techniques may be used for various signal constellations such as QPSK, 4-PAM, 8-PSK, 16-QAM, 32-QAM, 64- QAM, 256-QAM, etc. The code bits of a modulation symbol may be associated with different LLR functions. For example, code bits Z ₁ and q _\ for a 16-QAM modulation symbol may be associated with a first LLR function, and code bits h and qi for the 16- QAM modulation symbol may be associated with a second LLR function. Piecewise linear approximation may be used for each LLR function. Each LLR function may be approximated with one or more linear functions. The number of linear functions to use for the piecewise linear approximation of a given LLR function may be dependent on the mathematical expression for that LLR function, which may be different for different LLR functions. The LLRs for different code bits of a modulation symbol may be computed based on the piecewise linear approximations of the LLR functions for these code bits.

[0096] The techniques described herein may be used for various wireless communication systems and networks such as Code Division Multiple Access (CDMA) systems, Time Division Multiple Access (TDMA) systems, Frequency Division Multiple Access (FDMA) systems, Orthogonal FDMA (OFDMA) systems, Single- Carrier FDMA (SC-FDMA) systems, wireless local area networks (WLANs), etc. The terms "systems" and "networks" are often used interchangeably. A CDMA system may implement a radio technology such as Universal Terrestrial Radio Access (UTRA), Evolved UTRA (E-UTRA), cdma2000, etc. UTRA includes W-CDMA and Time Division-Synchronous CDMA (TD-SCDMA). cdma2000 covers IS-2000, IS-95 and

IS-856 standards. A TDMA system may implement a radio technology such as Global System for Mobile Communications (GSM). An OFDMA system may implement a radio technology such as Long Term Evolution (LTE) (which is part of E-UTRA), IEEE 802.20, Flash-OFDM®, etc. A WLAN may implement a radio technology such as IEEE 802.11, Hiperlan, etc. These various radio technologies and standards are known in the art. The techniques may also be used for downlink and uplink transmissions and may be implemented at a base station and a terminal.

[0097] The techniques described herein may be implemented by various means. For example, these techniques may be implemented in hardware, firmware, software, or a combination thereof. For a hardware implementation, the processing units used to perform LLR computation may be implemented within one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processors, controllers, micro-controllers, microprocessors, electronic devices, other electronic units designed to perform the functions described herein, a computer, or a combination thereof.

[0098] For a firmware and/or software implementation, the techniques may be implemented with modules (e.g., procedures, functions, etc.) that perform the functions described herein. The firmware and/or software instructions may be stored in a memory (e.g., memory 182 in FIG. 1) and executed by a processor (e.g., processor 180). The memory may be implemented within the processor or external to the processor. The firmware and/or software instructions may also be stored in other processor-readable medium such as random access memory (RAM), read-only memory (ROM), nonvolatile random access memory (NVRAM), programmable read-only memory (PROM), electrically erasable PROM (EEPROM), FLASH memory, compact disc (CD), magnetic or optical data storage device, etc.

[0099] An apparatus implementing the techniques described herein may be a standalone unit or may be part of a device. The device may be (i) a stand-alone integrated circuit (IC), (ii) a set of one or more ICs that may include memory ICs for storing data and/or instructions, (iii) an ASIC such as a mobile station modem (MSM), (iv) a module that may be embedded within other devices, (v) a cellular phone, wireless device, handset, or mobile unit, (vi) etc.

[00100] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[00101] WHAT IS CLAIMED IS: