A log-linear pixel circuit is a pixel circuit which generates an output voltage signal which is a linear function of incident radiation intensity for levels of incident radiation intensity below a transition intensity, and an output voltage signal which is a logarithmic function of incident radiation intensity for levels of incident radiation intensity above the transition intensity.

Digital imaging systems comprising arrays of CMOS (complementary metal-oxide- semiconductor) pixel circuits are known. In the majority of such systems, a particular pixel circuit generates an output voltage signal by integrating a current generated by a photodetector over an integration period using an integration capacitor, as shown in US Patent 5 155 348 for example. For a given integration period, the output voltage signal from a such a pixel circuit varies substantially linearly with the photodetector's illumination level. One problem with an array of such pixel circuits is that it has a poor simultaneous dynamic range because pixels onto which regions of high intensity within a scene are imaged become saturated.

When a scene to be imaged contains some regions of high intensity and other regions of low intensity, an array of such pixel circuits produces a poor quality image because it is not possible to set a common integration time for all the pixel circuits which allows detail in both high and low intensity regions to be imaged: a long integration time causes saturation in pixel circuits imaging high intensity regions and a short integration time results in loss of resolution in regions of the image corresponding to regions of low intensity in the scene.

Another type of prior art CMOS pixel circuit, for example that disclosed in International Patent Application Number PCT/GB98/02877, produces an output voltage signal which varies logarithmically with instantaneous incident. intensity.

Such pixel circuits do not carry out integration of a photocurrent. They have a very large simultaneous dynamic range and are more resistant to saturation than pixel

circuits having a linear response to incident intensity. However, such a pixel circuit has disadvantages when used at low intensity levels. Firstly, the output voltage signal has a low signal-to-noise ratio because it corresponds to an instantaneous intensity level incident on the pixel circuit rather than being derived from an integrated photocurrent. Secondly, the pixel circuit's speed of response at low intensity levels is slow, because photocurrents within the pixel are too low in magnitude to charge and discharge parasitic capacitances within the pixel circuit quickly. Furthermore, such a pixel circuit typically has a small output voltage swing at normal levels of incident intensity because the circuit's full output swing corresponds to a large dynamic range of incident intensities. An image generated by an array of such logarithmic pixel circuits appears noisy or bland, owing to poor discrimination between very similar output voltages.

There is therefore a need for a pixel circuit which has a logarithmic response at high intensity levels, in order to avoid saturation problems, and a linear response at low intensity levels, in order to provide an output voltage signal with an adequate signal- to noise ratio and an adequate response time. Such a pixel circuit, known as a"log- linear"or"linear-log"pixel circuit, has been proposed by Fox et al in the paper "Wide Dynamic Range Pixel with Combined Linear and Logarithmic Response and Increased Signal Swing", Proceedings of SPIE, volume 3965, pp 4-10 (2000).

The prior art log-linear pixel circuit mentioned above comprises a photodiode, a diode-connected load transistor and a reset transistor having its drain maintained at a voltage above the circuit's supply voltage and its source connected to the photodiode's positive terminal. During operation of such a pixel circuit, output voltage signals are generated at the photodiode's positive terminal and read out onto a output line via a source follower and a read-out transistor in response to a pulsed read-out control signal applied to the gate of the read-out transistor. Prior to application of a pulse to the gate of the read-out transistor the gate of the reset transistor is switched from zero volts to a voltage equal to the circuit's supply voltage by a pulse of a pulsed reset control signal. This increases the voltage at the photodiode's positive terminal towards the supply voltage and sets that voltage to a

first voltage from which it decreases linearly with time to a second voltage which is either a linear or logarithmic function of incident radiation intensity depending on the duration of an integration period between pulses of the reset and read-out control signals.

Images generated by an array of such prior art log-linear pixel circuits suffer from image-dependent noise because the positive terminal of a photodiode within a given pixel circuit is reset to a voltage which depends on the intensity of radiation incident on that pixel. Spatial characteristics of image-dependent noise depend on the scene being imaged rather than on the pixel circuits of a pixel array; correcting for such noise is therefore not possible without a priori knowledge of scenes to be imaged. In most practical situations, this knowledge is unavailable.

It is an object of the invention to provide an alternative log-linear pixel circuit.

According to an aspect of the present invention, there is provided a log-linear pixel circuit comprising a photodetector for generating an output voltage signal at an output thereof in response to radiation incident thereon, and a field-effect transistor (FET) having its source connected to the output and being arranged for sub- threshold conduction during of operation of the circuit, characterised in that the circuit further comprises resetting means for resetting the output to a fixed reset voltage which is independent of the incident radiation's intensity.

The invention provides the advantage that an imaging system employing an array of such log-linear pixel circuits is able to provide higher quality images than digital imaging systems employing prior art log-linear pixel circuits. A log-linear pixel circuit according to the invention also provides the advantage that, in an imaging system employing an array of such log-linear pixel circuits, image quality may be traded-off for reduced power consumption according to a user's requirements.

Preferably the resetting means comprises an n-channel FET having its source connected to the output and its drain connected to a supply voltage VSuppLy, and

switching means for switching the gate voltage of the n-channel FET to a voltage V which is greater than the circuit's supply voltage. This allows the circuit to be implemented using standard complementary metal-oxide-semiconductor (CMOS) technology. Alternatively, the resetting means may comprise a p-channel resetting FET having its source connected to the output and its drain connected to a supply voltage Vsupp, ya and switching means for switching the gate voltage of the p-channel resetting FET to a voltage V which more negative than the supply voltage.

Preferably the FET and the resetting means comprise a single FET and means for switching the voltage on the gate of the FET between the circuit's supply voltage VDD and the voltage V. This allows a digital imaging system employing an array of log-linear pixel circuits of the invention to be implemented using a pixel array chip having only three transistors per pixel.

Preferably, the voltage V is between 10% and 100% greater than the supply voltage where the resetting means comprises an n-channel resetting FET. Where the resetting means comprises a p-channel resetting FET, preferably the supply voltage is negative and the voltage V has a magnitude between 10% and 100% greater than the supply voltage. This provides for the output voltage at the output terminal of the photodetector to be reset to the fixed reset voltage without wasting power or damaging the circuit.

Conveniently, the photodetector may be a photodiode.

Preferably output voltage signals are read out via a source follower so that they buffer the photodetector from loading effects.

The circuit may further comprise means for reading out output voltage signals in response to a control signal. This allows a user to vary the circuit's integration period and hence to control the circuit's transition intensity.

According to another aspect of the invention, there is provided a pixel array system comprising a pixel array of log-linear pixel circuits wherein each log-linear pixel circuit comprises a photodetector for generating an output voltage signal at an output thereof in response to radiation incident thereon, and a field-effect transistor (FET) having its source connected to the output and being arranged for sub- threshold conduction during of operation of the circuit, characterised in that the system further comprises resetting means for resetting the output of a circuit to a fixed reset voltage which is independent of the intensity of radiation incident upon the circuit's photodetector.

Embodiments of the invention will now be described by way of example only with reference to the accompanying drawings in which: Figure 1 shows a prior art log-linear pixel circuit; Figure 2 illustrates operation of the Figure 1 circuit; Figure 3 shows a log-linear pixel circuit of the invention; Figure 4 illustrates operation of the Figure 3 circuit; Figure 5 shows another log-linear pixel circuit of the invention; Figure 6 shows a further log-linear pixel of the invention; Figure 7 illustrates operation of the Figure 6 circuit; Figures 8 and 9 show still further log-linear pixel circuits of the invention; Figure 10 shows a two-dimensional pixel array system of the invention; Figure 11 shows a multiplexer employed in the Figure 7 system; and

Figure 12 illustrates operation of the Figure 10 system.

Referring to Figure 1, there is shown a schematic representation of a prior-art log- linear pixel circuit indicated generally by 10. The pixel circuit 10 comprises four n- channel MOSFET transistors 12,14,16,18 and a photodiode 22. During operation of the pixel circuit 10 output voltage signals are generated at a point 13 (which is the positive terminal of the photodiode 22) and read out onto an output line 20.

Transistors 12 and 16 have drains 12D, 16D connected to a supply voltage VDD of the pixel circuit 10 which is nominally 5V. The gate of transistor 12 is also connected to VDD. The source 12S of transistor 12 is connected to the positive terminal 13 of the photodiode 22. The negative terminal 15 of the photodiode 22 is connected to ground. The gate 14G of transistor 14 is connected to a control signal C, which controls resetting of the pixel circuit 10 after an output voltage signal has been read out to the output line 20. The drain 14D of transistor 14 is connected to a voltage V, which is greater than VDD. The source 14S of transistor 14 is connected to the gate 16G of transistor 16 which acts as a source-follower. The source of transistor 16 is connected to the drain 18D of transistor 18, which is used to read out output voltage signals from the pixel circuit 10 onto the output line 20 in response to a control signal C2 which is applied to the gate 18G of transistor 18.

Referring to Figure 2 there are shown graphs of voltage versus time for the control signals C, and C2. The pixel circuit 10 operates as follows. During a readout period TREAD control signal C2 is switched from 0V to VDD and an output voltage signal generated at the terminal 13 is read out to the output line 20 via transistors 16 and 18. Following a readout period TREAD, control signal C2 is switched back to 0V and the control signal C, is switched from 0V to VDD for a reset period-CRST after which it is switched back to 0V for an integration period TINT and a subsequent readout period.

After a reset period, the point 13 is biased to a voltage higher than that needed for sub-threshold conduction of the transistor 14, and photocurrent generated within the photodiode 24 as a result of its illumination causes the voltage at the terminal 13 to

fall initially linearly during an integration period immediately following the reset period. This allows output voltage signals which have a linear dependence on incident radiation intensity to be read out from the pixel circuit 10 provided the integration period is relatively short. If the integration period is relatively long, the voltage at the point 13 falls further to a magnitude which results in sub-threshold conduction of the transistor 12 and output signal voltages of the pixel circuit 10 then have a logarithmic dependence on incident radiation intensity.

Referring to Figure 3, there is shown a log-linear pixel circuit of the invention, indicated generally by 30. Parts equivalent to those of the pixel circuit 10 are like referenced with reference numerals differing by a value of 20 from those in Figure 1.

The pixel circuit 30 comprises four n-channel MOSFET transistors 32, 34,36,38, a photodiode 42 and a multiplexer 35. The drains 32D, 34D, 36D of transistors 32, 34,36 are each connected to a supply voltage VDD which is nominally 5V. Output voltage signals are generated at a point 33, which is the positive terminal of the photodiode 42, and read out to an output line 40 via transistors 36,38 in response to a control signal C4 applied to the gate 38G of transistor 38. Transistor 36 acts as a source follower. A control signal C3 is applied to the gate of transistor 34 to reset the pixel circuit 30 following reading out of an output voltage signal onto the output line 40. The control signal C3 has two possible voltage states which are selectively applied to the gate 34G of transistor 34 by a multiplexer 35.

Referring to Figure 4, there are shown plots of voltage versus time for the control signals C3, C4 and voltage V33 at the point 33, illustrating four cycles of operation of the pixel circuit 10. Operation of the pixel circuit 30 is equivalent to that of the pixel circuit 10 except that during a reset period'TRST, the control signal C3 is switched between 0V and a voltage V, which is greater than VDD, for example 7V. This overdrives the gate of transistor 34 during a reset period causing V33to rise towards VDD and setting it to a fixed reset voltage VA which depends on V, and the geometry of transistor 34, and which is independent of the intensity of radiation incident on the photodiode 62. If V, is appreciably larger than Vpp, for example 9V, the transistor 34 is fully switched on during a reset period and VA = VDD. For lower values of V ;,

for example 6V, VA is reset to a voltage below VDD. Voltage VA is above an equilibrium value VB of V33 VB is dictated. by the photocurrent conducted by the photodiode 62. During a subsequent integration period TINT, V33 decreases linearly with time from the value VA at a rate which is dependent upon the radiation intensity incident on the photodiode 42. Figure 5 shows three plots 43,44,45 of voltage at the point 33 versus time corresponding to incident intensity levels 11, 12, 13 respectively where 11>12>13. At low intensity levels such 12 and 13 V33has a value at the end of an integration period which is a decreasing linear function of IXNT as illustrated by plots 44 and 45. At high intensity levels, such as 13, V33decreases linearly more rapidly and falls to the equilibrium voltage VB which is dictated by the current conducted by the photodiode 42 and which depends logarithmically on the intensity of radiation incident on the photodiode 42. For a fixed value of VA a user may vary the transition intensity of the pixel circuit 30 by varying the integration period. For a sufficiently short integration period, output voltage signals of the pixel circuit 30 have a linear dependence on incident radiation intensity for all values thereof, and for a sufficiently long integration period output voltage signals of the pixel circuit 30 have a logarithmic dependence on incident radiation intensity for all values thereof. By varying the integration period between these extremes the transition intensity of the pixel circuit 30 may be varied. Alternatively, for a fixed integration period, the transition intensity of the pixel circuit 30 may be varied by adjusting the voltage VA. This may be carried out by adjusting V,.

V, may be less than 7V, for example 6V. A lower value for V, results in the pixel circuit 30 consuming less power but also results in some variation of the voltage VA as a function of incident intensity. This results in greater image noise within images produced by an array of log-linear pixels circuits such as 30. Image quality may therefore be traded-off for reduced power consumption. Preferably the voltage V, is between 1. 1VDD and 2vox.

For a fixed value of the voltage VA, the transition intensity of the pixel circuit 30 may be adjusted by adjusting the integration period TINT Alternatively for a given

integration period IINT this may be achieved by adjusting the voltage VA : in practice this adjustment is made by altering the voltage V, to vary the quantity V,-VDD.

Other types of photodetector may be used in the circuit 30 in place of the photodiode 42, for example a phototransistor.

Within an imaging system having an array of log-linear pixel circuits such as 30, slight geometrical differences in transistors of the array result in a small variation in the voltage VA amongst pixel circuits of the array. This results in a certain amount of fixed pattern noise in images produced by the system, however by reading out output voltage from pixel circuits of the array immediately after resetting, a measure of the variation may be captured and used for fixed pattern noise correction.

Figure 5 shows another log-linear pixel circuit of the invention, indicated generally by 130. Parts equivalent to those of the circuit 30 are like referenced with a prefix of 1. The circuit 130 comprises a photodiode 142, p-channel FETs 132,134 and n- channel FETs 136,138, and has a supply voltage VDD. Drains 132D, 134D of transistors 132, 134 are connected to a supply voltage Vss. The circuit 130 is operated in a manner equivalent to operation of the circuit 30. Following read-out of an output signal onto the output line 140, the voltage at point 133 is reset by switching the voltage on the gate of the transistor 134 from the supply voltage VDD to a voltage V2 which is less than Vs.

Referring now to Figure 6, there is shown further log-linear pixel circuit of the invention indicated generally by 50. Parts equivalent to those of the pixel circuit 10 are like referenced with reference numerals differing by a value of 40 from those in Figure 1. The pixel circuit 50 comprises three n-channel-MOSFET transistors 52, 56, 58, a photodiode 62 and a multiplexer 55. The drains 52D, 56D of transistors 52 and 56 are connected to a supply voltage VDD of 5V. Output voltage signals generated at a point 53, which is the positive terminal of the photodiode 62, are read out from the pixel circuit 50 via transistors 56, 58 to an output line 60 in response to a control signal C6 applied to the gate of transistor 58. Transistor 56

acts as a source follower. The voltage of the point 53 is denoted by V53. A control signal C5 is applied to the gate of transistor 52 to reset the pixel circuit 50 after an output voltage signal has been read out onto the output line 60.

Referring to Figure 7, there are shown graphs of voltage versus time for the control signals C5, C6 which illustrate three cycles of operation of the pixel circuit 50. During a readout period TREAD control signal C6 is switched from 0V to Vpp and an output voltage signal is read out onto the output line 60. Following a readout periodiREAD, control signal C6 is switched back to 0V and the control signal C5 is switched from VDD to a voltage V3 for a reset period TRST after which it is switched back to VDD for an integration period TINT and a subsequent readout period. V3 is greater than VDD, for example 7V. The gate of transistor 52 is therefore overdriven during a reset period, raising V53 towards the value VDD and setting it to a fixed reset voltage VA which is determined by the geometry of transistor 56 and voltage V3, and which is independent of the intensity of radiation incident on the photodiode 62. During a subsequent integration period, V53 decreases linearly with time from VA towards an equilibrium voltage VB at a rate proportional to the intensity of radiation incident on the photodiode 62. For a low incident radiation intensity the value of V53 at the end of an integration period is a linear function of incident intensity. For a high incident radiation intensity V53 decreases more rapidly and reaches a voltage VB which is dictated by the current conducted by the photodiode 62 and which is a logarithmic function of the intensity incident on the photodiode 62.

The pixel circuit 50 has only three MOSFET transistors and therefore provides the advantage that a digital imaging system comprising an array of such pixel circuits may be implemented using a CMOS chip having only three transistors per pixel circuit. Furthermore an array of pixel circuits such as 50 has a fill-factor and resolution equivalent to arrays based on prior art linear or logarithmic pixel circuits.

V3 may be less than 7V ; for example 6V. A lower voltage for V3 results in the pixel circuit 50 consuming less power but also results in some variation of VA as a function of incident intensity. This results in greater image noise within images

produced by an array of log-linear pixels circuits such as 50. Image quality may therefore be traded-off for reduced power consumption. Preferably the voltage Vs is between 1. 1 Voo and 2VoD.

Other types of photodetector may be used in the circuit 30. in place of the photodiode 62, for example a phototransistor.

Within an imaging system having an array of log-linear pixel circuits such as 30, slight geometrical differences in transistors of the array result in a small variation in the voltage VA among the pixel circuits of the array. This results in a certain amount of fixed pattern noise in images produced by the system, however by reading out output voltage from pixel circuits of the array immediately after resetting, a measure of the variation may be captured and used for fixed pattern noise correction.

Referring to Figure 8, there is shown a further log-linear pixel circuit of the invention indicated generally by 150. Parts of the circuit 150 equivalent to those of the circuit 50 are like referenced with a prefix 1. The circuit 150 comprises a photodiode 162, a p-channel MOSFET transistor 152, n-channel MOSFET transistors 156,158 and a multiplexer 155. The circuit 150 has supply voltages VDD, Vss of 5V and 0V respectively. Operation of the circuit 150 is the same as that of the circuit 50 except that during a reset period the gate of the transistor 152 is switched from Vss to a negative voltage V4, for example or-2V.

Figure 9 shows a further log-linear pixel circuit of the invention indicated generally by 250. Parts of the circuit 250 equivalent to those of the circuit 50 are like referenced with a prefix 2. The circuit 250 comprises a photodiode 262, p-channel MOSFET transistors 252,256,258 and a multiplexer 255. The circuit 250 has supply voltages VDD of 5V and Vss of 0V. Operation of the circuit 250 is the same as that of the circuit 50 except that during a reset period the gate of the transistor 252 is switched from Vss to a negative voltage V4, for example or-2V.

Referring now to Figure 10, there is shown a two-dimensional pixel array system of the invention, indicated generally by 70. The system 70 comprises a two- dimensional array of log-linear pixel circuits 50 of the type shown in Figure 6 disposed on a single CMOS chip. The array shown is a 4 x 4 array for the sake of clarity and ease of explanation but an array of any size may be used depending on user requirements and available silicon area on the CMOS chip. The array has rows 73A, 73B, 73C, 73D. VDD and ground connections (not shown) are made to each of the pixel circuits 50. Preferably the ground connection is distributed as a metal plane covering all active circuitry on the CMOS chip with the exception of the photodetectors of the pixel circuits 50. The metal plane then acts as a low- impedance ground plane and a light shield preventing photons from exciting active circuitry of the CMOS chip other than the photodetectors. Each column of pixel circuits 50 is connected to a respective output line 72A, 72B, 72C, 72D onto which output voltage signals are read during operation of the system 70. Control signals C7A, C7B, C7C, C7D are applied via control lines 74A, 74B, 74C, 74D respectively to reset pixel circuits 50 within rows 73A, 73B, 73C and 73D following reading out of output voltage signals onto the output lines 72A, 72B, 72C, 72D. A control signal such as C7A may take one of two possible voltages, namely VDD or V3. Control signals C7A, C7B, C7C, C7D are each generated by a respective multiplexer, such as 78A, which is supplied with two constant reset voltages Vrst1 = VDD, Vrst2 = V3 and a digital control signal such as Y1. Multiplexer 78A outputs a reset voltage Vrst1 = VDD when the control signal Y1 is a digital"1"and a voltage Vrst2 = V3 when the digital control signal Y1 is a digital"0". Multiplexers 78B, 78C, 78D operate in a like manner and receive digital control signals Y2, Y3 and Y4 respectively.

Control signals Y1, Y2, Y3, Y4 are generated by respective shifts register stages 82A, 82B, 82C, 82D of a shift register, which, together with a multiplexer 82 forms a first row scanner. The multiplexer 82 is arranged to receive a control signal "controlB", which has two possible states, and a digital input signal"In2B". The shift register stages 82A, 82B, 82C, 82D are connected in series as shown in Figure 7 and are arranged such that each receives a clock signal"clockB". Shift register stage 82D has an output which is connected to an input of multiplexer 82.

Control signals C8A, C8B, C8c, CsD are applied via control lines 76A, 76B, 76C, 76D respectively to read out output voltage signals from the pixel circuits 50 within rows 73A, 73B, 73C and 73D onto the output lines 72A, 72B, 72C, 72D during operation of the system 70. A particular control signal such as C8A may take on one of two possible voltage values, namely zero volts and VDD. The control signals Czar Cog, C8C7 C8D are received from a second row scanner comprising a multiplexer 80 and shift register stages 80A, 80B, 80C, 80D which each receive a clock signal"clockA".

Multiplexer 80 is arranged to receive a control signal"controlA"and a digital input signal"In2A". Clock signals clockA, clockB have the same period TcLocx-Shift register stage 80D has an output connected to an input of multiplexer 80.

Each output line 72A, 72B, 72C, 72D is connected to a respective column amplifier 84A, 84B, 84C, 84D. Column amplifiers are well known to those skilled in the art of electronics and will not be discussed further. The column amplifiers 84A, 84B, 84C, 84D are connected in parallel and their outputs are connected to a buffer 88.

Output voltage signals received at the column amplifiers 84A, 84B, 84C, 84D are sequentially read out to an output 89 via the buffer 88 in response to control signals col1, col2, col3, col4 from a readout scanner comprising a multiplexer 86 and shift register stages 86A, 86B, 86C, 86D. Multiplexer 86 receives a digital input signal"In2C"and a control signal"controlC". A clock signal"clockC"is supplied to the shift register stages 86A, 86B, 86C, 86D and has a frequency which exceeds TCLOCK by a factor equal to the number of pixels circuits 50 in a row of the array.

Shift register stage 86D has an output connected to an input of multiplexer 86.

Multiplexers 78A, 78B, 78C, 78D are required to pass a voltage Vrst2 = V3 which is greater than the supply voltage VDD Standard multiplexers are not suitable for this purpose. Figure 11 shows multiplexer 78A, which is based on n-well CMOS technology, in further detail. The multiplexers 78B, 78C, 78D are of like construction. Multiplexer 78A comprises two n-channel MOSFET transistors 90,94 and two p-channel MOSFET transistors 92,96 connected as shown in Figure 8.

Transistors 92,96 are formed in a common n-well which is held at a voltage Vw.

The system 70 comprises means (not shown) to set Vw to the greater of Vrst1 and

Vrst2. Thus in the present case Vw = V3. Digital control signal Y1 is applied to the gates of transistors 90,96 and the complement of Y1 is applied to the gates of transistors 92,94. The drain of transistor 90 and the source of transistor 92 are connected to reset voltage Vrst1, which in the present embodiment is the supply voltage VDD. The drain of transistor 94 and the source of transistor 96 are connected to reset voltage Vrst2, which in the present case is V3.

The first and second row scanners and the column scanner may be implemented using other suitable addressing means, for example a suitable combination of demultiplexers (or address decoders) and latches.

The system 70 is operated as follows. A bit pattern having a single digital"0"and all other bits set to digital"1"is loaded into the first row scanner. To achieve this, control signal"controlB"is set to a first state and a bit provided by the signal In2B is loaded into the multiplexer 82 under control of clock signal clockB so that the shift register stage 82A stores that bit. With each subsequent cycle of clockB, the bit stored within a given shift register stage is passed to the next shift register stage in the direction of the arrow 71 and an additional bit corresponding to signal In2B is loaded into the shift register stage 82A. By varying the digital signal In2B with each clock cycle, the first row scanner may be loaded with a desired bit pattern; in the first mode of operation the first row scanner is loaded with a bit pattern having a single digital"0"and having all other bits set to digital"1". When the shift register stages 82A, 82B, 82C, 82D have been loaded, the control signal controlB is switched to a second state and further clock cycles then cause the bit pattern to be circulated repeatedly through the shift register stages 82A, 82B, 82C, 82D. Those skilled in the art of electronics will appreciate that with suitable polarities for the shift register stages and control signals, the same effect could be produced by circulating a bit pattern having a single digital"1"and having all other bits set to digital"0".

The second row scanner is loaded with the same bit pattern such that the digital"0" is offset by two rows from that in the bit pattern stored in the first row scanner.

During operation of the system 70 the second row scanner circulates the bit pattern in the same manner as the first row scanner. Loading and operation of the second row scanner are carried out in response to clock signal clockB, control signal controlA and digital input signal In2A, in a similar manner to that described above in respect of the first row scanner.

The column scanner comprising multiplexer 86 and shift register stages 86A, 86B, 86C, 86D is also loaded with a bit pattern having a single digital"0"and having all other bits set to digital"1". The bits of the bit pattern are supplied by the digital signal In2C and read into the scanner under control of clock signal clockC when control signal controlC is in a first state. With controlC set to a second state, further cycles of the clock signal clockC cause the bit pattern to circulate through the shift register stages 86A, 86B, 86C, 86D as previously described with respect to the first and second row scanners.

Referring now to Figure 12, there are shown graphs of voltage versus time for the control signals C7A, C7B, C7C, C7D which control resetting of the pixel circuits 50, and for the control signals C8A, Cgs, Cgc, C8D which provide for output voltage signals to be read out from the pixel circuits 50. Two read out cycles of the system 70 are illustrated. The voltage on each of the lines 76A, 76B, 76C, 76D is switched in turn from 0 volts to VDD as the digital"0"of the bit pattern stored in the second row scanner cycles through the shift register stages 80A, 80B, 80C, 80C in response to the clock signal clockA. Similarly, the voltage on each of the lines 74A, 74B, 74C, 74D is switched from VDD to V2 as the digital"0"of the bit pattern stored within the first row scanner is cycled through the shift register stages 82,82A, 82B, 82C, 82D in response to clock signal clockB. Pulses comprising the control signals C7A, C7B, C7C, C7D, C8A, C8B, C8C, C8D have a duration equal to the period TCLOCK of the clock signals clockA, clockB.

The integration period for the pixel circuits 50 of the array is equal TCLOCK the bit pattern stored in the second row scanner is offset from that stored in the first row scanner by two rows of the array. Other integration periods may be set by a user of

the system 70 by offsetting the bit patterns in the first and second row scanners by a different number of rows, or by altering the clock period Clock- Alternatively, the system 70 may comprise a pixel array which consists of log-linear pixel circuits of a kind shown in any one of Figures 3,5,8 and 9, provided suitable voltage Vrst1, Vrst2 are supplied to the multiplexers 78A, 78B, 78C, 78D.