Title:
LOGIC CIRCUIT GENERATION DEVICE AND METHOD
Document Type and Number:
WIPO Patent Application WO/2015/087957
Kind Code:
A1
Abstract:
In the present invention, a specific information processing function, which assumes circuit implementation, is described in a programming language, and from this description, an RTL description that can be logic synthesized is automatically generated. A logic circuit generation device (1) comprises: a control flow graph generation unit (23) for generating a control flow graph; a control flow degenerate conversion unit (28) for generating a control flow degenerate program by deleting all condition branch commands from the control flow program; a data flow graph generation unit (29) for generating a data flow graph from the control flow degenerate program; and a logic circuit description output unit (33) for generating logic circuit description indicating a sequence circuit in which a rooted branch of the data flow graph corresponds to the wiring of the logic circuit and a node of the data flow graph corresponds to the calculator of the logic circuit.
Inventors:
ISSHIKI TSUYOSHI (JP)
Application Number:
PCT/JP2014/082797
Publication Date:
June 18, 2015
Filing Date:
December 11, 2014
Export Citation:
Assignee:
TOKYO INST TECH (JP)
International Classes:
G06F17/50
Foreign References:
| JP2012118835A | 2012-06-21 | |||
| JP2009211614A | 2009-09-17 | |||
| JP2000113026A | 2000-04-21 | |||
| JP2011134308A | 2011-07-07 |
Other References:
TOSHINOBU MATSUBA ET AL.: "Clock Frequency Enhancement by SSA Transformation of Hardware Behavioral Descriptions", DA SYMPOSIUM 2008, 19 August 2008 (2008-08-19), pages 103 - 108
Attorney, Agent or Firm:
ISONO INTERNATIONAL PATENT OFFICE, P. C. (JP)
Patent business corporation Isono international patent trademark office (JP)
Patent business corporation Isono international patent trademark office (JP)
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