Title:
LOGIC CIRCUITRY
Document Type and Number:
WIPO Patent Application WO2006044175
Kind Code:
A3
Abstract:
A logic circuit (100) including at least one evaluate circuit (130) coupled to a static output logic circuit (190). In one example, the evaluate circuit (130) includes a dynamic node (139), a full keeper (132), an evaluate device (136), and a logic tree (134). In some examples, the output logic circuit is a sampled static output logic circuit (150) and includes a sample device. In some examples, the logic circuit includes multiple evaluate circuits (140), each with a dynamic node (149) coupled to a control gate of a transistor of the output logic circuit. Some examples may include a delay (180) in a clock signal to increase the internal race margin.
Inventors:
BJORKSTEN ANDREW A (US)
MAI KHOI B (US)
ROSSBACH PAUL C (US)
MAI KHOI B (US)
ROSSBACH PAUL C (US)
Application Number:
PCT/US2005/035468
Publication Date:
July 06, 2006
Filing Date:
September 30, 2005
Export Citation:
Assignee:
FREESCALE SEMICONDUCTOR INC (US)
BJORKSTEN ANDREW A (US)
MAI KHOI B (US)
ROSSBACH PAUL C (US)
BJORKSTEN ANDREW A (US)
MAI KHOI B (US)
ROSSBACH PAUL C (US)
International Classes:
H03K19/096
Foreign References:
| US6646487B2 | 2003-11-11 | |||
| US5933038A | 1999-08-03 | |||
| US6690204B1 | 2004-02-10 |
Download PDF: