Title:
LOGIC INTEGRATED CIRCUIT, CONFIGURATION INFORMATION SETTING METHOD, AND RECORDING MEDIUM
Document Type and Number:
WIPO Patent Application WO/2020/095854
Kind Code:
A1
Abstract:
In order to reduce influence of a single event transient while satisfying both requirements of a circuit scale and speed performance, a logic integrated circuit is provided with: a first logic selection circuit to which a first signal group which is not made redundant of a logic signal group is input and which selects, on the basis of a combination of signals constituting the first signal group, at least two data signals from a data signal group; a filter circuit to which the at least two data signals selected by the first logic selection circuit are input and which removes a glitch included in the at least two data signals; and a second logic selection circuit to which a second signal group which is made redundant of the logic signal group and an output data signal group of the filter circuit are input and which selects, on the basis of a combination of signals constituting the second signal group, at least one of the output data signal group.
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Inventors:
MIYAMURA MAKOTO (JP)
NEBASHI RYUSUKE (JP)
TADA AYUKA (JP)
BAI XU (JP)
NEBASHI RYUSUKE (JP)
TADA AYUKA (JP)
BAI XU (JP)
Application Number:
PCT/JP2019/043139
Publication Date:
May 14, 2020
Filing Date:
November 01, 2019
Export Citation:
Assignee:
NEC CORP (JP)
International Classes:
H03K19/003; H01L21/82; H01L21/822; H01L27/04; H03K17/693; H03K19/177
Domestic Patent References:
| WO2018047124A1 | 2018-03-15 | |||
| WO2017126451A1 | 2017-07-27 |
Foreign References:
| US6768338B1 | 2004-07-27 | |||
| JP2009296312A | 2009-12-17 | |||
| US20140247068A1 | 2014-09-04 | |||
| JP2012221077A | 2012-11-12 |
Attorney, Agent or Firm:
SHIMOSAKA Naoki (JP)
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