Title:
LOGIC INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2017/126451
Kind Code:
A1
Abstract:
The purpose of the present invention is to provide a logic integrated circuit that increases the reliability of configurative information held in a switch while maintaining high damper resistance and a small chip area. This logic integrated circuit has a three-terminal resistance change switch having a first resistance change switch and a second resistance change switch connected in series, a reading circuit for reading first data based on the resistance state of the first resistance change switch and second data based on the resistance state of the second resistance change switch, and a first error detection circuit for comparing the first data and the second data and issuing output based on the result of the comparison.
Inventors:
NEBASHI RYUSUKE (JP)
SAKAMOTO TOSHITSUGU (JP)
MIYAMURA MAKOTO (JP)
TSUJI YUKIHIDE (JP)
TADA AYUKA (JP)
BAI XU (JP)
SAKAMOTO TOSHITSUGU (JP)
MIYAMURA MAKOTO (JP)
TSUJI YUKIHIDE (JP)
TADA AYUKA (JP)
BAI XU (JP)
Application Number:
PCT/JP2017/001147
Publication Date:
July 27, 2017
Filing Date:
January 16, 2017
Export Citation:
Assignee:
NEC CORP (JP)
International Classes:
G11C13/00; H03K19/177
Domestic Patent References:
| WO2012043502A1 | 2012-04-05 | |||
| WO2013187193A1 | 2013-12-19 | |||
| WO1999048103A1 | 1999-09-23 |
Foreign References:
| JP2015082671A | 2015-04-27 | |||
| US20140043059A1 | 2014-02-13 |
Attorney, Agent or Firm:
SHIMOSAKA Naoki (JP)
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