Title:
LOGIC INTEGRATED CIRCUIT, LOGIC CIRCUIT USING SAME, COMPARATOR, AND HIGH RELIABILITY SYSTEM
Document Type and Number:
WIPO Patent Application WO/2015/075783
Kind Code:
A1
Abstract:
There is a tendency for costs, at which masks for manufacturing ASICs are designed and manufactured, to surge with the integration degree being enhanced according to Moore's law. It has been, therefore, predicted that ASICs will be no longer applicable unless ASICs are in considerably mass production. Especially, the quantity of production of highly reliable, highly safe systems to which the present invention is directed is naturally limited because of the specialty of the application purposes thereof. In view of this, it has been expected to utilize a field programmable gate array (FPGA) that can suppress the initial costs in manufacture. The objective of the invention is to prevent explosion in number of test patterns that is a problem in using FPGA. The outputs of LUTs constituting a logic circuit of interest are extracted outside FPGA and then checked by use of a test circuit.
Inventors:
KANEKAWA NOBUYASU (JP)
SHIMAMURA KOTARO (JP)
KANNO YUSUKE (JP)
HIROTSU TEPPEI (JP)
SHIMAMURA KOTARO (JP)
KANNO YUSUKE (JP)
HIROTSU TEPPEI (JP)
Application Number:
PCT/JP2013/081224
Publication Date:
May 28, 2015
Filing Date:
November 20, 2013
Export Citation:
Assignee:
HITACHI LTD (JP)
International Classes:
H03K19/173; H03K19/007
Domestic Patent References:
| WO2009107309A1 | 2009-09-03 |
Foreign References:
| JPS61201342A | 1986-09-06 | |||
| JPH04248712A | 1992-09-04 |
Attorney, Agent or Firm:
INOUE Manabu et al. (JP)
Manabu Inoue (JP)
Manabu Inoue (JP)
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