LOGIC INTEGRATED CIRCUIT

WIPO Patent Application WO/2019/059118

A1

The present invention provides a programmable logic integrated circuit with which it is possible to reduce leakage current while inhibiting increase in the number of connection wires and a consequent increase in occupied area. This logic integrated circuit is a logic operation circuit that has a plurality of first switch cells including variable resistance elements and a plurality of second switch cells including variable resistance elements, the logic integrated circuit comprising: a first output port and a second output port; the plurality of first switch cells for switching the electrical connections between a first wire and a third wire; the plurality of second switch cells for switching the electrical connections between a second wire and the third wire; a first control transistor which is connected to the first wire and which is for switching the electrical connections between the first wire and a first power line supplying power to the first wire; and a second control transistor which is connected to the second wire and which is for switching the electrical connections between the second wire and the first power line supplying power to the second wire.

TSUJI YUKIHIDE (JP)
SAKAMOTO TOSHITSUGU (JP)
MIYAMURA MAKOTO (JP)
NEBASHI RYUSUKE (JP)
TADA AYUKA (JP)
BAI XU (JP)

PCT/JP2018/034150

March 28, 2019

September 14, 2018

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NEC CORP (JP)

H01L21/82; H01L21/822; H01L21/8239; H01L27/04; H01L27/105; H01L45/00; H01L49/00; H03K19/177

WO2016042750A1	2016-03-24
WO2016194332A1	2016-12-08
WO2012032937A1	2012-03-15
WO2013190742A1	2013-12-27

JP2016178183A	2016-10-06
JP2000232162A	2000-08-22
JP2013251888A	2013-12-12

SHIMOSAKA Naoki (JP)

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