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Patent Searching and Data


Title:
LOGIC INTEGRATED CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2019/146534
Kind Code:
A1
Abstract:
In order to provide a logic integrated circuit having a reduced chip area, the present invention provides a logic integrated circuit comprising a switch cell array that has: a plurality of first wirings extending in a first direction; a plurality of second wirings extending in a second direction; switch cells that include unit elements including two serially connected resistance-changing elements, and that also include cell transistors connected to a shared terminal of the two resistance-changing elements; and bit lines to which the shared terminal is connected via the cell transistors. Two switch cells adjacent in the first direction are connected to different first wirings and second wirings, and the two switch cells share the bit lines and a diffusion layer to which the bit lines are connected.

Inventors:
NEBASHI Ryusuke (7-1 Shiba 5-chome, Minato-k, Tokyo 01, 〒1088001, JP)
SAKAMOTO Toshitsugu (7-1 Shiba 5-chome, Minato-k, Tokyo 01, 〒1088001, JP)
MIYAMURA Makoto (7-1 Shiba 5-chome, Minato-k, Tokyo 01, 〒1088001, JP)
TSUJI Yukihide (7-1 Shiba 5-chome, Minato-k, Tokyo 01, 〒1088001, JP)
TADA Ayuka (7-1 Shiba 5-chome, Minato-k, Tokyo 01, 〒1088001, JP)
BAI Xu (7-1 Shiba 5-chome, Minato-k, Tokyo 01, 〒1088001, JP)
Application Number:
JP2019/001581
Publication Date:
August 01, 2019
Filing Date:
January 21, 2019
Export Citation:
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Assignee:
NEC CORPORATION (7-1 Shiba 5-chome, Minato-ku Tokyo, 01, 〒1088001, JP)
International Classes:
H01L21/82; G11C13/00; H01L21/8239; H01L27/105; H01L45/00; H01L49/00; H03K19/177
Domestic Patent References:
WO2017126451A12017-07-27
WO2016194332A12016-12-08
Foreign References:
JP2018007167A2018-01-11
Attorney, Agent or Firm:
SHIMOSAKA Naoki (7-1 Shiba 5-chome, Minato-k, Tokyo 01, 〒1088001, JP)
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