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Title:
LOW-AREA LOW CLOCK-POWER FLIP-FLOP
Document Type and Number:
WIPO Patent Application WO/2017/147895
Kind Code:
A1
Abstract:
In one example, an apparatus may be a flip-flop that includes a slave latch and a master latch. The master latch includes a first logic element in the master latch. The first logic element includes a first transistor. The first transistor is shared by a second logic element in one of the master latch or the slave latch. The first transistor provides a clocking signal input to the first logic element and the second logic element.

Inventors:
RASOULI SEID HADI (US)
KANG HANANEL (US)
CAI YANFEI (US)
CHEN XIANGDONG (US)
BOYNAPALLI VENUGOPAL (US)
Application Number:
PCT/CN2016/075596
Publication Date:
September 08, 2017
Filing Date:
March 04, 2016
Export Citation:
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Assignee:
QUALCOMM INC (US)
RASOULI SEID HADI (US)
KANG HANANEL (US)
CAI YANFEI (US)
CHEN XIANGDONG (US)
BOYNAPALLI VENUGOPAL (US)
International Classes:
H03K3/356; H03K3/012; H03K3/3562
Foreign References:
US8941429B22015-01-27
CN105191127A2015-12-23
CN104796132A2015-07-22
CN105122646A2015-12-02
CN102394596A2012-03-28
US20130278314A12013-10-24
Attorney, Agent or Firm:
SHANGHAI PATENT & TRADEMARK LAW OFFICE, LLC (CN)
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