The precise timing of events in digital circuitry is supervised and synchronized by free running clock signals. The clock generator, usually a crystal oscillator, can be designed to run on low current consumption. The output of a clock generator must typically be buffered before it is transmitted to another component in which it is to be used (i. e., the clock load), such as an application specific integrated circuit (ASIC). In order to get it to the clock load, the clock signal is very often routed on a printed circuit board or other such means for mounting and/or interconnecting the various components and/or devices that make up the circuit. This routing, together with input loads, effectively forms a capacitive load to ground. This stray capacitive load, together with the voltage swing needed at the load, determines the current needed in the clock generator's output buffer before transmitting the signal. For higher frequencies, the stray capacitive load can cause this current to become quite large. For example, a 13 MHZ clock signal typically requires a buffer current in the range of 1 mA This problem is illustrated in FIG. 1. A first ASIC 101 includes a clock generator 103 that generates a clock signal. The clock signal is supplied to a buffer 105, that is also within the first ASIC 101. The clock signal at the output of the buffer 105 is to be transmitted to other components, such as a clock input 109 that is within a second ASIC 107. However, the higher the frequency of the clock signal, the more it will be diverted through the stray capacitance, represented in FIG. 1 as the capacitor CSTRAY 111. The more the clock is diverted, the more current must be supplied by the buffer 105 in order to ensure that a sufficient amount of current is received at the clock input 109.

This problem is not insubstantial, because many modern-day applications require that as little power as possible be expended. For example, in mobile communications systems, the mobile terminals are very often battery powered. In order to extend the battery life, the circuits within the mobile terminal must be designed to utilize as little power as possible. Saving power on clock distribution is one way of doing this.

Furthermore, the more power that is utilized to distribute a clock signal in a mobile terminal, the more noise there is likely to be transmitted to the radio or other analog parts of the transceiver circuits. Thus, it is important to utilize a clock generator that generates very little noise. Reducing the power that is supplied to the clock generator is one way of doing this.

SUMMARY It is therefore an object of the present invention to provide methods and apparatuses capable of using low currents to distribute clocks in applications that are characterized by stray capacitances.

In accordance with one aspect of the present invention, the foregoing and other objects are achieved in a methods and apparatuses in which a clock signal is distributed to a load by generating a current clock signal having a periodic current waveform ; and distributing the current clock signal to the load. By using a current clock signal rather than the conventional voltage clock signal, virtually no power loss occurs through stray capacitances.

In another aspect of the invention, voltage changes at the input of the load are kept to a minimum by supplying the distributed current clock signal to a low impedance input means ; and supplying the current clock signal from the low impedance input means to the load. In some embodiments, the low impedance input means may be a current mirror. In alternative embodiments, the low impedance input means may be an amplifier having an input terminal, and coupled to a suitable feedback circuit that causes the input terminal to have a low input impedance.

Many loads are designed to utilize voltage, rather than current waveforms. Thus, in still another aspect of the invention, the current clock signal supplied at the output of the low impedance input means is converted from a current

clock signal into a corresponding voltage clock signal. The corresponding voltage clock signal is then supplied to the load.

In yet another aspect of the invention, the current clock signal having the periodic current waveform may be generated by generating a voltage clock signal having a voltage waveform ; and converting the voltage clock signal into the current clock signal having the periodic current waveform.

BRIEF DESCRIPTION OF THE DRAWINGS The objects and advantages of the invention will be understood by reading the following detailed description in conjunction with the drawings in which : FIG. 1 is a block diagram of a conventional clock distribution technique ; FIG. 2 is a block diagram of a clock distribution system in accordance with one aspect of the invention ; FIG. 3 is a block diagram of an exemplary embodiment of a current clock generator in accordance with one aspect of the invention ; FIG. 4 is a block diagram of an exemplary embodiment of a clock distribution system in accordance with the invention ; FIG. 5 is a block diagram of an exemplary embodiment of a low impedance input circuit in accordance with one aspect of the invention ; and FIG. 6 is a block diagram of a low impedance input circuit in accordance with an alternative embodiment of one aspect of the invention.

DETAILED DESCRIPTION The various features of the invention will now be described with respect to the figures, in which like parts are identified with the same reference characters.

Referring now to FIG. 2, the losses in the parasitic capacitor are reduced by substantially eliminating the voltage swing in the clock signal. That is, by substantially holding the clock voltage constant, there will be no current flowing through the stray capacitance 111. In accordance with one aspect of the invention, a current swing is used in place of a clock voltage swing. In one embodiment, this is accomplished by supplying the clock signal from the clock generator 103 to a voltage- to-current converter 203. The output of the voltage-to-current converter 203 is a

current waveform that is distributed to the clock load in place of the conventional voltage waveform.

FIG. 3 is a block diagram of an exemplary current clock generator. A balanced oscillator 301 generates a voltage clock signal in accordance with conventional techniques, and therefore need not be described here in detail. Optional outputs ports 305 supply a voltage clock signal for internal use. An output of the balanced oscillator 301 is also supplied to a voltage-to-current converter 303, which in this example is an emitter follower arrangement comprising a transistor 307 having an emitter coupled to one end of a resistor 309, the other end of which is tied to ground.

The collector of the transistor 307 supplies the output current clock signal.

In another aspect of the invention, the distributed clock voltage is maintained substantially constant by providing the load with a low impedance input 207. With a sufficiently low impedance input 207, the voltage on the receiving node is essentially constant, thus substantially eliminating any current flow through the stray capacitor 111. Because current is no longer diverted through the stray capacitor 111, it is possible to reduce the amount of current that needs to be supplied from the clock source.

In one exemplary embodiment of the invention, the low impedance input 207 is provided in the form of a current mirror 401, as shown in FIG. 4. The second leg of the current mirror 401 mirrors the clock current received in the first leg. The mirrored clock current is then converted back to a clock voltage swing over a resistor 403. This clock voltage may then be supplied to the clock input 109, which utilizes it in the usual manner. The parasitic capacitances are very small inside the ASIC, so that the current consumption in the current mirror 401 can be low.

Alternatives to the current mirror 401 may be utilized in other embodiments. For example, an amplifier with feedback may be configured to provide the low impedance input 207.

FIG. 5 is a block diagram of one such configuration. In this example, a modified common base/gate stage is utilized. For this circuit, an approximation of the input impedance, Zin is given by the formula :

Z ~<BR> <BR> <BR> <BR> '"J?<BR> <BR> <BR> <BR> °m7°m2) where gm, and gm2 are the respective transconductances of the first and second transistors 501 and 503. It can be seen that large transconductances will keep the input impedance of this configuration low. This circuit also performs a current to voltage conversion (see the Vout port) through the resistor R2. The output voltage is given by Vout-Iin xR2. A lowpass filter 505 is provided to generate the reference signal VRF. In order to operate correctly, the VREF signal has to be on the same DC level as the input port. A simple RC low pass filter disposed between the input port 507 and the VREF signal is a simple way to do this.

Viewed at a high level, it will be recognized by those having ordinary skill in the art that the circuit illustrated in FIG. 5 is merely one exemplary embodiment of a type of circuit for serving as the low impedance input 207, where in general the circuit has a transistor (e. g., the second transistor 503) having a drain terminal, a source terminal and a gate terminal ; an impedance circuit (e. g., the resistor R2) having a first terminal coupled to a voltage source and a second terminal coupled to the drain terminal of the transistor ; and an inverting clock signal amplifier (e. g., the differential amplifier including the first transistor 501) having an input terminal (e. g., the gate of first transistor 501) and an output terminal (e. g., the drain of first transistor 501). The input terminal of the inverting clock signal amplifier is coupled to the source terminal of the transistor and to the input port 507, and the output terminal of the inverting clock signal amplifier is coupled to the gate terminal of the transistor.

Other embodiments of this arrangement may also be used as the low impedance input 207, including but not limited to those embodiments in which bipolar transistors are substituted for one or more of the illustrated field effect transistors (FETs).

FIG. 6 is a block diagram of an alternative embodiment of a low impedance input circuit, in accordance with one aspect of the invention. Here, an operational amplifier 601 is arranged with a resistor, R 1, in a feedback path between the output port and the non-inverting input port. The input current clock signal, I in, is also supplied to the non-inverting input terminal. The inverting input terminal of the operational amplifier 601 is tied to a voltage reference level, VREF-In this arrangement, the input impedance, Zin, is approximately : A - in R1 The inventive technique of distributing the clock in the form of a current signal is especially useful when the clock is to be delivered to only one load. A current signal may advantageously also be distributed to two or more loads. However, when more than one load is involved, it is advisable to match the loads with each other so that the current will be divided up equally among them.

The invention has been described with reference to a particular embodiment. However, it will be readily apparent to those skilled in the art that it is possible to embody the invention in specific forms other than those of the preferred embodiment described above. This may be done without departing from the spirit of the invention. For example, in the exemplary embodiments, the clock generation equipment, as well as the clock loads, are all shown embodied within ASICs. It will be readily apparent to a skilled person, however, that this is merely for illustrative purposes, and that the use of ASICs is in no way essential to practicing the invention.

To the contrary, the inventive principles of utilizing a current clock (and converting a voltage clock to a current clock, if necessary), distributing the current clock and receiving the current clock in a low impedance load (and converting the received current clock into a voltage clock, if necessary) may be employed in any manner of construction, including the use of discrete components, and other types of integrated circuit devices.

Thus, the preferred embodiment is merely illustrative and should not be considered restrictive in any way. The scope of the invention is given by the appended claims, rather than the preceding description, and all variations and equivalents which fall within the range of the claims are intended to be embraced therein.