LOW POWER ARCHITECTURES

WIPO Patent Application WO/2014/145066

A3

Systems and methods for operating transistors near or in the sub¬ threshold region to reduce power consumption are described herein. In one embodiment, a method for low power operation comprises sending a clock signal (Ck) to a flop (150) via a clock path (225) comprising a plurality of transistors, wherein the clock signal has a high state corresponding to a high voltage (VH) that is above threshold voltages of the transistors in the clock path (225). The method also comprises sending a data signal (D) to the flop (150) via a data path (135) comprising a plurality of transistors, wherein the data signal has a high state corresponding to a low voltage (VL) that is below threshold voltages of the transistors in the data path (135). The method further comprises latching the data signal (D) at the flop (150) using the clock signal (Ck).

BRUNOLLI MICHAEL JOSEPH (US)

PCT/US2014/029721

November 06, 2014

March 14, 2014

Click for automatic bibliography generation  

QUALCOMM INC (US)

H03K3/037; H03K3/356

US5568429A	1996-10-22
US20080258790A1	2008-10-23

IK JOON CHANG ET AL: "Robust Level Converter for Sub-Threshold/Super-Threshold Operation:100 mV to 2.5 V", IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, IEEE SERVICE CENTER, PISCATAWAY, NJ, USA, vol. 19, no. 8, 1 August 2011 (2011-08-01), pages 1429 - 1437, XP011336682, ISSN: 1063-8210, DOI: 10.1109/TVLSI.2010.2051240
HAVARD PEDERSEN ALSTAD ET AL: "Seven subthreshold flip-flop cells", NORCHIP, 2007, IEEE, PISCATAWAY, NJ, USA, 19 November 2007 (2007-11-19), pages 1 - 4, XP031240537, ISBN: 978-1-4244-1516-8

LANGTON, Grant, T. et al. (P.O. Box 2207Wilmington, DE, US)

View/Download PDF      PDF Help

Previous Patent: AFFINITY-BASED ANALYTICAL PURIFICATION OF BIOTHERAPEUTCS FOR BIOPROCESS MONITORING

Next Patent: TOPICAL COMPOSITIONS OF FLUNISOLIDE AND METHODS OF TREATMENT