Title:
LOW-POWER-CONSUMPTION FRACTIONAL FREQUENCY-DIVISION PHASE-LOCKED LOOP CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2022/161193
Kind Code:
A1
Abstract:
Disclosed in the present invention is a low-power-consumption fractional frequency-division phase-locked loop circuit, comprising a phase discrimination module, a voltage-to-current conversion module, a loop filter, a voltage-controlled oscillator, a frequency divider, and a digital logic module. The phase discrimination module, the voltage-to-current conversion module, the loop filter, the voltage-controlled oscillator, and the frequency divider are connected in sequence; a reference signal is inputted from the phase discrimination module, and the phase discrimination module performs phase discrimination on the reference signal and a feedback signal having a quantization error and outputted by the frequency divider, compensates a quantization phase error generated by fractional frequency division, and outputs a compensated phase discrimination result to the voltage-to-current conversion module; a quantization error generated by fractional frequency division is converted to a voltage domain by means of a digital domain or is directly coupled to a phase error signal in the phase discrimination module to complete compensation for the quantization error. According to the present invention, edge conversion processes in the quantization error compensation process and the sampling phase discrimination process are combined, thereby reducing the frequency of edge conversion, reducing power consumption, and completing compensation for the quantization error generated by fractional frequency division.
Inventors:
GAO XIANG (CN)
JIN GAOFENG (CN)
FENG FEI (CN)
JIN GAOFENG (CN)
FENG FEI (CN)
Application Number:
PCT/CN2022/072209
Publication Date:
August 04, 2022
Filing Date:
January 17, 2022
Export Citation:
Assignee:
UNIV ZHEJIANG (CN)
International Classes:
H03L7/08; H03L7/18
Foreign References:
| CN112953516A | 2021-06-11 | |||
| CN105871372A | 2016-08-17 | |||
| CN110739966A | 2020-01-31 | |||
| US10804913B1 | 2020-10-13 |
Other References:
JIN GAOFENG; FENG FEI; GAO XIANG; CHEN WEN; SHU YIYANG; LUO XUN: "A 3.3-4.5GHz Fractional-N Sampling PLL with A Merged Constant Slope DTC and Sampling PD in 40nm CMOS", 2021 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM (RFIC), IEEE, 7 June 2021 (2021-06-07), pages 63 - 66, XP033947496, DOI: 10.1109/RFIC51843.2021.9490495
Attorney, Agent or Firm:
HANGZHOU QIUSHI PATENT OFFICE CO., LTD. (CN)
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