Field of the Invention

[0001] The present invention relates to analogue to digital conversion (ADC).

In particular, the present invention relates to a low power hybrid ADC for high- resolution analogue to digital signal conversion.

Background

[0002] In CMOS technology, power consumption of analog to digital converter does not scale linearly with resolution, PAUL: ° FS X 2 ⁿ , where FS is sampling frequency and N is resolution of the analog to digital converter. This is due to larger capacitors and transistors that are needed to prevent the process and circuit errors limiting the precision under a required design specification, in the case of high- resolution binary weighted charge redistribution successive approximation analog to digital converter (CR SA-ADC), the precision is limited by matching of integrated capacitors. The bigger the ratio of largest capacitor to smallest capacitor, more challenges to achieve a required accuracy. For example, in a 12-bit binary weighted CR SA-ADC, the largest capacitor is 2" x Cunit, where Cunit is the capacitance of the smallest capacitor, and accordingly, the total capacitance in the binary array is 2 ¹² x Cunit. This results in large power consumption in order to charge and discharge these capacitors during data conversion and also the accuracy is severely affected due to poor matching. (0003] I'IG. 1A illustrates a block diagram of a typical successive approximation analogue-digital converter (SA-ADC) well known in the art. The SA- ADC typically includes a sample and hold (S/H) circuit 102 for acquiring input voltage, Vin, a successive approximation register (SAR) for supplying an approximate digitalized Vi _n to an internal digital-to-analoguc converter (DAC) 106, an analogue voltage comparator 108 for comparing the Vj _n to the output of the internal DAC 106, and an internal relcrcncc DAC that supplies the comparator 108 with an analogue voltage equivalent of the digitized output of the SAR 104 for comparison with V,·,,.

[0004] Operationally, the SAR 1 4 is initialized to set the most significant bit (MSB) to 1. The MSB is fed into the DAC 106, which then supplies the analog equivalent of the digital code (i.e. V _re t/2) into the comparator 108 for comparison with the sampled inpul voltage. If this analog voltage exceeds V _in , the comparator 108 causes the SAR to reset this bit; otherwise, the bit is left as 1. Then the next bit is set to I and the same test is done, continuing this binaiy search until every bit in the SAR has been tested. The resulting output is the digital approximation of the sampled input voltage and is ultimately output by the DAC at the end of the conversion (EOC).

[0005] SAR ADC is designed with low power consumption, high resolution and accuracy, and a small form factor. The main limitations of the SAR architecture arc the lower sampling rales and the requirements that the building blocks, the DAC and the comparator, be as accurate as the overall system.

[0006] FIG. IB illustrates a block diagram of a known time based cyclic/algorithmic ADC (CYC-ADC). The CYC-ADC has a sample and hold stage implemented by a capacitor array and an am lifier. Residue voltage is generated in the CYC-ADC. Such CYC-ADC. is relatively slower than a SA ADC because it cycles through or generates one bit of conversion for many clock cycles as compared to one bit of resolution per cycle for the SA ADC.

Summary [0007] In one aspect of the present invention provides a hybrid analoguc-to- digital converter (ADC) comprise a successive approximation analoguc-to-digital converter (SAR-ADC); and a time based integrating and cyclic analogue-to-digital converter (CYC-ADC) integrated with the SAR-ADC. An input analogue signal is processed through the SAR-ADC to output a first output constituting most significant bits (MSBs) of an digital output signal and a residue signal, the residue signal is further processed through the CYC-ADC to output a second output constituting the least significant bits (LSBs).

[0008] in one embodiment, the SAR-ADC further comprises a comparator, a capacitor array, a successive approximation register (SAR) and a digital to analog converter (DAC), and the CYC-ADC further comprises an analogue switch network, a pair of capacitor, a state-machine, a reference current generator, wherein the CYC-ADC is coupled to share the comparator with the SAR-ADC. The DAC of the SAR-ADC is coupled with the SAR and output analogue signal to the comparator. The pair of capacitors may also be adapted for performing signal integrating over time; the network of switches for directing different charging currents to different capacitors: the state- machine to generate control signals for the analogue switch network and the comparator; an output register to stoic converted bits. [0009] In another embodiment, the SAR-ADC is adapted to process the analogue input signal to acquire first M-bit MSBs of the output digital signal and the residue signal is processed through the CYC-ADC to acquire the remaining LSBs.

[0010] In another aspect of the present invention, there is provided a method of converting an analogue input signal to a digital output signal. The method comprises converting the analogue input signal through a successive approximation to output a first output constituting part of the total bits of the digital output signal and a residue signal; processing the residue signal through a lime- based integrating cyclic analog to digital conversion lo output a second output constituting the remaining bits of the digital output signal; and combining the first output and the second output to output the digital output signal.

[0011] hi one embodiment, the method further comprises identifying the first output as the most significant bits of the digital output signal; identifying the second output as the least significant bils of Ihe digital uulput signal; and adding the first output to the second output lo output the digital output signal.

[0012] In another embodiment, adding ihe first output and Ihe second output further comprises shifting bits of the first output such the first output constitute the most significant bits of the second portion of the conversion result are added to one or more least significant bits of the digital output signal. [0013] 7n a further embodiment, converting the analogue input signal through the successive approximation further include performing a number of analog to digital conversion iterations, the number of analog to digital conversion iterations is less than the number of bits in the digital output signal. Yet, processing the residue signal through the time- based integrating cyclic conversion includes performing a number of analog lo digital conversion iterations, wherein the number of analog to digital conversion iterations is less than the number of bits in the digital output signal. [0014] The successive approximation may produce a single bit of resolution for each iteration and the time based integrating cyclic based analog to digital conversion produces two bits of resolution during the first iteration and a single bit of resolution for subsequent iterations.

Brief Description of the Drawings [0015] This invention will be described by way of non-limiting embodiments of the present invention, with reference to the accompanying drawings, in which:

[0016] FIG. 1A shows a typical successive approximation analogue to digital converter;

[0017] FIG. IB shows a typicaJ time based cyclic/algorithmic ADC; [0018] FIG. 2A illustrates a schematic diagram of an ULPII-A C 200 in accordance with one embodiment of the present invention;

[0019] FIG. 2B illustrates a general flow process of the ADC conversion in accordance with an embodiment of the present invention;

[0020] FIGs. 3A to 3D illustrate a first step of the ULPH-ADC of the present invention; and [0021] FTGs. 4A and 4B illustrate a second step of the ULPII-ADC οΓ the present invention.

Detailed Description

[0022] In line with the above summary, the following description of a number of specific unci alternative embodiments is provided to understand the inventive features of the present invention. It shall be apparent to one skilled in the art, however that this invention may be practiced without such specific details. Some of the details may not be described at length so as not to obscure the invention. For ease of reference, common reference numerals will be used throughout the figures when referring to the same or similar features common to the figures.

[0023] In ultra-low power operation applications, the most optimal resolution in terms of power consumption for different analoguc-to-digital conversion (ADC) topologies can be combined to yield a very power efficient architecture especially for high-resolution Nyquist rate ADC. Such combination must however be synergistic in terms of low power circuit blocks (i.e. without op-amps) and method of conversion (i.e. power should scale linearly with resolution and speed).

[0024] The present invention provides an Ultra Low Power Hybrid Analog

Digital Converter (ULPII-ADC) adapted for converting an analogue input signal to a digital output signal using a two-step approach: resolving the analogue input signal through a successive approximation algorithm; and resolving analogue residue voltage, VRES SAK through time based integrating cycl ic ADC. [0025] FTG. 2Λ illustrates a schematic diagram of an ULPH-ADC 200 in accordance with one embodiment of the present invention. The ULPH-ADC 200 is a hybrid of a successive approximation ADC (SAR-ADC) and a time based integrating and cyclic ADC (CYC-ADC) adapted for converting an analogue input signal into a digital signal at a desire bit The ULPH-ADC comprises a comparator 202, a capacitor array 204, a digital-to-analogue converter (DAC) 205 and a successive approximation register 206 coupled to form a SAR-ADC, and an analogue switch network 208, a pair of capacitors 210, a logic circuit 212 and a reference current generator 214 coupled with the same comparator 202 to form the CYC-ADC. The logic circuit 212 further comprises a state-machine to generate control signals for the analogue switch network and an output register to store converted bits. The output of the capacitor array 204 is electrically coupled to comparator 202. The pair of capacitors 210 are provided for performing signal integrating over time, the analogue switch network 208 is used for directing different charging currents to different capacitors 210 for performing signal integration over time.

[0026] FIG. 2B illustrates a general flow process of the ADC conversion in accordance with an embodiment of the present invention. The ADC conversion encompasses two different known methods for converting analogue signals to digital signals, The two known method are carrying out in two main steps. In the first step 250, first half most significant bits (MSUs) are processed through a successive approximation. Λ residue voltage is generated at Ihe end of the successive approximation A D conversion 250. [0027] In a second stage 260, the next half least significant bits (LSBs) arc resolved from the residue voltage output with an integrated cyclic/algorithmic conversion.

[0028] Through the above method, as only part of the bits are converted through the successive approximation method, it requires a smallei- capacitance for the largest binary weighted capacitor when compared with one that process all the bits through the successive approximation method. Accordingly, the ratio of the largest to smallest capacitor is reduced resulting in improved ciipacitor matching and accuracy. For example, when a 12-bits digital output is desired from an analogue input, 6 out of 12 bits output is processed using successive approximation method, the largest binary weighted capacitor size for MSB bit is 2 ^s x Cunit instead of 2 ^{! l} x Cimit. Accordingly, the total capacitance that the reference voltage needs to be driven is also much smaller, i.c 2 ⁶ x Cunit instead of 2 ¹² x Cunit, which reduces overall power consumption.

[0029] The use of a time based integrating cyclic analogue-to-digital converter to resolve the next 6 (i.e. the remaining) LSBs does not increase power consumption the converter is designed for f> bit accuracy instead of 12 bit accuracy, further, as the hybrid ADC 200 is implemented with a single comparator shared by the SA-ADC and a reference current to keep the power consumption low. Further, the gain and subtraction routines arc performed by using time as an intermediate variable instead of voltage or current so substantial energy is saved.

[0030] Thus both types of converters benefit from reduced power consumption due to the fact that the circuit blocks of which are designed for half the resolution and accuracy of the final ADC. Further, as some of the components are shared by the two converters, it reduces the overall size.

[0031] FIGs. 3A to 3D illustrate the first step of the ULP1I-ADC in accordance with one embodiment of the present invention. he successive approximation algorithm is further earned in two phases: a sampling phase and a bit cycling phase.

[0032] As shown in FIG. 3A, the sampling phase is carried out by having an analogue input Vix sampled through the bottom plates of the capacitor array, when the top plate nodes are switched to VREF = V^. As shown iti FIG. 3B, the bottom plates of the capacitor array are then switched to V _UNU , with the top plates disconnected, i.e. 'D^C is a floating node. Through charge conservation, top plate node voltage VDAC hecorncs VR^.- - ^.

[0033] The successive approximation goes on to the bit cycling phase, where the register in SAR Logic block is first set to midseale, setting the MSB to Ί ^! and all other bits to Ό'. The bottom plate of the largest capacitor is switched to V m ^: , redistributing the charge on the top plates of the capacitors driving VfMc to -VI + VRRF/ as shown in FIG. 3C. V| _N is then compared to V . _\ c, if V _1N is greater than V _DA c o VDAC < , comparator output is logic ' and the MSB of the M-bit register remains at 1. Conversely, if VIN is less than VU _A C or V^ _A C > 0, the comparator output is logic 'Ο' and the MSB of the register is cleared to 0. The SAR control logic then moves to the next bit down, forces that bit high, and does another comparison as above. The sequence continues all the way down to the least significant bit (LSB), Once this is done, the conversion is completed, and the M-bit digital word is available in the register. FIG. 3D exemplifies a switch arrangement when the SA-ADC is completed. [0034] Through the SA-OAC illusti'ates above, the top plate of the capacitor array would have residue voltage VRES .SAR- The VRES SAR ^im be derived by the following:

[0035] V«ES _SA K - - IN + V _Kbf (B, 2 + B ₂ /4 + .... + B _M /2M) [0036] wherein Bi, B _2; ... B _N as value +/- 1 , M is the resolution.

[0037] Subsequently, the analog residue voltage, V _W |. _s _ _¾A r< is resolved in the second-step by using the time based integrating cyclic ADC, which will also be carryin out in two-phases, a MSB phase and a residue quantization phase. During the MSB phase as shown in TIG. 4A, the residue voltage is initially transferred (i.e. sampled and held) onto capacitor QN by charging the capacitor QN with an input current IIN until the voltage equals to VRHS SAK (VRES AK. ~ V _DAC ). Once the capacitor QN is charged up, CKUF is charged with ΙΚΗΓ- until its voltage is also equals to V^ES SAR ( iiEs_SAit = V[)AC) as shown in FIG. 4A. The operation can be done by the comparator 202. In this charging operation, the ratio IRHF ~ TRHF/TCI IC is to be obtained, wherein the RRF is the time required to charge C _R RF up to the voltage VRRSJAR and II is the current required for charging capacitor QN. Further, the IIN must be less than 41REF for conversion efficiency. A 2-bil counter can be used foi counting the number of clock edges during T _KTI .-, so that the input current l _& w can be quantized to within two bits f the reference current IIN. A residual time, T^, defined as time remaining beyond the last clock edge as shown in FiG. 4B is formed at the end of the ^'" !½(.·. At the end of the MSB phase, the comparator's output goes high. The MSB phase signals as a state- machine to reset both capacitors QN and C _R R _F to zero and to rearrange the analog circuitry such that m- i now redirected to charge QN. π

[0038] During the residue quantization phase, ^" l½ is obtained by subtracting the quantized signal from Ί½ρ. Subtraction of intermediate quantization results is automatic in the algorithm if integer number of quantisation clock cycles that have already passed (or not) are ignored and the residual time signal is always referenced to the next neighboring clock edge.

[0039] If T esis is defined as the time from end of up to the next clock edge, then T RSB = n,K - T _Bra

[0040] Quantizing ^' I sn is then equivalent to quantizing ^' l s: quantizing x and

(1 - x) are equivalent as long as we can digitally compensate for referencing with respect to 1 rather than with respect to 0.

[0041] The time TRESB can be converted into a voltage by integrating QN with I EF from the end of T _KB up to the next clock edge. Then, the voltage on N is

[0042] V I = (IRF.F X TRESB) / QN (2)

[0043] TKEF/QN is timc-to-voltagc conversion gain, and accordingly the conversion of TRCSII to Vci as timc-to-voltagc conversion. At this time, is switched over to charge CRRF until the voltage on CRM is equal to Vci . The latter comparison can be achieved by using the same comparator used during the MSB phase. As soon as the two voltages are equal, the voltage on capacitor ON is reset to zero, and the same charge integration on <¾ is repealed. At the end of this comparison, the TRESB m be amplified by two. By counting the number of cluck edges seen within 2TRESB _> Ι· ^ηκ number of clock edges seen within one bit of TCL can be quantized accordingly. [0044] After 2TRESB is quantized, it is subtracted from the un-quantized value to produce a new residue for successive conversions. To do so, the "subtraction" routine is repeated by encoding the time from the end of 2TKKSB to the next chick edge as a new residue. At the end of the amplification stage, both capacitors C _lN and C _liU v are reset to zero, and the slate-machine reconfigures the analog circuitry such that I _{K i} y. is now set to charge CREF- The elements are now in place to repeat the previous subtraction and amplification processes except that the time-to- voltage conversions are carrying out on CREP aiid voltagc-to-timc conversions are carrying out using C H- Each successive subtraction-and-amplitication process recursively yields one more bit through the hybrid ADC according to the present invention.

[0045] While specific embodiments have been described and il Instated, it is understood that many changes, modifications, variations and combinations thereof could be made to the present invention without departing from the scope of the invention.