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Title:
LOW POWER OPERATION FOR FLASH MEMORY SYSTEM
Document Type and Number:
WIPO Patent Application WO/2016/195845
Kind Code:
A1
Abstract:
The present invention relates to a circuit and method for low power operation in a flash memory system. In disclosed embodiments of a selection-decoding circuit path, pull-up and pull-down circuits are used to save values at certain output nodes during a power save or shut down modes, which allows the main power source to be shut down while still maintaining the values.

Inventors:
TRAN, Hieu Van (2642 Gayley Pl, San Jose, CA, 95135, US)
LY, Anh (3385 Lindmuir Dr, San Jose, CA, 95121, US)
VU, Thuan (431 Danna Ct, San Jose, CA, 95138, US)
NGUYEN, Hung Quoc (3272 Winding Vista Common, Fremont CA, 94539, GB)
NGUYEN, Viet Tan (26 Nguyen Van To, Ho Chi Minh, Minh, VN)
Application Number:
US2016/029390
Publication Date:
December 08, 2016
Filing Date:
April 26, 2016
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
SILICON STORAGE TECHNOLOGY, INC. (450 Holger Way, San Jose, CA, 95134, US)
International Classes:
G11C5/14; G11C7/10; G11C7/22; G11C8/10; G11C8/12; G11C16/08; G11C16/30; G11C16/32; G11C29/14
Foreign References:
US5970018A1999-10-19
Attorney, Agent or Firm:
YAMASHITA, Brent (DLA Piper LLP US, 2000 University AvenueEast Palo Alto, CA, 94303, US)
Download PDF:
Claims:
What Is Claimed Is:

1. A non- volatile memory device comprising:

a first circuit capable of operating in a shut down mode, wherein during shut down mode: a power source for the first circuit is shut down;

a first node in the first circuit is selectively connected to a second circuit that drives the first node to a high level; and

a second node in the first circuit is selectively connected to a third circuit that drives the second node to a low level.

2. The memory device of claim 1, wherein the first circuit is a decoder circuit.

3. The memory device of claim 1, wherein the first circuit is a test mode circuit.

4. The memory device of claim 2, further comprising a bulk voltage coupled to bulks of one or more transistors in the decoder circuit.

5. The memory device of claim 2, wherein the decoder circuit comprises a row decoder circuit.

6. The memory device of claim 1, wherein the first node is selectively connected to the second circuit through a first switch.

7. The memory device of claim 6, wherein the second node is selectively connected to the third circuit through a second switch.

8. The memory device of claim 1, wherein a third node in the first circuit is selectively connected to the second circuit that drives the third node to a high level.

9. The memory device of claim 1, wherein a fourth node in the first circuit is selectively connected to the third circuit that drives the fourth node to a low level.

10. The memory device of claim 8, wherein a fourth node in the first circuit is selectively connected to the third circuit that drives the fourth node to a low level.

11. The method of claim 1, wherein the first node and second node hold the same level from shut down mode to active mode

12. A method of executing a shut down mode in a non- volatile memory device comprising a first circuit, the method comprising:

asserting a signal that indicates the shut down mode;

in response to the signal, shutting down a power source for the first circuit;

selectively connecting a first node in the first circuit to a second circuit that drives the first node to a high level; and

selectively connecting a second node in the first circuit to a third circuit that drives the second node to a low level.

13. The method of claim 12, wherein the first circuit is a decoder circuit.

14. The method of claim 12, wherein the first circuit is a test mode circuit.

15. The method of claim 13, further comprising coupling a bulk voltage to bulks of one or more transistors in the decoder circuit.

16. The method of claim 13, wherein the decoder circuit comprises a row decoder circuit.

17. The method of claim 12, wherein the step of selectively connecting the first node to the second circuit comprises closing a first switch.

18. The method of claim 17, wherein the step of selectively connecting the second node to the third circuit comprises closing a second switch.

19. The method of claim 12, further comprising selectively connecting a third node in the first circuit to the second circuit to drive he third node to a high level.

20. The method of claim 12, further comprising selectively connecting a fourth node in the first circuit to the third circuit to drive the fourth node to a low level.

21. The method of claim 19, further comprising selectively connecting a fourth node in the first circuit to the third circuit to drive the fourth node to a low level.

22. The method of claim 12, wherein the first node and second node hold the same level from shut down mode to active mode

23. A method of executing a shut down mode in a non-volatile memory device comprising a first circuit, the method comprising:

asserting a signal that indicates the shut down mode;

in response to the signal, shutting down a power source for the first circuit;

selectively connecting a first node in the first circuit to a second circuit that drives the first node to a high level; and

selectively connecting a second node in the first circuit to a third circuit that drives the second node to a low level,

wherein the first node and second node hold the same level from shut down mode to active mode

24. The method of claim 23, further comprising:

asserting a shut down mode for circuit blocks comprising an array, row decoder, column decoder, high voltage decoder, sensing block, data out block, testmode block, trimbits-live block, trimbits block, command decoder, data in block, analog low voltage block, analog high voltage block, non-volatile controller, and

not asserting the shut down mode for circuit blocks comprising a power sequence controller, pin interface, and global power switch during a hard power down mode.

25. The method of claim 23, further comprising:

asserting the shut down mode for circuit blocks comprising part of an array, part of a row decoder, part of a column decoder, part of a high voltage decoder, part of a sensing block, data out block, testmode block, trimbits block, data in block , analog high voltage block, non- volatile controller, and

not asserting the shut down mode for circuit blocks comprising trimbits-live block, command decoder, analog low voltage block, power sequence controller, pin interface, and global power switch in a standby mode.

26. The method of claim 23, further comprising:

asserting the shut down mode for circuit blocks comprising part of an array, part of a row decoder, part of a column decoder, part of a high voltage decoder, part of a sensing block, testmode block, trimbits block, data in block, analog high voltage block, non- volatile controller, and

not asserting the shut down mode for circuit blocks comprising data out block, trimbits- live block, command decoder, analog low voltage block, power sequence controller, pin interface, and global power switch in the active mode.

27. The method of claim 23, further comprising:

asserting the shut down mode for circuit blocks comprising part of an array, part of a row decoder, part of a column decoder, part of a high voltage decoder, sensing block, data out block, testmode block, and

not asserting the shut down mode for circuit blocks comprising trimbits-live block, trimbits block, command decoder, data in block, analog low voltage block, analog high voltage block, non- volatile controller, power sequence controller, pin interface, and global power switch in the non- volatile operation mode.

28. A non- volatile memory device comprising:

a first device with first terminal coupled to high power supply and second terminal coupled to first terminal of a comparator; a second device coupled to first device's second terminal and to first terminal of the comparator, the second device further coupled to selected memory cell and

a second terminal of the comparator coupled to a reference voltage level.

29. The device of claim 28, wherein the memory device comprises an array of split gate flash memory cells.

30. The device of claim 29, wherein cell read current level of programmed state of selected memory cell is close to or below a zero current level.

31. The device of claim 30, wherein the memory cell is programmed using a deep programmed state.

32. The device of claim 31, wherein the coupling gate of the memory cell is biased at zero volt or negative voltage.

33. A method of operating a non- volatile memory device comprising:

time sampling a reference current or voltage in a floating holding node to obtain a hold voltage;

applying the hold voltage in the sensing circuitry

34. The device of claim 33, wherein the sensing circuitry comprises a sensing pull up PMOS transistor.

35. The device of claim 33, wherein the holding reference node is on a capacitor

36. The device of claim 33 further comprising an array of split gate memory cells.

37. The device of claim 33 further comprising a sampling PMOS transistor.

38. The device of claim 33 further comprising a reference element.

39. The device of claim wherein the reference element is a memory cell, a resistor, or a capacitor.

40. The claim of 33 wherein an operational amplifier applies the hold reference voltage into the sensing circuitry.

41. The method of operating a non- volatile memory comprising:

comparing a read address to a previous read address;

if a match is found, then not performing a read to the memory;

comparing current data to previous data; and

if a match is found, then not performing data out switching.

42. The method of claim 41 wherein the array comprises an array of spit gate memory cells.

43. The method of claim 42 wherein a bias is applied on a coupling gate and wordline of a memory cell.

44. A method of operating a non-volatile memory comprising:

reading with consecutive addressing in the column direction of a memory array starting at a selected row and selected columns

45. The method of claim 44 comprising:

performing a first consecutive column read for N words;

performing a second consecutive column read for N words starting at the row of the first consecutive column read and the next column from the column of the first consecutive column read.

46. The method of claim 44, wherein the array comprises spit gate memory cells.

47. The method of claim 45 wherein a bias is applied on a coupling gate and wordline of a memory cell.

48. The method of claim 44 further comprising: scrambling column addresses for a consecutive read.

49. The method of claim 44 further comprising scrambling row addresses for a consecutive read.

Description:
LOW POWER OPERATION FOR FLASH MEMORY SYSTEM

TECHNICAL FIELD

[0001] The present invention relates to a circuit and method for low power operation in a flash memory system. In disclosed embodiments of a selection-decoding circuit path, pull-up and pulldown circuits are used to save values at certain output nodes during a power save or shut down modes, which allows the main power source to be shut down while still maintaining the values.

BACKGROUND OF THE INVENTION

[0002] Non- volatile memory cells are well known in the art. One prior art non- volatile split gate memory cell 10 is shown in Figure 1. The memory cell 10 comprises a semiconductor substrate

12 of a first conductivity type, such as P type. The substrate 12 has a surface on which there is formed a first region 14 (also known as the source line SL) of a second conductivity type, such as

N type. A second region 16 (also known as the drain line) also of N type is formed on the surface of the substrate 12. Between the first region 14 and the second region 16 is a channel region 18.

A bit line BL 20 is connected to the second region 16. A word line WL 22 is positioned above a first portion of the channel region 18 and is insulated therefrom. The word line 22 has little or no overlap with the second region 16. A floating gate FG 24 is over another portion of the channel region 18. The floating gate 24 is insulated therefrom, and is adjacent to the word line 22. The floating gate 24 is also adjacent to the first region 14. The floating gate 24 may overlap the first region 14 to provide coupling from the region 14 into the floating gate 24. A coupling gate CG

(also known as control gate) 26 is over the floating gate 24 and is insulated therefrom. An erase gate EG 28 is over the first region 14 and is adjacent to the floating gate 24 and the coupling gate 26 and is insulated therefrom. The top corner of the floating gate 24 may point toward the inside corner of the T-shaped erase gate 28 to enhance erase efficiency. The erase gate 28 is also insulated from the first region 14. The cell 10 is more particularly described in U.S. Patent No.

7,868,375, whose disclosure is incorporated herein by reference in its entirety.

[0003] One exemplary operation for erase and program of prior art non-volatile memory cell 10 is as follows. The cell 10 is erased, through a Fowler-Nordheim tunneling mechanism, by applying a high voltage on the erase gate 28 with other terminals equal to zero volt. Electrons tunnel from the floating gate 24 into the erase gate 28 causing the floating gate 24 to be positively charged, turning on the cell 10 in a read condition. The resulting cell erased state is known as T state.

The cell 10 is programmed, through a source side hot electron programming mechanism, by applying a high voltage on the coupling gate 26, a high voltage on the source line 14, a medium voltage on the erase gate 28, and a programming current on the bit line 20. A portion of electrons flowing across the gap between the word line 22 and the floating gate 24 acquire enough energy to inject into the floating gate 24 causing the floating gate 24 to be negatively charged, turning off the cell 10 in read condition. The resulting cell programmed state is known as '0' state. The memory cell 10 is read in a Current Sensing Mode as following: a bias voltage is applied on the bit line 20, a bias voltage is applied on the word line 22, a bias voltage is applied on the coupling gate 26, a bias or zero voltage is applied on the erase gate 28, and a ground is applied on the source line 14. There exists a cell current flowing from the bit line 20 to the source line 14 for erased state and there is insignificant or zero cell current flow from the bit line 20 to the source line 14 for programmed state. Alternative the memory cell can be read in a Reverse Current

Sensing Mode, in which the bit line 20 is grounded and a bias voltage is applied on the source line. In this mode the current reverses the direction from the source line 14 to the bitline 20. The memory cell 10 alternatively can be read in a Voltage Sensing Mode as following: a bias current (to ground) is applied on the bit line 20, a bias voltage is applied on the word line 22, a bias voltage is applied on the coupling gate 26, a bias voltage is applied on the erase gate 28, and a bias voltage is applied on the source line 14. There exists a cell output voltage (significantly >0v) on the bit line 20 for erased state and there is insignificant or close to zero output voltage on the bit line 20 for programmed state. Alternative the memory cell can be read in a Reverse Voltage Sensing Mode, in which the bit line 20 is biased at a bias voltage and a bias current (to ground) is applied on the source line. In this mode the cell output voltage is on the source line 14 instead of on the bit line 20.

[0004] In the prior art, various combinations of positive or zero voltages were applied to word line 22, coupling gate 26, and floating gate 24 to perform read, program, and erase operations

[0005] In response to the read, erase or program command, the logic circuit 270 causes the various voltages to be supplied in a timely and least disturb manner to the various portions of both the selected memory cell 10 and the unselected memory cells 10.

[0006] For the selected and unselected memory cell 10, the voltage and current applied are as follows. As used hereinafter, the following abbreviations are used: source line or first region 14 (SL), bit line 20 (BL), word line 22 (WL), and coupling gate 26 (CG).

Table No. 1: PEO (Positive Erase Operation ) Table

Read 1.0- ov 0.6-2V OV- 0-2.6V 0-2.6V 0- 0- 0-2.6V

2V FLT 2.6V 2.6V

Erase ov ov OV OV OV 0-2.6V 0- 11.5- 0-2.6V

2.6V 12V

Program IV ov luA Vinh 10- 0-2.6V 0- 4.5- 0-2.6V

11V 2.6V 5V

[0007] In a recent application by the applicant— US Patent Application No. 14/602,262, filed on January 21, 2015, which is incorporated by reference— the applicant disclosed an invention whereby negative voltages could be applied to word line 22 and/or coupling gate 26 during read, program, and/or erase operations. In this embodiment, the voltage and current applied to the selected and unselected memory cell 10, are as follows. Table No. 2: PEO (Positive Erase Operation ) Table

[0008] In another embodiment of US Patent Application No. 14/602,262, negative voltages can be applied to word line 22 when memory cell 10 is unselected during read, erase, and program operations, and negative voltages can be applied to coupling gate 26 during an erase operation, such that the following voltages are applied: Table No. 3: PNEO (Positive Negative Erase Operation) Table

[0009] The CGINH signal listed above is an inhibit signal that is applied to the coupling gate 26 of an unselected cell that shares an erase gate 28 with a selected cell. [0010] Figure 2 depicts an embodiment recently developed by applicant of an architecture for a flash memory system comprising die 200. Die 200 comprises: memory array 215 and memory array 220 for storing data, memory arrays 215 and 220 comprising rows and columns of memory cells of the type described previously as memory cell 10 in Figure 1, pad 240 and pad 280 for enabling electrical communication between the other components of die 200 and, typically, wire bonds (not shown) that in turn connect to pins (not shown) or package bumps that are used to access the integrated circuit from outside of the packaged chip or macro interface pins (not shown) for interconnecting to other macros on a SOC (system on chip); high voltage circuit 275 used to provide positive and negative voltage supplies for the system; control logic 270 for providing various control functions, such as redundancy and built-in self-testing; analog circuit 265; sensing circuits 260 and 261 used to read data from memory array 215 and memory array 220, respectively; row decoder circuit 245 and row decoder circuit 246 used to access the row in memory array 215 and memory array 220, respectively, to be read from or written to; column decoder circuit 255 and column decoder circuit 256 used to access bytes in memory array 215 and memory array 220, respectively, to be read from or written to; charge pump circuit 250 and charge pump circuit 251, used to provide increased voltages for program and erase operations for memory array 215 and memory array 220, respectively; negative voltage driver circuit 230 shared by memory array 215 and memory array 220 for read and write operations; high voltage driver circuit 225 used by memory array 215 during read and write operations and high voltage driver circuit 226 used by memory array 220 during read and write operations.

[0011] With flash memory systems becoming ubiquitous in all manner of computing and electronic devices, it is increasingly important to create designs that reduce the amount of power consumed by the flash memory system. What is needed is novel circuitry for reducing power consumption in a flash memory system. SUMMARY OF THE INVENTION

[0012] The present invention relates to a circuit and method for low power operation in a flash memory system. In disclosed embodiments of a selection-decoding circuit path, pull-up and pulldown circuits are used to save values at certain output nodes during a power save or shut down modes, which allows the main power source to be shut down while still maintaining the values. Low power read reference generation are described. Address and data encoding, decoding and scrambling to save power is described.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a cross-sectional view of a non-volatile memory cell of the prior art to which the method of the present invention can be applied.

[0014] Figure 2 is a block diagram of a non- volatile memory device using the non- volatile memory cell of the prior art shown in Figure 1.

[0015] Figure 3 is a block diagram of an embodiment of a non-volatile memory device.

[0016] Figures 4 A and 4B depict embodiments of pull-down circuits.

[0017] Figures 5 A and 5B depict embodiments of pull-up circuits.

[0018] Figures 6A and 6B depict a first embodiment of a selection-decoding circuit path.

[0019] Figures 7A and 7B depict a second embodiment of a selection-decoding circuit path.

[0020] Figures 8A and 8B depict a third embodiment of a selection-decoding circuit path.

[0021] Figure 9 depicts a test mode circuit.

[0022] Figure 10 depicts a global power switch circuit.

[0023] Figure 11A and 11B depict local power switch circuits.

[0024] Figure 12 depicts a row decoder circuit. [0025] Figure 13 depicts a sensing circuit.

[0026] Figure 14 depicts a sampling circuit for providing a sampled reference current to a sensing circuit.

[0027] Figure 15 depicts another sampling circuit for providing a sampled reference current to a sensing circuit.

[0028] Figure 16 depicts an embodiment of a read path for a memory device.

[0029] Figure 17 depicts symbols of different gate configurations.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0030] Figure 3 depicts an embodiment of an architecture for a flash memory system comprising die 300. Die 300 comprises memory section 390. Memory section 390 comprises memory blocks 391 and 392, where memory block 391 comprises memory arrays 302 and 322 and memory block 392 comprises memory arrays 312 and 332 for storing data, each of memory arrays 302, 312, 322, and 332 comprising rows and columns of memory cells of the type described previously as memory cell 10 in Figure 1; sensing circuit 346 used to read data from memory arrays 302 and 322 and sensing circuit 345 used to read data from memory arrays 312 and 332; row decoder circuits 303, 313, 323, and 333 used to access the selected row in memory arrays 302, 312, 322, and 332, respectively, to be read from or written to; column decoder circuits 304, 314, 324, and 334 used to access bytes in memory arrays 302, 312, 322, and 332, respectively, to be read from or written to; local power switches 305, 315, 325, and 335 for row decoders 303, 313, 323, and 333; local power switch 347A,347B for column decoder circuits 304, 314, 324, and 334; local power switches 348A,348B for sensing circuits 346 and 345 ; and local power switches 342 and 343 for high voltage row decoder WSHDR 341 and 344. [0031] Die 300 further comprises the following functional structures and sub-systems: pads (not shown) for enabling electrical communication between the other components of die 300; wire bonds (not shown) that in turn connect to pins (not shown) or package bumps (not shown) that are used to access the integrated circuit from outside of the packaged chip or macro interface pins (not shown) for interconnecting to other macros on a SOC (system on chip); low voltage generation (including a low voltage charge pump circuit) circuits 361 and high voltage generation (including a high voltage charge pump circuit) circuit 362 used to provide increased voltages for program and erase operations for memory arrays 302, 312, 322, and 332; non-volatile operation controller circuit 363 shared by memory arrays 302, 312, 322, and 332 for read and write operations; low voltage generation circuit 361 used by memory arrays 302, 312, 322, and 332; high voltage generation circuit 362 used by memory arrays 302, 312, 322, and 332; analog low voltage circuit 359 and analog high voltage circuit 360 used by analog circuitry on die 300; global power switch (GPS) circuit 364; data out circuit 351; test mode circuit 352; trimbits-live circuit 353; trimbits circuit 354; command decoder circuit 355; data in circuit 356; power sequence controller 357; and pin interface 358. The circuit blocks 351-356,359-363 have local power switches inside their blocks.

[0032] Trimbits circuit 354 is used to store bits used during a trimming process whereby certain parameters in the flash memory system are configured, adjusted, and/or optimized. These bits can include non- volatile configuration bits such as algorithm parameters and endurance (number of erase/program cycles) data retention specification configuration bits and non- volatile trimbits such as bits for the high voltage range that are applied to erase gate 28, control gate 26, source line 14; the ranges used for Vinh and Iprog (current for bit line 20 during a programming operation) such as the ones specified in Tables 1-3, above; temperature operating range and timing ranges for erase and program operations. [0033] Trimbits-live circuit 353 is used to store configuration bits used during a normal operation of the flash memory system. These bits can include read trimbits used to configure certain parameters, such as read timing; read bias; voltage ranges that are applied to bitline 20, word line 22, erase gate 28, and control gate 26; Icellref trim values for configuring a reference cell current; and redundancy configuration. These bits also can include read configuration parameters such as read low width, write 10 width, read speed, and power mode.

[0034] HARD POWER DOWN

[0035] A hard power down operation can be implemented on die 300 when the overall system is being shut down through a shut down command from the user, such as when a mobile device containing die 300 is shut down by a user pressing the power button.

[0036] During a hard power down of die 300, the following portions are powered down: memory section 390, data out circuit 351; test mode circuit 352; trimbits-live circuit 353; trimbits circuit 354; command decoder circuit 355; data in circuit 356; analog low voltage circuit 359; analog high voltage circuit 360; low voltage generation circuit 361; high voltage generation circuit 362; and non- volatile operation controller circuit 363. Circuits used to assist in the power down mode are described below.

[0037] During a hard power down of die 300, the following portions remain powered on: power sequence controller 357; pin interface 358; and GPS circuit 364.

[0038] SOFT POWER DOWN

[0039] A soft power down operation can be implemented on die 300 when the overall system is being shut down through a shut down command from the operating system or similar device, such as when the operating system of a mobile device containing die 300 commands the system to shut down. Circuits used to assist in the power down mode are described below. [0040] During a soft power down of die 300, the following portions are powered down: memory section 390, data out circuit 351; test mode circuit 352; trimbits circuit 354; command decoder circuit 355; data in circuit 356; analog low voltage circuit 359; analog high voltage circuit 360; low voltage generation circuit 361; high voltage generation circuit 362; and non- volatile operation controller circuit 363.

[0041] During a soft power down of die 300, the following portions remain powered on: trimbits- live circuit 353; power sequence controller 357; pin interface 358; and GPS circuit 364.

[0042] STANDBY

[0043] A standby operation can be implemented on die 300 when the overall system is being placed in a sleep mode, such as when a mobile device containing die 300 is placed in a sleep mode.

[0044] During a standby operation of die 300, the following portions are powered down: memory section 390 except for an active portion of the array 390, for example array 322, row decoder 323, column decoder 324, high voltage decoder 344, and power source 325 and 343; data out circuit 351; test mode circuit 352; trimbits circuit 354; data in circuit 356; analog high voltage circuit 360;high voltage generation circuit 362; and non- volatile operation controller circuit 363.

Circuits used to assist in the power down mode are described below.

[0045] During a standby operation of die 300, the following portions remain powered on: array 322; row decoder 323; column decoder 324; high voltage decoder 344; power source 343; power source 325; trimbits-live circuit 353; command decoder circuit 355; power sequence controller 357; pin interface 358; analog low voltage circuit 359; low voltage generation circuit 361; and GPS circuit 364.

[0046] ACTfVE READ [0047] An active read mode can be implemented on die 300 when data from the array 390 is needed from a system controller (not shown). A read command is executed to the pin interface 358 from the system controller.

[0048] During an active read operation of die 300, the following portions are powered down: memory section 390 except for array 322 (as example data is needed from this array plane), row decoder 323, column decoder 324, power sources 325 and 343, high voltage decoder WSHDR 344; test mode circuit 352; trimbits circuit 354; data in circuit 356; analog high voltage circuit 360; high voltage generation circuit 362; and non- volatile operation controller circuit 363. Circuits used to assist in the power down mode are described below.

[0049] During an active read operation of die 300, the following portions remain powered on: array 322; row decoder 323; column decoder 324; power sources 325 and 343; data out circuit 351; trimbits-live circuit 353; command decoder circuit 355; power sequence controller 357; pin interface 358; analog low voltage circuit 359; low voltage generation circuit 361; and GPS circuit 364.

[0050] TEST MODE

[0051] A test mode can be implemented on die 300 when a designer, manufacturer, or other personnel wishes to test die 300.

[0052] During a test mode of die 300, the following portions are powered down: memory section 390, data out circuit 351; data in circuit 356; analog low voltage circuit 359; analog high voltage circuit 360; low voltage generation circuit 361; high voltage generation circuit 362; and nonvolatile operation controller circuit 363. Circuits used to assist in the power down mode are described below. [0053] During a test mode of die 300, the following portions remain powered on: test mode circuit 352; trimbits-live circuit 353; trimbits circuit 354; command decoder circuit 355; power sequence controller 357; pin interface 358; and GPS circuit 364.

[0054] NQN- VOLATILE OPERATION

[0055] Non-volatile operation is the normal operation mode for die 300. In such mode, normal erase, program, and read operations can occur.

[0056] During non-volatile operation of die 300, the following portions are powered down: memory section 390 except for a selected portion of the array 390, as example for array 322, row decoder 323, column decoder 324, power sources 325 and 343, high voltage decoder WSHDR 344; data out circuit 351; and test mode circuit 352. Circuits used to assist in the power down mode are described below.

[0057] During non-volatile operation of die 300, the following portions remain powered on: a selected portion of the array 390 as example array 322; row decoder 323; column decoder 324; high voltage decoder 344; power sources 325 and 343; trimbits-live circuit 353; trimbits circuit 354; command decoder circuit 355; data in circuit 356;power sequence controller 357; pin interface 358; analog low voltage circuit 359; analog high voltage circuit 360; low voltage generation circuit 361; high voltage generation circuit 362; non-volatile operation controller circuit 363; and GPS circuit 364.

[0058] CIRCUITS FOR POWER DOWN

[0059] Figures 4A, 4B, 5 A, and 5B depict NAND and INVERTER power save gate circuits used during a power down of various portions of die 300 as discussed above. The gate circuits in Figure 4A/4B and 5A/5B ensure that the output is known '0' or T state in power down mode respectively. Other circuit embodiments for other type of gate circuits such as NOR, XOR, complex gate are similar. [0060] Figure 4 A depicts pull down 2-input NAND gate circuit 401. Pull down gate circuit 401 pulls output node 441 down to a "0" state (such as a ground voltage) during a power down mode. During the power down mode, switch 421 is opened (off) , this dis-connecting node 411 (top power supply) to node 451 (local power supply) of the circuit 431. Device 461 (an additional device to 2-input NAND gate) is turned on by a power down signal to pull node 441 to a "0" state.

[0061] Figure 4B depicts pull down INVERTER circuit 402. Pull down circuit 402 pulls node 442 down to a "0" state (such as a ground voltage) during a power down mode. During the power down mode, switch 422 is opened (off) , thus dis-connecting node 412 (top power supply) to node 452 (local power supply) of the circuit 432. Device 462 (an additional device to an inverter) is turned on by a power down signal to pull node 442 to a "0" state.

[0062] Figure 5 A depicts pull up 2-input NAND circuit 501. Pull up circuit 501 pulls node 541 to a "1" state (such as a Vdd voltage) during a power down mode. During the power down mode, switch 521 is opened (off) , thus dis-connecting node 511 (top ground node) to node 551 (local ground node) of the circuit 531. Device 561 is turned on by a power down signal to pull node 541 up to a "1" state.

[0063] Figure 5B depicts pull up INVERTER circuit 502. Pull up circuit 502 pulls node 542 to a "1" state (such as a Vdd voltage) during a power down mode. During the power down mode, switch 522 is opened (off) , thus dis-connecting node 512 (top ground node) to node 552 (local ground node) of the circuit 532. Device 562 is turned on by a power down signal to pull node 542 up to a "1" state.

[0064] SELECTION-DECODING CIRCUITS

[0065] Figures 6A, 6B, 7 A, 7B, 8 A, and 8B depicts various embodiments of selection-decoding circuits that can operate in a low-power shutdown mode. [0066] Figure 6 A depicts selection-decoding circuit 600, which comprises NAND gate 601 and inverters 602, 603, and 604 and is shown in symbolic fashion.

[0067] Other selection-decoding and block circuits similar to those in Figure 6A, 6B.7A, 7B, 8 A, 8B, and 9 employing other type of gate circuits such as NOR and/or complex gate are

implemented in similar fashion.

[0068] Figure 6B depicts selection-decoding circuit 600 at a transistor level. During a power down event, it is desired to "save" (hold) the output values of NAND gate 601 and inverters 602, 603, and 604 even while the power source VDD and ground GND are turned off, using power save gate circuit techniques as in Figure 4 A, 4B, 5 A, and 5B. NAND gate 601 and inverter 603 is similarly to power gate pull up circuit 501 and pull up circuit 502. Inverter gate 602 and inverter 604 is similarly to power gate pull down circuit 401 and pull down circuit 402. Thus NAND gate 601 is coupled to top ground node 630through switch 631, which can be a form of switch 521 or switch 522 in Figures 5 A and 5B, in the manner shown in Figure 6B. Node 630 (top ground line), which is coupled to ground power-save line 620 (also labeled as GND_PS) corresponds to node 511 or node 512 in Figures 5 A and 5B. When switch 631 is opened (off) , the output of NAND 601 will be a "1" and will remain in that state while switch 631 is opened . Inverter 603 also is coupled through the switch 631 to ground power-save line 620 and will output a "1" during the power down mode. Thus, during a power down event, the outputs of NAND gate 601 and inverter 603 will be pulled up to a "1" state.

[0069] During the power down event, inverter 604 is coupled to top power supply line node 640 through switch 641, which can be a form of switch 421 or switch 422 in Figures 4 A and 4B.

Node 640, which is coupled to VDD power-save line 611 (also labeled as VDD_PS) corresponds to node 411 or node 412 in Figures 4A and 4B. Pulling VDD power-save line 611 to a "0" state will cause the output of inverter 604 to be "saved" as a "0." Inverter 602 also is coupled to VDD power-save line 611 and will have its output "saved" as a "0." Thus, during a power down event, the outputs of inverters 602 and 604 will be pulled down to a "0" state.

[0070] Figure 7 A depicts selection-decoding circuit 700, which comprises NAND gate 701 and inverters 702, 703, and 704 and is shown in symbolic fashion. NAND gate 701 and inverter 703 is similarly to power gate pull up circuit 501 and pull up circuit 502 (except no device 562 as in Figure 5B). Inverter gate 702 and inverter 704 is similarly to power gate pull down circuit 401 and pull down circuit 402 except there is no device 562 as Figure 5B. Basically the circuit 700 only needs first power gate circuit (NAND 701) to have an additional device (device 561 in Figure 5A).

[0071] Figure 7B depicts selection-decoding circuit 700 at a transistor level. During a power down event, it is desired to "save" the output values of NAND gate 701 and inverters 702, 703, and 704 even while the power source VDD and ground GND are turned off. Thus NAND gate 701 is coupled to the top ground line node 730 through switch 731, which can be a form of switch 521 or switch 522 in Figures 5 A and 5B, in the manner shown in Figure 7B. Node 730, which is coupled to ground power-save line 720 (also labeled as GND_PS) corresponds to node 511 or node 512 in Figures 5A and 5B. When switch 731 is opened (off) , the output of NAND 701 will be a "1" and will remain in that state while switch 731 is closed. Inverter 703 also is coupled to ground power-save line 720 and will output a "1" during the power down mode. Thus, during a power down event, the outputs of NAND gate 701 and inverter 703 will be pulled up to a "1" state.

[0072] During the power down event, inverter 704 is coupled to top power supply line node 740 through switch 741, which can be a form of switch 421 or switch 422 in Figures 4 A and 4B.

Node 740, which is coupled to VDD power-save line 711 (also labeled as VDD_PS) corresponds to node 411 or node 412 in Figures 4A and 4B. Pulling VDD power-save line 711 to a "0" state will cause the output of inverter 704 to be "saved" as a "0." Inverter 702 also is coupled to VDD power-save line 711 and will have its output "saved" as a "0." Thus, during a power down event, the outputs of inverters 702 and 704 will be pulled down to a "0" state.

[0073] Figure 8 A depicts selection-decoding circuit 800, which comprises NAND gate 801 and inverters 802, 803, and 804 and is shown in symbolic fashion.

[0074] Figure 8B depicts selection-decoding circuit 800 at a transistor level. During a power down event, it is desired to "save" the output values of NAND gate 801 and inverters 802, 803, and 804 even while the power source VDD and ground GND are turned off. Thus NAND gate 801 is coupled to top ground line node 830 through switch 831, which can be a form of switch 521 or switch 522 in Figures 5 A and 5B, in the manner shown in Figure 8B. Node 830, which is coupled to (local) ground power-save line 820 (also labeled as GND_PS) corresponds to node 511 or node 512 in Figures 5A and 5B. When switch 831 is opened , the output of NAND 801 will be a "1" and will remain in that state while switch 831 is opened . Inverter 803 also is coupled to ground power-save line 820 and will output a "1" during the power down mode. Thus, during a power down event, the outputs of NAND gate 801 and inverter 803 will be pulled up to a "1" state.

[0075] During the power down event, inverter 804 is coupled to top power supply line node 840 through switch 841, which can be a form of switch 421 or switch 422 in Figures 4 A and 4B. Node 840, which is coupled to (local) VDD power-save line 811 (also labeled as VDD_PS) corresponds to node 411 or node 412 in Figures 4A and 4B. While switch 841 is opened (off), the output of inverter 804 to be "saved" as a "0." Inverter 802 also is coupled to VDD power- save line 811 and will have its output "saved" as a "0." Thus, during a power down event, the outputs of inverters 802 and 804 will be pulled down to a "0" state. [0076] Figure 8B also depicts bulk line 850 (also labeled as NWBULK), which provides a common bulk voltage for certain transistors in NAND gate 801 and inverters 802, 803, and 804, as shown in Figure 8B. Implementation for bulk bias modulation to minimize power consumption and to maximize performance is as following. Voltage bias on the bulk line 850 is higher than the power supply VDD in power down or stand by mode to reduce leakage and lower than or equal to VDD in active mode to enhance gate current drive.

[0077] TEST MODE CIRCUIT

[0078] Figure 9 depicts test mode circuit 900, which comprises pass gates 901, 904, 907, and 908; NAND gates 902 and 905, and inverters 903 and 906 as shown. During a power down operation, the output of NAND gates 902 and 905 are pulled up to a "1" using ground power-save line 920 (also labeled as GND_PS), power save gate pull-up circuit 501 or pull-up circuit 502 (circuit technique of Figures 4A, 4B, 5 A, and 5B ) and the selection-decoding power save circuit techniques of Figures 6A, 6B, 7A, 7B, 8A, and/or 8B. During the power down operation, the output of inverters 903 and 906 are pulled down to a "0" using VDD power-save line 910 (also labeled as VDD_PS), power save gate pull-down circuit 401 or pull-down circuit 402( circuit technique of Figures 4 A, 4B, 5 A, and 5B), and the techniques of Figures 6 A, 6B, 7 A, 7B, 8 A, and/or 8B.

[0079] GPS CIRCUIT

[0080] Figure 10 depicts global power switch circuit 1000, which comprises PMOS transistor 1010 and NMOS transistor 1020 connected in the manner shown. Output VDD_IP will be the same as input VDD_SYS when the signal ENB_VDD_IP is low. Output VDD_IP will be pulled down to VDD_IP_LOW when the signal DIS_VDD_IP is high.

[0081] LOCAL POWER SWITCH CIRCUIT [0082] Figure 11A depicts local power switch 1101, which comprises a PMOS transistor as shown. Output VDD_PS will be same as input VDD_SYS when the signal ENB_VDD_PS is low.

[0083] Figure 11B depicts local power switch 1102, which comprises an NMOS transistor as shown. Output GND_PS will be pulled down to low (e.g., ground) when the signal EN_GND_PS is high.

[0084] ROW DECODER

[0085] Figure 12 depicts power save row decoder 1200. Row decoder 1200 comprises NAND gate 1201, inverter 1202, and circuit blocks 1203, 1204, 1213, and 1214. The circuit block 1203 includes PMOS 1203 A, PMOS 1203C and NMOS 1203B. The circuit block 1204 includes PMOS 1204 A and NMOS 1204B. The circuit blocks 1213 and 1214 are similar to circuit block 1203 and 1204 respectively, During a power down operation, the outputs of NAND gate 1201 and circuit blocks 1203 and 1213 are pulled up to a "1" using power save pull-up circuit 501 or pull- up circuit 502, and the techniques of Figures 6A, 6B, 7A, 7B, 8A, and/or 8B, and the outputs of inverter 1202 and circuit blocks 1204 and 1214 are pulled down to a "0" using power save pulldown circuit 401 or pull-down circuit 402, and the techniques of Figures 6 A, 6B, 7 A, 7B, 8 A, and/or 8B. During a power down operation, power supply ZVDD 1230 can be shut down, which results in overall power savings. During a power down operation, node 1240 and 1241 are biased at a high voltage T so that voltage between source and drain of transistors 1203C and 1203B is the same, which results in overall power savings. During a power down operation, node nwell 1250 can be biased at a high voltage > ZVDD2 1220 and ZVDD 1230 to increase reverse bulk- source voltage leading to increase threshold voltage for PMOS 1203A and 1204A, which results in overall power savings.

[0086] SENSING CIRCUIT [0087] Figure 13 depicts sensing circuit 1300, which comprises comparator 1301, PMOS transistor 1302, NMOS transistor 1303, and selected memory cell 1304. The NMOS 1303 couples between the memory cell 1304 and the comparator 1301. The positive input of comparator

1301 is the node between PMOS transistor 1302 and NMOS transistor 1303, and the negative input of comparator 1301 is a reference voltage bias signal. The PMOS 1302 coupled to a high power supply is biased by a leakage current such as to compensate for array bit line leakage and/or leakage due to decoding path (such as from transistor direct gate tunneling current or junction). Thus, no reference memory cell is used for reading data from the selected memory cell

1304. In this mode, the effective reference for read sensing is basically ground reference level

(zero current level), meaning the memory cell current window (difference between high (erased) and low (programmed) current level) has been shifted towards ground level. Meaning the low current level is shifted under the ground level. This can be implemented such as by biasing memory cell coupling gate at zero or negative voltage, and/or by very deep programming such as with higher programming voltage and/or with larger programming current and/or with longer programming time, and/or by biasing read bit line voltage at a low level.

[0088] Figure 14 depicts a circuit 1400 for method of sampling a reference current ( or a reference cell voltage) for a sensing operation, whereby a sampling current mirror (or a voltage) instead of a continuous current mirror ( or a voltage) will be used, resulting in power savings.

Circuit 1400 comprises sampling PMOS transistor 1401, sampling switches 1402 and 1405, enabling NMOS transistor 1403, reference element 1404 (which can be a resistor, memory cell, transistor, or other element), reference holding capacitor 1406 (this can be optional), floating hold node 1410 VREFBIAS (on terminal of the capacitor) and sensing pull up PMOS transistor 1407

(as part of sensing circuitry per selected bit line) as shown. The sampling interval is for example

0.2us per 0.2ms, hence effectively the effective power consumption from the reference current 1404 is reduced by a ratio of -2/2000. The transistor 1401, 1402, 1403, 1404, 1405 are off during reference hold period (not sampling) and on during sampling period to sample bias on the reference element 1404 into the floating hold node 1410. The reference 1504 can be generated by as switching cap circuit (Req = l/R*Freq).

[0089] Figure 15 depicts a circuit 1500 for sampling a reference current (or a reference cell voltage) for a sensing operation, whereby a sampling current mirror (or a voltage) instead of a continuous current mirror ( or a voltage) will be used, resulting in power savings. Circuit 1500 comprises sampling PMOS transistor 1501, sampling switches 1502 and 1505, enabling NMOS transistor 1503, reference element 1504 (which can be a resistor, memory cell, transistor, or other element), reference holding capacitor 1506, a floating hold node 1510 (on terminal of the capacitor 1506) operational amplifier 1507, and sensing pull up PMOS transistor 1508 (as part of sensing circuitry per selected bit line) as shown. The sampling interval is for example 2us per 0.2ms, hence effectively the effective power consumption from the reference current 1504 is reduced by a ratio of -2/200. The transistor 1501, 1502, 1503, 1504, 1505 are off during reference hold period (not sampling) and on during sampling period to sample bias on the reference element 1504 into the floating hold node 1510. The op amp 1507 is used to drive the hold reference bias (voltage on capacitor 1506) into the gate of multiple of sensing transistor 1508.

[0090] READ PATH

[0091] Figure 16 depicts a read decoding path modulation embodiment of a flash memory system 1600 during a read operation to save power. Flash memory system 1600 implements a features that result in overall power savings, specifically, a sense operation does not occur if the same address is being read as was read during the previous cycle.

[0092] The read address for the current read operation is placed in buffer 1602. The address for the prior read operation is placed in buffer 1601. Comparator 1603 compares the address stored in buffer 1601 and the address stored in buffer 1601. If they are the same address, then an enable signal is sent to buffer 1608, which outputs the same output data as during the prior operation. If they are different addresses, then a read enable signal is sent to row decoder 1605 and column decoder 1606, and a normal read operation will occur in array 1604 using sensing circuit 1607. In another embodiment, if data out from sensing 1607 is same as that held in data out circuit 1608, then no DOUT switches which results in saving power in no DOUT switching.

[0093] ADDRESS/DATA ENCODING/DECODING/SCRAMBLING

[0094] In a method of saving power by encoding/decoding/scrambling address and/or data, certain addressing and/or data accessing method are used to save power. In an embodiment for address encoding/decoding/scrambling, the consecutive word sequence is read consecutively with consecutive addressing (address incrementing) on the column (bit line) direction for N number of words starting at a selected row and selected columns. Such as following: word 1-4 are on rowl-4 consecutively, next word2-8 are on rowl-4 consecutively for next selected columns, and this keep repeating. For this example an array unit sector includes four rows. In another embodiment for data encoding/decoding/scrambling, a mostly '0' state are used, meaning T data majority in a word will be converted to mostly '0' data in a word before storage. Other address scrambling are embodied such as by scrambling column addresses. Other address scrambling are possible such as by switching higher order row addresses ordering.

[0095] POWER GATE TYPES

[0096] Figure 17 depict various gate symbols and various configurations.

[0097] The first row depicts NOR gate 1701, NAND gate 1702, and inverter 1703 as standard gates.

[0098] The second row depicts NOR gate 1701, NAND gate 1702, and inverter 1703 with a voltage source of VDDin and a ground of GNDin. [0099] The third row depicts NOR gate 1701, NAND gate 1702, and inverter 1703 with a voltage source of VDDin.

[00100] The fourth row depicts NOR gate 1701, NAND gate 1702, and inverter 1703 with a ground of GNDin.

[00101] The fifth row depicts NOR gate 1701, NAND gate 1702, and inverter 1703 with a voltage source of VDDin and connected to pull down circuit 401 or pull down circuit 402 to drive the output of the device to "0."

[00102] The sixth row depicts NOR gate 1701, NAND gate 1702, and inverter 1703 with a voltage source of VDDin and connected to pull up circuit 501 or pull up circuit 502 to drive the output of the device to "1."